CN115020245A - Chip suspension packaging manufacturing method and packaging structure - Google Patents
Chip suspension packaging manufacturing method and packaging structure Download PDFInfo
- Publication number
- CN115020245A CN115020245A CN202210944260.9A CN202210944260A CN115020245A CN 115020245 A CN115020245 A CN 115020245A CN 202210944260 A CN202210944260 A CN 202210944260A CN 115020245 A CN115020245 A CN 115020245A
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- chip
- pin
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- substrate
- front surface
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 239000000725 suspension Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000047 product Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 239000011265 semifinished product Substances 0.000 claims abstract description 3
- 230000007704 transition Effects 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 2
- 230000001070 adhesive effect Effects 0.000 claims 2
- 230000017525 heat dissipation Effects 0.000 abstract description 20
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000001815 facial effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a chip suspension packaging manufacturing method and a chip suspension packaging structure, and belongs to the field of semiconductor packaging. Aiming at the problems of poor heat dissipation, complex process flow and high cost of the existing packaged chip in the prior art, the invention provides a chip suspension packaging manufacturing method and a packaging structure, and the chip suspension packaging manufacturing method comprises the following steps: etching the front surface of the substrate to form a pit base island and expose a front surface pin; arranging a radiating fin in the pit base island; installing a chip on the heat dissipation sheet; connecting the chip with the front pin; encapsulating the frame formed in the step and forming an encapsulating layer on the front surface; etching the back surface of the frame after being packaged to form an etching area, wherein the back surface of the radiating fin is exposed; back pins are formed on the periphery of the back of the substrate; electroplating metal on the back pin; and cutting the semi-finished product to form a single product. The chip heat dissipation structure can ensure that the chip has better heat dissipation, has simple process and can reduce the cost.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a chip suspension packaging manufacturing method and a chip suspension packaging structure.
Background
For decades, the technology of packaging integrated circuits has been developed following the development of integrated circuits, and people have sought the best balance between small size and high performance. The integrated circuit packaging is that an integrated circuit bare chip is placed on a frame substrate which plays a bearing role, then a pin is led out, and then the integrated circuit bare chip is fixedly packaged to form a packaging body, wherein the packaging body can play a role in protecting a chip, is equivalent to a shell of the chip, and not only can fix and seal the chip, but also can enhance the electric heating performance of the chip. Because the packaging body is smaller and is more dense, the heat dissipation of the chip is very important, and how to ensure better heat dissipation after packaging is very important, the existing high-voltage-resistant packaging mostly adopts a PCB (printed circuit board) or ceramic substrate packaging technology. However, the cost of the PCB or the ceramic substrate is high, and the chip is not favorable for heat dissipation of the product because the chip is fully enclosed in the package.
The prior art also has a related technology for assisting heat dissipation, such as chinese utility model patent, application No. 201921500622.5, published 2020, 3 and 20, disclosing a packaging structure with suspended bottom. The chip is fixed on the base island, the base island and the chip are wrapped by the plastic package body, the lower surface of the pin is flush with the lower surface of the plastic package body, and a suspension cavity is formed in the bottom surface of the plastic package body. After the PCB is welded, the bottom surface of the suspension cavity is not contacted with the PCB, but a certain gap is formed, so that air flow is facilitated, heat exchange between the bottom of the product and the outside is improved, heat dissipation performance of the bottom surface of the product is improved, direct heat transfer of a packaged product to the PCB is reduced, circuit abnormity or signal instability of the PCB caused by direct contact heat transfer is avoided, and the abnormal problem of the PCB caused by full contact heat dissipation of the bottom of the product is solved; after the product is heated, the product is stressed and deformed due to different thermal expansion coefficients of different materials, and the flatness problem caused by product deformation can be offset due to the suspended structure at the bottom of the product, so that abnormal welding can not occur during high-temperature welding. However, the direct suspension scheme has a complex structure and a complex process flow, and is high in cost and not suitable for industrialization for chips produced in large scale.
Disclosure of Invention
1. Technical problem to be solved
Aiming at the problems of poor heat dissipation, complex process flow and high cost of the existing packaged chip in the prior art, the invention provides a chip suspension packaging manufacturing method and a chip suspension packaging structure, which can ensure better heat dissipation of the chip, have simple process and can reduce the cost.
2. Technical scheme
The purpose of the invention is realized by the following technical scheme:
a chip suspension packaging manufacturing method comprises the following steps:
etching the front surface of the substrate to form a pit base island and expose a front surface pin;
arranging a radiating fin in the pit base island;
installing a chip on the heat dissipation sheet;
connecting the chip with the front pin;
encapsulating the frame formed in the step and forming an encapsulating layer on the front surface;
etching the back surface of the frame after being packaged to form an etching area, wherein the back surface of the radiating fin is exposed; back pins are formed on the periphery of the back of the substrate;
electroplating metal on the back pin;
and cutting the semi-finished product to form a single product.
Furthermore, the size of the pit base island is not smaller than the size of the heat sink and the chip.
Furthermore, the heat sink is not smaller than the size of the chip.
Furthermore, a transition area is arranged between the bottom of the pit base island and the front pin, and the transition area is an inclined plane or an arc surface.
Furthermore, a vertical surface is formed between the bottom of the pit base island and the front pin.
Furthermore, the radiating fins are ceramic plates.
Furthermore, a layer of non-conductive glue is brushed in the pit base island, then a radiating fin is installed, and the non-conductive glue is solidified through baking.
Furthermore, a transition area is arranged between the etching area and the back pin, and the transition area is a bevel or a cambered surface.
Furthermore, a transition region is arranged between the etching region and the back pin, and the transition region is a vertical surface.
A chip suspension packaging structure comprises:
the front surface of the substrate is provided with a pit base island, a radiating fin is arranged on the pit base island, a chip is arranged on the radiating fin and is connected with a front surface pin through a lead, and the encapsulating layer encapsulates the front surface of the whole substrate;
the back of the substrate is an etching area, the back of the radiating fin is exposed in the etching area, the periphery of the back of the substrate is a back pin, and a metal coating is arranged on the back pin.
3. Advantageous effects
The invention obtains the packaging structure with the suspended bottom surface of the chip by the way of front surface curing and back surface etching, is particularly suitable for high-voltage chip products, has simple process flow, reduces the production cost and is more beneficial to the heat dissipation of the high-voltage chip products.
Drawings
FIG. 1 is a schematic view of the frame structure of the present invention;
FIG. 2 is a schematic structural view of the frame of the present invention after the frame is implanted with a supporting material;
FIG. 3 is a schematic view of the mounted structure of the present invention;
FIG. 4 is a schematic diagram of the structure after wire bonding according to the present invention;
FIG. 5 is a schematic diagram of the encapsulated structure of the present invention;
FIG. 6 is a schematic diagram of a structure after backside etching according to the present invention;
FIG. 7 is a schematic diagram of the post-electroplating structure of the present invention;
fig. 8 is a schematic view of a package back structure according to the present invention.
The reference numbers in the figures illustrate: 1. a substrate; 2. a heat sink; 3. a chip; 4. an encapsulation layer; 5. an etching region; 6. and (5) plating a metal layer.
Detailed Description
The invention aims to overcome the problems of complex process, great process difficulty and insufficient heat dissipation of a chip, and designs a novel packaging structure and a process method;
a packaging structure is composed of a substrate and a substrate,
as shown in fig. 1, a substrate 1 is taken, the substrate 1 mainly plays a role in bearing and protecting a bare chip (die) before packaging, electrically connecting the bare chip (die) and a circuit board, the substrate 1 is generally made of copper, the thickness of the substrate is not limited, the substrate is selected according to requirements, the corresponding size of the substrate is selected according to the size of a required chip, and after the chip is packaged, the substrate is cut subsequently. The substrate 1 is etched to form a front pin and a pit base island. The bottom of the pit base island is a flat area, the size of which is not less than the size of the heat radiating fin 2 which is subsequently installed, and is at least greater than the size of the chip 3. There is certain transition between pit base island bottom and the front pin, forms certain inclined plane, or also can be direct etching, forms a perpendicular, the condition that only has certain inclined plane is shown in the figure to guarantee that can set up fin 2 and chip 3 smoothly in the follow-up pit base island. The formation of the corresponding pit-based islands can be achieved by etching, wherein etching refers to contacting metal with a chemical solution to achieve the effect of dissolution and corrosion and form pits.
As shown in fig. 2, the heat sink 2 is implanted in the pit base island, the heat sink 2 is generally made of high-pressure resistant materials such as ceramic sheets, and the heat sink 2 is fixed in the pit base island, specifically, the heat sink 2 can pass through the pit base island, a layer of non-conductive glue is arranged on the back of the material, then the heat sink 2 is installed, and the glue is cured by baking, so that the heat sink 2 is fixed. The size of the radiating fin is not larger than the smooth range of the bottom of the pit and larger than the size of the chip 3, and the length and the width of the radiating fin are ensured to be capable of smoothly installing the chip 3 in a follow-up smooth mode.
As shown in fig. 3, the chip 3 is mounted on the heat sink 2, and the chip may be fixed on the heat sink by ball bonding or other suitable methods, and it is necessary to ensure that the chip 3 is tightly attached to the heat sink 2 to ensure better heat transfer.
As shown in fig. 4, wire bonding is performed to electrically connect the front pin with the chip. The process steps are conventional in the prior art and are not described herein.
As shown in fig. 5, the whole package front surface is encapsulated to form an encapsulating layer 4, and the encapsulating layer 4 encapsulates the whole package front surface.
As shown in fig. 6, in the encapsulated structure, the area of the back surface of the heat sink 2 at the center of the back surface is etched to form an etching area 5, so as to ensure that the back surface of the heat sink 2 is exposed, the periphery of the etching area 5 is provided with back surface pins, and the bottom of the etching area is provided with the back surface of the heat sink 2, so as to ensure that the back surface of the heat sink 2 is exposed. There is a certain transition between the bottom of the etching area 5 and the back pin to form a certain inclined plane, or it can be etched directly to form a vertical plane, which is only the case of a certain inclined plane. The etching process is substantially the same as the front etching, and will not be described herein.
As shown in fig. 7, the etched back pins are provided with metal coatings 6 to ensure smooth subsequent point connection. The metal is silver, and the conductivity, corrosion resistance and wear resistance of the back pin can be enhanced through electroplating, so that the reliability of the product after being coated on the PCB is improved.
The completed frame is finally diced to form individual chips as shown in fig. 8. The invention has relatively simple structure, and the chip is in a suspended state after etching, thereby being more beneficial to the heat dissipation of high-voltage chip products.
According to the scheme, the chip is mounted on the radiating fin 2, the exposed radiating fin 2 is formed through back etching, and a single product is formed through encapsulation, etching, electroplating and cutting. The invention has relatively simple structure, and the chip is in a suspended state after etching, thereby being more beneficial to the heat dissipation of high-voltage chip products.
The packaging structure is provided with the radiating fin 2, the chip 3 is arranged on the front surface of the radiating fin 2, the chip 3 is electrically connected with the pins on the front surface, the front surface of the packaging structure is provided with the encapsulating layer 4, the back surface of the radiating fin 2 is the etching area 5, the back surface of the radiating fin 2 is exposed, the periphery of the etching area 5 on the back surface of the packaging structure is provided with the pins on the back surface, and the pins on the back surface are provided with the metal coatings 6.
Although the product of this scheme and prior art all are unsettled, but our use is the direct frame of metal itself, carry out the setting of fin on metal frame, through encapsulating earlier, the back facial features forms unsettled heat dissipation area, whole simple and reliable of technology has been guaranteed, and whole metal frame can guarantee that the electricity is connected more conveniently, and simple process, owing to add the setting of fin, and unsettled heat dissipation area's setting, in subsequent chip use, better heat dispersion has, different with the scheme in the comparison file, its structure is complicated, easy deformation, and our simple process, and owing to there is the regional setting of heat dispersion, whole back is not merely the pin position heat dissipation, pin position and unsettled region all can dispel the heat, its heat dispersion is more balanced, can guarantee more that the structure is difficult to change. The overall stability performance will also be better.
The invention and its embodiments have been described above schematically, without limitation, and the invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The representation in the drawings is only one of the embodiments of the invention, the actual construction is not limited thereto, and any reference signs in the claims shall not limit the claims concerned. Therefore, if a person skilled in the art receives the teachings of the present invention, without inventive design, a similar structure and an embodiment to the above technical solution should be covered by the protection scope of the present patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Several of the elements recited in the product claims may also be implemented by one element in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (10)
1. A chip suspension packaging manufacturing method comprises the following steps:
etching the front surface of the substrate (1) to form a pit base island and expose a front surface pin;
a radiating fin (2) is arranged in the pit base island;
a chip (3) is arranged on the radiating fin (2);
connecting the chip (3) with the front pin;
encapsulating the frame formed in the step and forming an encapsulating layer (4) on the front surface;
etching the back surface of the frame after being packaged to form an etching area (5), wherein the back surface of the radiating fin (2) is exposed; a back pin is formed at the periphery of the back of the substrate (1);
electroplating metal on the back pin;
and cutting the semi-finished product to form a single product.
2. The method for manufacturing the chip suspended package according to claim 1, wherein the size of the pit base island is not smaller than the sizes of the heat sink (2) and the chip (3).
3. The method for manufacturing the chip suspension package according to claim 2, wherein the size of the heat sink (2) is not smaller than that of the chip (3).
4. The method for manufacturing the chip suspension package according to claim 1, 2 or 3, wherein a transition region is arranged between the bottom of the pit base island and the front pin, and the transition region is an inclined plane or an arc surface.
5. The method of claim 1, 2 or 3, wherein a vertical plane is formed between the bottom of the recessed island and the leads on the front surface.
6. The method for manufacturing the chip suspension package according to claim 1, wherein the heat sink (2) is a ceramic sheet.
7. A method for manufacturing a chip suspension package according to claim 1 or 6, characterized in that a heat sink (2) is installed after a layer of non-conductive adhesive is brushed in the pit base island, and the non-conductive adhesive is cured by baking.
8. The method for manufacturing the chip suspension package according to claim 1, wherein a transition region is formed between the etching region (5) and the back pin, and the transition region is an inclined surface or an arc surface.
9. The method of claim 1, wherein a transition region is formed between the etching region (5) and the backside leads, and the transition region is a vertical surface.
10. A chip suspension packaging structure is characterized by comprising:
the LED packaging structure comprises a substrate (1), wherein a pit base island is arranged on the front surface of the substrate (1), a radiating fin (2) is arranged on the pit base island, a chip (3) is arranged on the radiating fin (2), the chip (3) is connected with a front surface pin through a lead, and an encapsulating layer (4) encapsulates the front surface of the whole substrate (1);
the back of the substrate (1) is an etching area (5), the back of the radiating fin (2) is exposed in the etching area (5), the periphery of the back of the substrate (1) is a back pin, and a metal coating (6) is arranged on the back pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210944260.9A CN115020245A (en) | 2022-08-08 | 2022-08-08 | Chip suspension packaging manufacturing method and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210944260.9A CN115020245A (en) | 2022-08-08 | 2022-08-08 | Chip suspension packaging manufacturing method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115020245A true CN115020245A (en) | 2022-09-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210944260.9A Pending CN115020245A (en) | 2022-08-08 | 2022-08-08 | Chip suspension packaging manufacturing method and packaging structure |
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| Country | Link |
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| CN (1) | CN115020245A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001024135A (en) * | 1999-07-07 | 2001-01-26 | Mitsui High Tec Inc | Manufacture of semiconductor device |
| US20130249077A1 (en) * | 2012-03-20 | 2013-09-26 | Byung Tai Do | Integrated circuit packaging system with terminals and method of manufacture thereof |
| US20190074242A1 (en) * | 2017-09-06 | 2019-03-07 | Shinko Electric Industries Co., Ltd. | Lead frame and method of manufacturing lead frame |
-
2022
- 2022-08-08 CN CN202210944260.9A patent/CN115020245A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001024135A (en) * | 1999-07-07 | 2001-01-26 | Mitsui High Tec Inc | Manufacture of semiconductor device |
| US20130249077A1 (en) * | 2012-03-20 | 2013-09-26 | Byung Tai Do | Integrated circuit packaging system with terminals and method of manufacture thereof |
| US20190074242A1 (en) * | 2017-09-06 | 2019-03-07 | Shinko Electric Industries Co., Ltd. | Lead frame and method of manufacturing lead frame |
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Application publication date: 20220906 |