TWI387080B - Qfn package structure and method - Google Patents

Abstract

A QFN semiconductor package structure, in which a chip with a plurality of metal contacts on its active surface is fixedly connected to the bottom surface of a metal base, the second surface of the metal substrate being provided with a concave in near-geometrical pattern; a plurality of metal wires are then provided for connecting the plurality of metal contacts on the chip to first surface of a plurality of metal pads; an encapsulant is subsequently provided for covering the chip, the metal wires, the first surface of the metal substrate and the first surface of the plurality of metal pads, and the second surface of the metal substrate and the second surface of the plurality of metal pads are exposed.

Description

Quad flat no-lead semiconductor package structure and packaging method

The present invention relates to a quad flat no-lead semiconductor package structure, and more particularly to a structure for forming a geometric pattern on a metal pedestal in a quad flat no-lead semiconductor package structure.

In the modern semiconductor packaging process, a wafer that has completed the Front End Process is first subjected to a thinning process, and the thickness of the wafer is ground to between 2 and 20 mils; Then, coating or printing a layer of polymer material on the back side of the wafer, the polymer material may be a resin (Epoxy), and then, a removable tape (tape) Attached to the semi-cured polymer material; then, the wafer is sawing process to make the wafer a single die; finally, the wafer can be connected to the substrate .

In many semiconductor package types, the Quad Flat Non-Lead (QFN) package structure is built into the package, so it can be closely attached to the external circuit board. The circuit board can have a small combined thickness, so the QFN package structure meets the requirements of "light, thin, short, and small" for electronic components, especially for portable devices. In addition, such a package structure with "light, thin, short, and small" can effectively save space.

First, please refer to FIG. 1A, which is a typical QFN package structure. The QFN package structure is to fix the wafer 11 to the wafer holder 15 in the lead frame, and the wafer holder 15 is provided with a plurality of internal leads. The height of the plurality of inner leads 12 is higher than the wafer holder 15 such that a height difference is formed therebetween, and the plurality of inner leads 12 are formed by a plurality of metal wires 13 and a plurality of metals on the active surface of the wafer. Contact connection. In this package structure, a plurality of inner pins 12 are front end degrees It is easy to fix, and it is easy to be bent when performing wire bonding of metal wires, thus reducing the reliability of the package structure.

Next, please refer to FIG. 1B, which is another typical QFN package structure, which is disclosed by U.S. Patent No. 5,942,794, which is mainly based on a lead frame and has a tie bar 16 at the four ends of the lead frame. Bending, so that it can support the wafer 11, so that the wafer 11 can be raised, the package 14 can be sealed to seal the wafer 11 and the inner leads 12, but the package structure increases the thickness of the package, and the inner leads 12 are flat. It is attached to the bottom surface of the package, so a long metal wire 13 is required to connect the wafer 11 and the inner lead 12. In addition to increasing the delay of the electronic signal, the metal wire 13 is also used to become soft due to too large cross-arc. Therefore, when the molding is performed, the metal wire 13 may be prevented from being displaced by the pressure of the mold flow, and the metal wire 13 in the package is short-circuited, so that the reliability of the package structure is also lowered.

Next, please refer to FIG. 1C, and another QFN package structure that does not use a lead frame is disclosed in US Pat. No. 6,372,539. This patent mainly defines a wafer holder 17 and a pin group 18 on a metal substrate by a half etch process, and then covers the wafer 11 and the metal wire 13 via a glue 14. Since many QFN package structures are used in small or portable electronic products, the thermal effects generated by electronic products affect the performance of the products, so heat dissipation is an important issue. The package structure of the QFN can improve the shortcomings of the QFN package structure mainly based on the lead frame, but also because the wafer holder 17 and the lead group 18 are on the same plane, so that they are completely flat on the outer circuit board. Therefore, heat dissipation is not good.

In view of the shortcomings and problems of the above QFN package structure, the present invention provides an approximate geometric pattern for forming an indentation or protrusion on the exposed surface of the wafer base, thereby increasing the heat dissipation area of the QFN package structure to effectively solve the QFN package. The problem of poor heat dissipation of the structure.

Accordingly, one of the main objects of the present invention is to provide a QFN package junction that can increase the heat dissipation area. Structure to effectively solve the problem of poor heat dissipation of the QFN package structure.

Another main object of the present invention is to provide a QFN packaging method capable of increasing heat dissipation area to effectively solve the problem of poor heat dissipation of the QFN package structure.

Still another main object of the present invention is to provide a QFN package structure which can increase the heat dissipation area, and is coated with an exposed metal pad by a plating layer to prevent oxidation of the etched metal pad.

According to the above object, the present invention firstly provides a quad flat no-lead semiconductor package structure, in which a wafer having a plurality of metal contacts on an active surface is fixed to a bottom surface of a metal base, and the metal base is On both sides, a dimple of approximate geometric pattern is arranged; then a plurality of metal wires are used to connect a plurality of metal contacts on the wafer to the first side of the plurality of metal pads; finally, a sealant is used The first surface of the metal substrate and the first surface of the plurality of metal pads are covered, and the second surface of the metal base and the second surface of the plurality of metal pads are exposed.

The present invention further provides a quad flat no-lead semiconductor package structure, in which a wafer having a plurality of metal contacts on an active surface is fixed to a bottom surface of a metal base; and then a plurality of metal wires are used to mount the wafer The plurality of metal contacts are connected to the first side of the plurality of metal pads; and then the first side of the wafer, the metal wire, the metal base, and the first surface of the plurality of metal pads are covered by a sealant And exposing the second side of the metal base and the second side of the plurality of metal pads; finally, fixing the second side of the metal base and the second side of the plurality of metal pads with a plating layer, wherein The plating on the second side of the metal base is an approximately geometric pattern.

The invention further provides a method for a quad flat no-lead semiconductor package, which provides a metal substrate having a first surface and a second side opposite to the first surface; forming a pattern on the metal substrate On the first side, a metal pedestal region and a plurality of metal pad regions are defined; then, the metal substrate is etched to form the metal pedestal region and the plurality of metal pad regions; and an active surface is disposed a plurality of metal contacts of the semiconductor wafer are attached to the metal pedestal region; forming a plurality of metal wires for bonding the plurality of metal contacts on the wafer to the plurality of metals The pad region is connected; then, the encapsulant is formed by molding to cover the first surface of the wafer, the metal wire, the first surface of the metal pedestal region and the plurality of metal pad regions, and the metal pedestal is exposed a second side of the board; then, etching the second side of the exposed metal substrate to separate the metal pedestal region from the plurality of metal pad regions to form a metal pedestal and a plurality of metal pads; The geometric pattern is on the second side of the metal base; finally, the metal base is etched and the geometric pattern is formed on the second side of the metal base.

The direction of the invention discussed herein is a QFN package structure and mode, so that the QFN package structure has better heat dissipation effect. In order to thoroughly understand the present invention, detailed steps and compositions thereof will be set forth in the following description. Obviously, the implementation of the present invention does not define the specific details familiar to those skilled in the art of the structure and manner of the QFN package. On the other hand, the detailed steps of the well-known wafer formation method and the wafer thinning process are not described in detail to avoid unnecessary limitation of the present invention. However, the preferred embodiments of the present invention will be described in detail below, but the present invention may be widely practiced in other embodiments and the scope of the present invention is not limited by the detailed description. The scope of the patents that follow will prevail.

First, please refer to FIGS. 2A to 2J, which are detailed manufacturing processes of one embodiment of the present invention. Please refer to FIG. 2A, which is a flat metal substrate 100. The material of the metal substrate 100 may be copper, aluminum or an alloy of the two. A suitable pattern is then attached to the surface of the metal substrate 100 (not shown), and then an etching process is performed to remove the metal substrate 100 that is not masked to define a metal pedestal region 102. And a plurality of metal pad regions 104; in this embodiment, first performing an approximate half etch, first removing a portion of the metal substrate 100 that is not masked by the pattern, that is, not completely Etch penetration, as shown in Figure 2B. After the half-etch process, the metal pedestal region 102 and the plurality of metal pad regions 104 can be defined in accordance with the pattern. Then, a plating process may be selectively performed on the metal pad region 104 to deposit a metal material on each of the metal pad regions 104. To form a metal layer 106, and the metal material of the metal layer 106 is selected from the following groups, including gold, silver, copper, tin, antimony, palladium or alloys thereof; after forming the metal layer 106, the subsequent When welding metal wires, it is easier to form solder joints, as shown in Figure 2C. Then, a semiconductor wafer 200 is fixed to the metal pedestal region 102 of the metal substrate 100 via an adhesive layer (not shown). The purpose of the adhesive layer is to bond the semiconductor wafer 200 and the metal pedestal region 102. Therefore, as long as it is an adhesive material having such a function, it is an embodiment of the present invention, for example, a die attached film or a semi-cured adhesive (i.e., B-Stage adhesive) as shown in Fig. 2D. Then, a wire bonding process is performed to electrically connect a plurality of metal contacts (not shown) on the semiconductor wafer 200 to the plurality of metal pad regions 104 of the metal substrate 100 by using a plurality of metal wires 108. The metal wires 108 may be soldered directly to the plurality of metal pad regions 104, or may be soldered to the metal layer 106 of the metal pad region 104, as shown in FIG. 2E. Then, an encapsulation process is performed to mold the wafer 200, the metal wires 108, and the metal pedestal region 102 by molding a polymer material or a resin body 300 formed by a resin material. The first side of the first face and the plurality of metal pad regions 104 are covered and cured into one body, as shown in FIG. 2F.

It is emphasized herein that the above described process of the present invention is described in terms of a unit of a semiconductor wafer 200 whose primary purpose is to disclose the features of the present invention. The actual fabrication process is to etch a single piece of metal substrate 100 in a pattern. The plurality of metal pedestal regions 102 and the plurality of metal pad regions 104 are formed, so that the semiconductor wafers 200 are also sequentially attached to the metal pedestal regions 102, so after the completion of the sealing process, the entire metal is completed. A plurality of encapsulants 300 are formed on the substrate 100. Therefore, the other side of the encapsulant 300 is still a flat metal layer.

Then, the metal substrate 100 of the entire encapsulation process is subjected to another etching process to remove the metal layer on the other side of the encapsulant 300, and a part of the metal has been removed due to the previous half etching process. The metal pedestal region 102 and the plurality of metal pad regions 104 are defined. Therefore, when the metal layer of the other surface (the second surface) is removed, the partially etched portion is naturally etched through. ), the metal pedestal region 102 and the plurality of metal pad regions 104 Completely separated, at the same time, a plurality of metal pad regions 104 are also separated to form separate pads, that is, a metal base 102' and a plurality of metal pads 104' are formed. Please refer to FIG. 2G. Obviously, after the second etching is completed, the metal substrate 102' and the second side 105 of the plurality of metal pads 104' are not covered by the encapsulant 300, that is, the metal layer is directly exposed or exposed. Finally, an isolation layer 400 having an approximate geometric pattern 401 is attached to the exposed surface of the metal pedestal 102' as shown in FIG. 2H. Then, an etching process is performed again to etch the approximate geometric pattern 600 on the second side of the metal pedestal 102', as shown in FIG. The approximate geometric pattern may be a parallel straight line, a concentric circle, a parallel curved curve, or other regular and irregular patterns. Obviously, the etched dimple pattern can increase the contact area with air, so when the package structure is placed on a portable computer (NB), the heat dissipation area of the QFN package structure can be increased. To effectively solve the problem of poor heat dissipation of the QFN package structure.

In the above process of forming an embodiment of the present invention, in order to enable the second etching process to be surely etched between the metal pedestal 102' and the plurality of metal pads 104' and the plurality of metal pads 104' It is etched for a period of time, and is completely etched through by over etching. Therefore, in order to maintain a flat coplanarity between the plurality of metal pads 104', a plating process may be selectively performed to form a metal plating layer 500 on the plurality of metal pads 104'. On the two sides 105, as shown in Figure 2J. In this way, in addition to maintaining a flat coplanarity of the etched metal pad 104', it is also possible to prevent oxidation of the plurality of metal pads 104' exposed after etching; in addition, the metal plating layer 500 also has a certain thickness. Therefore, when the QFN package structure is bonded to the external circuit board, the metal base 102' can be prevented from contacting the external circuit board, so that the entire metal base 102' and the approximate geometric pattern 600 thereon have a distance from the external circuit board. Therefore, the heat dissipation effect can be further increased. Of course, it is also possible to select on the approximate geometric pattern 600 of the metal pedestal 102', and a metal plating layer 500 is also plated by the electroplating process, which is not limited herein.

Figure 2J shows an idealized schematic diagram. In the process of implementation, since a wet etching process is selected, an etched non-isotropic etch is formed after etching. Under-cut traces, as shown in Figure 2K. However, since the metal substrate 100 is not very thick, the undercut trace is not obvious under the macroscopic view, especially when the etching depth of the geometric pattern is not large, the undercut trace is less noticeable. At the same time, the undercut trace is a phenomenon that is inevitable in the wet etching process, and is not a feature of the present invention, and thus is not described in detail herein.

Next, please refer to FIGS. 3A to 3E, which are schematic diagrams of a simplified process of another embodiment of the present invention. In this embodiment, a metal substrate 100 is etched in different patterns to define a metal pedestal region 102 and a plurality of metal pad regions 104; and may be selectively performed on the first side of the metal pad region 104. A primary plating process deposits a metal material on the first side of each of the metal pad regions 104 to form a metal layer 106, and then fixes a semiconductor wafer 200 to the metal of the metal substrate 100 via an adhesive layer. The first surface of the pedestal region 102 is followed by a plurality of metal wires 108 for electrically connecting a plurality of metal contacts on the semiconductor wafer 200 to the plurality of metal pad regions 104 of the metal substrate 100. Figure 2 is the same.

Then, a polymer material or a sealing material 300 formed of a resin material is molded along the sides of the plurality of metal pad regions 104 to mold the wafer 200, the metal wires 108, and the metal pedestal region. The first side of 102 and the first side of the plurality of metal pad regions 104 are covered and cured into one body, as shown in Figure 3A. Then, the metal substrate 100 of the entire encapsulation process is subjected to another etching process, and the partially etched portion of the metal substrate 100 is etched through, so that the metal pedestal region 102 and the plurality The metal pad regions 104 are completely separated, and the plurality of metal pad regions 104 are also separated to form separate pads, that is, a metal base 102' and a plurality of metal pads 104' are formed, as shown in FIG. 3B. Obviously, after the second etching is completed, the second side of the metal base 102' and the second side 105 and the third side 107 of the plurality of metal pads 104' are not covered by the encapsulant 300, That is, the second side 105 and the third side 107 of the plurality of metal pads 104' directly expose or expose the metal layer, and the second side 105 and the third side 107 of the metal pad 104' are connected together. Finally, an isolation layer 400 having an approximate geometric pattern 401 is attached to the second side of the metal base 102' and a plurality of metal pads 104'. The exposed portion of the second side 105 is as shown in Figure 3C. Then, an etching process is performed again to etch the approximate geometric pattern 600 on the second side of the metal pedestal 102' as shown in FIG. 3D. The approximate geometric pattern may be a parallel straight line, a concentric circle, a parallel curved curve, or other regular and irregular patterns. Obviously, the etched dimple pattern can increase the contact area with air, thereby increasing the heat dissipation area of the QFN package structure, so as to effectively solve the problem of poor heat dissipation of the QFN package structure.

In the above process of forming an embodiment of the present invention, in order to enable the second etching process to be surely etched between the metal pedestal 102' and the plurality of metal pads 104' and the plurality of metal pads 104' It is etched for a period of time and is ensured to be completely etched by over-etching. Therefore, in order to maintain a flat coplanarity between the plurality of metal pads 104', a plating process may be selectively performed to form a metal plating layer 500 on the plurality of metal pads 104'. On the two sides 105, as shown in Figure 3E. In this way, in addition to maintaining a flat coplanarity of the etched metal pad 104', it is also possible to prevent oxidation of the plurality of metal pads 104' exposed after etching; in addition, the metal plating layer 500 also has a certain thickness. Therefore, when the QFN package structure is bonded to the external circuit board, the metal base 102' can be prevented from contacting the external circuit board, so that the entire metal base 102' and the approximate geometric pattern 600 thereon have a distance from the external circuit board. Therefore, the heat dissipation effect can be further increased. Of course, it is also possible to select on the approximate geometric pattern 600 of the metal pedestal 102', and a metal plating layer 500 is also plated by the electroplating process, which is not limited herein.

Please refer to FIG. 4A and FIG. 4B for further simplified schematic diagrams of another embodiment of the present invention. In this embodiment, after the steps of FIGS. 2A to 2G are completed, the etching process is no longer used to etch the approximate geometric pattern on the metal base 102', but the layer has an approximate geometric pattern 401 and metal. The spacer layer 400 of the pad layer pattern 402 is directly attached to the exposed surface of the metal pedestal 102' and the plurality of metal pads 104', as shown in FIG. 4A. The electroplating process is then performed directly, the electroplated layer 500 is formed over the plurality of metal pads 104', and an approximate geometric pattern 600 of electroplating is formed on the metal pedestal 102', as shown in FIG. 4B. This approximate geometric pattern can It is a parallel straight line, a concentric circle, a parallel curved curve or other rules and irregular patterns. Obviously, the raised geometric pattern formed by the electroplating process can also increase the contact area with the air, so that the heat dissipation area of the QFN package structure can be increased to effectively solve the problem of poor heat dissipation of the QFN package structure.

Similarly, the present embodiment can also be directly attached to the metal base 102' by directly forming a spacer layer 400 having an approximate geometric pattern 401 and a metal pad layer pattern 402 after completing the steps of FIG. 3B. And an exposure surface of the plurality of metal pads 104'; then directly performing an electroplating process, forming a plating layer 500 over the plurality of metal pads 104', and forming an approximate geometric pattern of plating on the metal pedestal 102' As shown in Figure 5. The approximate geometric pattern may be a parallel straight line, a concentric circle, a parallel curved curve, or other regular and irregular patterns. Obviously, the raised geometric pattern formed by the electroplating process can also increase the contact area with the air, so that the heat dissipation area of the QFN package structure can be increased to effectively solve the problem of poor heat dissipation of the QFN package structure.

It will be apparent that the features of the present invention are comparable to prior art in that the wide metal layers of the prior art are miniaturized and are configured differently at the locations of the micrometal microstrips. Obviously, many modifications and differences may be made to the invention in light of the above description. It is therefore to be understood that within the scope of the appended claims, the invention may be The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Within the scope.

10‧‧‧QFN package structure (prior art)

11‧‧‧ wafer

12‧‧‧ inner pin

13‧‧‧Metal wire

14‧‧‧ Sealant

15‧‧‧ wafer holder

16‧‧‧The seat of the bulge

17‧‧‧ wafer holder

18‧‧‧ pin group

100‧‧‧Metal substrate

102‧‧‧Metal pedestal area

102'‧‧‧Metal base

104‧‧‧Metal pad area

104'‧‧‧Metal pad

105‧‧‧The second side of the metal pad

106‧‧‧metal layer

107‧‧‧The third side of the metal pad

108‧‧‧Metal wire

200‧‧‧ wafer

300‧‧‧ Sealant

400‧‧‧Isolation

401‧‧‧Geometric pattern

402‧‧‧Metal pad pattern

500‧‧‧Electroplating

600‧‧‧Geometric patterns

1A~1C are schematic diagrams of a prior art QFN package structure; 2A~2K are schematic diagrams showing a manufacturing process of the QFN package structure of the present invention; and 3A-3E are diagrams showing a manufacturing process of another QFN package structure of the present invention. ; 4A-4B are schematic views showing a manufacturing process of still another QFN package structure of the present invention; and FIG. 5 is a schematic view showing a manufacturing process of another QFN package structure of the present invention.

102'‧‧‧Metal base

104'‧‧‧Metal pad

106‧‧‧metal layer

108‧‧‧Metal wire

200‧‧‧ wafer

300‧‧‧ Sealant

500‧‧‧Electroplating

600‧‧‧Geometric patterns

Claims (34)

A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from any two sides of the metal base; a plurality of metal wires for the plurality of metal contacts on the wafer and the first of the plurality of metal pads a colloid, covering the wafer, the metal wire, the first side of the metal base and the first side of the plurality of metal pads, and exposing the second side of the metal base and the plurality of The second side of the metal pad. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from the four sides of the metal base; a plurality of metal wires are used for the plurality of metal contacts on the wafer and the first surface of the plurality of metal pads a colloid covering the wafer, the metal wire, the first side of the metal base, and the first side of the plurality of metal pads, and exposing the second side of the metal base and the plurality of metals The second side of the pad. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first side is fixed to the bottom surface of the active surface of the wafer; a plurality of metal pads having a first face and a second face opposite the first face and spaced apart from either side of the metal base; a plurality of metal wires for the plurality of wires on the wafer a metal contact is connected to the first surface of the plurality of metal pads; a gel covering the wafer, the metal wire, the first side of the metal base and the first side of the plurality of metal pads, And exposing the second side of the metal base and the second surface of the plurality of metal pads; a plating layer is fixed to the second side of the metal base and the plating layer is an approximate geometric pattern. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer; the plurality of metal pads have a first surface and a second surface opposite to the first surface and are arranged at four sides of the metal base a plurality of metal wires for connecting a plurality of metal contacts on the wafer to the first surface of the plurality of metal pads; a gel covering the wafer, the metal wires, and the metal base a first side and a first surface of the plurality of metal pads, and exposing a second side of the metal base and a second side of the plurality of metal pads; a plating layer fixed to the metal base The two sides and the plating layer are an approximate geometric pattern. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from any two sides of the metal base; a plurality of metal wires are used for the plurality of metal contacts on the wafer and the plurality of metal pads a first surface; a gel covering the wafer, the metal wire, the first side of the metal base and the first side of the plurality of metal pads, and exposing the second side of the metal base and the The second side and the third side of the plurality of metal pads. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from the four sides of the metal base; a plurality of metal wires are used for the plurality of metal contacts on the wafer and the first surface of the plurality of metal pads a colloid covering the wafer, the metal wire, the first side of the metal base, and the first side of the plurality of metal pads, and exposing the second side of the metal base and the plurality of metals The second side and the third side of the pad. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer; the plurality of metal pads have a first surface and a second surface opposite to the first surface and are spaced apart from any two of the metal bases a plurality of metal wires for connecting the plurality of metal contacts on the wafer to the first surface of the plurality of metal pads; a gel covering the wafer, the metal wires, and the metal base a first side and a first side of the plurality of metal pads, and exposing a second side of the metal base and a second side of the plurality of metal pads and a third surface; a plating layer fixed to the second side of the metal base and the plating layer is an approximate geometric pattern. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer; the plurality of metal pads have a first surface and a second surface opposite to the first surface and are arranged at four sides of the metal base a plurality of metal wires for connecting a plurality of metal contacts on the wafer to the first surface of the plurality of metal pads; a gel covering the wafer, the metal wires, and the metal base a first side and a first surface of the plurality of metal pads, and exposing a second side of the metal base and a second side and a third side of the plurality of metal pads; a plating layer fixed to the metal The second side of the pedestal and the plating layer is an approximate geometric pattern. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from any two sides of the metal base; a plurality of metal wires for the plurality of metal contacts on the wafer and the first of the plurality of metal pads a colloid, covering the wafer, the metal wire, the first side of the metal base and the first side of the plurality of metal pads, and exposing the second side of the metal base and the plurality of a second surface of the metal pad; a plating layer fixed to the second surface of the plurality of metal pads. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from the four sides of the metal base; a plurality of metal wires are used for the plurality of metal contacts on the wafer and the first surface of the plurality of metal pads a colloid covering the wafer, the metal wire, the first side of the metal base, and the first side of the plurality of metal pads, and exposing the second side of the metal base and the plurality of metals a second side of the solder pad; an electroplated layer fixed to the second side of the plurality of metal pads. A quad flat no-lead semiconductor package structure comprising a wafer having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second side opposite to the first surface The first surface is fixed to the bottom surface of the active surface of the wafer, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and a relative surface a second surface of the first surface is spaced apart from any two sides of the metal base; a plurality of metal wires for the plurality of metal contacts on the wafer and the first of the plurality of metal pads a colloid, covering the wafer, the metal wire, the first side of the metal base and the first side of the plurality of metal pads, and exposing the second side of the metal base and the plurality of a second surface and a third surface of the metal pad; a plating layer fixed to the second surface of the plurality of metal pads. A quad flat no-lead semiconductor package structure, including a chip having a plurality of metal contacts disposed on an active surface thereof; a metal base having a first surface and a second surface opposite to the first surface, the first surface and the active surface opposite to the wafer The bottom surface is fixed, and the second surface of the metal base is provided with an indentation of an approximate geometric pattern; the plurality of metal pads have a first surface and are spaced apart from the second surface of the first surface On the four sides of the metal base; a plurality of metal wires for connecting the plurality of metal contacts on the wafer to the first surface of the plurality of metal pads; a gel covering the wafer, the a metal wire, a first side of the metal base and a first side of the plurality of metal pads, and exposing a second side of the metal base and a second side and a third side of the plurality of metal pads; The plating layer is fixed to the second surface of the plurality of metal pads. The package structure of claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the wafer and the metal base are fixed by an adhesive layer . The package structure of claim 13, wherein the adhesive layer is a polymer material. The package structure of claim 13, wherein the adhesive layer is a B-Stage material. The package structure as described in claim 3, 4, 7, 8, 9, 10, 11 or 12, wherein the material of the plating layer is selected from the group consisting of gold, silver, copper, tin, antimony, Palladium or its alloy. The package structure of claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the sealant is a resin material. The package structure as described in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the second surface of the plurality of metal pads is further configured a metal layer. The package structure of claim 18, wherein the material of the metal layer is selected from the group consisting of gold, silver, copper, tin, antimony, palladium or alloys thereof. Such as the application of the patent scope 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12 The structure is characterized in that the metal base and the material of the plurality of metal pads are copper, aluminum or alloys thereof. A package structure as described in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the approximate geometric pattern is selectable from the group consisting of: a parallel straight line Concentric circles, parallel curved curves. A method of a quad flat no-lead semiconductor package, comprising: providing a metal substrate having a first side and a second side opposite to the first side; forming a pattern on the first side of the metal substrate Forming a metal pedestal region and a plurality of metal pad regions; etching the metal substrate to form the metal pedestal region and the plurality of metal pad regions; attaching a wafer to the metal a plurality of metal contacts are disposed on the susceptor region; a plurality of metal wires are formed for connecting the plurality of metal contacts on the wafer to the plurality of metal pad regions; forming a gel body Coating the wafer, the metal wire, the first side of the metal pedestal region and the first surface of the plurality of metal pad regions by a molding method, and exposing the second surface of the metal substrate; Etching the second side of the exposed metal substrate to separate the metal pedestal region from the plurality of metal pad regions to form a metal pedestal and a plurality of metal pads, and exposing the metal pedestal Two sides and the plurality of metal pads Surface; forming a geometric pattern on the second surface of the base metal of the exposed; etching the metal base to the geometric pattern formed on the second surface of the base metal. A method of a quad flat no-lead semiconductor package, comprising: providing a metal substrate having a first side and a second side opposite to the first side; forming a pattern on the first side of the metal substrate Forming a metal pedestal region and a plurality of metal pad regions; etching the metal substrate to form the metal pedestal region and the plurality of metal pad regions; attaching a wafer to the metal a pedestal area on which a plurality of metal contacts are disposed; Forming a plurality of metal wires for connecting the plurality of metal contacts on the wafer to the plurality of metal pad regions; forming a gel body, the wafer, the metal wire is molded by a filming method The first surface of the metal pedestal region and the first surface of the plurality of metal pad regions are covered, and the second surface of the metal substrate is exposed; the second surface of the exposed metal substrate is etched to make the metal After the pedestal region is separated from the plurality of metal pad regions, a metal pedestal and a plurality of metal pads are formed, and the second surface of the metal pedestal and the second surface of the plurality of metal pads are exposed; A plating pattern is on the second surface of the metal base, wherein the plating pattern on the second surface of the metal base is a geometric pattern; and a plating pattern forming a geometric pattern is formed on the second surface of the metal base. A method of a quad flat no-lead semiconductor package, comprising: providing a metal substrate having a first side and a second side opposite to the first side; forming a pattern on the first side of the metal substrate Forming a metal pedestal region and a plurality of metal pad regions; etching the metal substrate to form the metal pedestal region and the plurality of metal pad regions; attaching a wafer to the metal a plurality of metal contacts are disposed on the susceptor region; a plurality of metal wires are formed for connecting the plurality of metal contacts on the wafer to the plurality of metal pad regions; forming a gel body Coating the wafer, the metal wire, the first side of the metal pedestal region and the first surface of the plurality of metal pad regions by a molding method, and exposing the second surface of the metal substrate; Etching the second side of the exposed metal substrate to separate the metal pedestal region from the plurality of metal pad regions to form a metal pedestal and a plurality of metal pads, and exposing the metal pedestal Two sides and the plurality of metal pads Surface and the third surface; forming a second surface of the base metal is exposed to a pattern of a geometric; The metal pedestal is etched to form the geometric pattern on the second side of the metal pedestal. A method of a quad flat no-lead semiconductor package, comprising: providing a metal substrate having a first side and a second side opposite to the first side; forming a pattern on the first side of the metal substrate Forming a metal pedestal region and a plurality of metal pad regions; etching the metal substrate to form the metal pedestal region and the plurality of metal pad regions; attaching a wafer to the metal a plurality of metal contacts are disposed on the susceptor region; a plurality of metal wires are formed for connecting the plurality of metal contacts on the wafer to the plurality of metal pad regions; forming a gel body Coating the wafer, the metal wire, the first side of the metal pedestal region and the first surface of the plurality of metal pad regions by a molding method, and exposing the second surface of the metal substrate; Etching the second side of the exposed metal substrate to separate the metal pedestal region from the plurality of metal pad regions to form a metal pedestal and a plurality of metal pads, and exposing the metal pedestal Two sides and the plurality of metal pads And a third surface; forming a plating pattern on the second surface of the metal base, wherein the plating pattern on the second surface of the metal base is a geometric pattern; forming a geometric pattern of the plating layer on the metal base On the second side. The encapsulation method of claim 22, 23, 24 or 25, wherein a plurality of metal contacts on the wafer are connected to the plurality of metal pad regions before the plurality of metal wires are connected to the plurality of metal pad regions, further preceding A metal layer is formed on the plurality of metal pad regions. The encapsulation method of claim 22, 23, 24 or 25, wherein the wafer and the metal pedestal section are attached by an adhesive layer. The encapsulation method of claim 27, wherein the adhesive layer is a polymer material. The encapsulation method of claim 27, wherein the adhesive layer is a B-Stage material. The packaging method according to claim 23 or 25, wherein the material of the plating layer is from the bottom Among the column groups are selected: gold, silver, copper, tin, antimony, palladium or alloys thereof. The encapsulation method of claim 22, 23, 24 or 25, wherein the encapsulant is a resin material. The encapsulation method of claim 26, wherein the material of the metal layer is selected from the group consisting of gold, silver, copper, tin, antimony, palladium or alloys thereof. The encapsulation method of claim 22, 23, 24 or 25, wherein the material of the metal substrate is copper, aluminum or an alloy thereof. The encapsulation method of claim 22, 23, 24 or 25, wherein the metal substrate is etched by a half etch.