TWI688057B - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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TWI688057B
TWI688057B TW107144415A TW107144415A TWI688057B TW I688057 B TWI688057 B TW I688057B TW 107144415 A TW107144415 A TW 107144415A TW 107144415 A TW107144415 A TW 107144415A TW I688057 B TWI688057 B TW I688057B
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adhesive layer
carrier
pins
side wall
corner
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TW107144415A
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Chinese (zh)
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TW202023000A (en
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周世文
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南茂科技股份有限公司
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Priority to CN201910148998.2A priority patent/CN111312666B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package structure includes a lead frame, a chip, an adhesive layer, and a molding compound. The lead frame includes a die pad and a plurality of leads. The die pad has an upper surface, a lower surface opposite to the upper surface, a side surface connecting the upper surface, and a first corner between the upper surface and the side surface. The chip is disposed on the upper surface of the die pad and electrically connected to the plurality of leads. The chip is adhered to the die pad through the adhesive layer. The adhesive layer covers the upper surface and a portion of the side surface of the die pad and covers the first corner of the die pad. The molding compound covers the lead frame, the chip and the adhesive layer.

Description

半導體封裝結構Semiconductor packaging structure

本發明是有關於一種封裝結構，且特別是有關於一種半導體封裝結構。The invention relates to a packaging structure, and in particular to a semiconductor packaging structure.

半導體封裝技術包含有許多封裝形態，其中屬於扁平封裝系列的四方/二方扁平無外引腳(QFN/DFN)封裝具有較短的訊號傳遞路徑及相對較快的訊號傳遞速度，因此四方/二方扁平無外引腳封裝適用於高頻傳輸之晶片封裝，且為低腳位(low pin count)封裝型態的主流之一。一般而言，QFN/DFN封裝所採用的導線架的製做是將金屬薄板以蝕刻的方式形成晶片承載座與多個引腳。蝕刻液由金屬薄板底面流入使得最終形成的承載座或引腳具有略呈弧狀的側壁，且承載座或引腳的頂面與側壁之間形成較銳利的夾角，導致應力易集中於該處。在後續的溫度循環測試(Temperature Cycle Test, TCT)或實際產品的應用中，包覆導線架的封裝膠體(molding compound)易因熱脹冷縮從承載座或引腳較銳利的夾角處開始破裂(crack)，甚至還會破裂至半導體封裝外，進而降低封裝體的可靠度。因此，如何克服上述半導體封裝受熱後產生破裂的技術問題，便成為當前亟待解決的問題之一。Semiconductor packaging technology includes many packaging forms. Among them, the quadrilateral/two-square flat no-lead (QFN/DFN) package that belongs to the flat package series has a short signal transmission path and a relatively fast signal transmission speed. Therefore, the square/two The square flat leadless package is suitable for high-frequency transmission chip packages, and is one of the mainstream of low pin count package types. Generally speaking, the lead frame used in the QFN/DFN package is made by etching a thin metal plate to form a chip carrier and multiple pins. The etching solution flows from the bottom surface of the metal thin plate so that the resulting carrier or pin has a slightly curved side wall, and a sharp angle is formed between the top surface of the carrier or pin and the side wall, causing stress to be concentrated there . In the subsequent Temperature Cycle Test (TCT) or the application of actual products, the molding compound covering the lead frame is likely to crack from the sharp corner of the carrier or the pin due to thermal expansion and contraction (crack), or even break out of the semiconductor package, thereby reducing the reliability of the package. Therefore, how to overcome the above-mentioned technical problem that the semiconductor package cracks after being heated has become one of the problems to be solved urgently.

本發明提供一種半導體封裝結構，具有良好的可靠度。The invention provides a semiconductor packaging structure with good reliability.

本發明的半導體封裝結構包括導線架、晶片、膠層以及封裝膠體。導線架包括承載座與多個引腳。承載座具有上表面、相對於上表面的下表面、連接上表面的側表面以及位於上表面與側表面之間的第一轉角。晶片設置於承載座的上表面，且電性連接多個引腳。晶片透過膠層連接承載座。膠層覆蓋承載座的上表面及部分側表面，且包覆承載座的所述第一轉角。封裝膠體覆蓋導線架、晶片及膠層。The semiconductor packaging structure of the present invention includes a lead frame, a wafer, an adhesive layer, and an encapsulating gel. The lead frame includes a bearing base and a plurality of pins. The carrier has an upper surface, a lower surface opposite to the upper surface, a side surface connecting the upper surface, and a first corner between the upper surface and the side surface. The chip is disposed on the upper surface of the carrier, and is electrically connected to a plurality of pins. The chip is connected to the carrier through the adhesive layer. The adhesive layer covers the upper surface and part of the side surfaces of the bearing seat, and covers the first corner of the bearing seat. The encapsulating colloid covers the lead frame, chip and glue layer.

在本發明的一實施例中，上述的膠層的彈性模數小於封裝膠體的彈性模數。In an embodiment of the invention, the elastic modulus of the adhesive layer is smaller than the elastic modulus of the encapsulating gel.

在本發明的一實施例中，上述的晶片延伸超出承載座的第一轉角。In an embodiment of the invention, the above-mentioned wafer extends beyond the first corner of the carrier.

在本發明的一實施例中，上述的各引腳具有頂面、連接頂面的側壁以及位於頂面與側壁之間的第二轉角，且晶片與膠層延伸至部分多個引腳的頂面，膠層包覆部分多個引腳的第二轉角。In an embodiment of the present invention, each of the above-mentioned pins has a top surface, a side wall connecting the top surface, and a second corner between the top surface and the side wall, and the chip and the adhesive layer extend to the top of some of the multiple pins On the surface, the adhesive layer covers the second corners of some of the leads.

在本發明的一實施例中，上述的承載座還具有第一凹陷。第一凹陷使側表面包括第一側表面與第二側表面，且下表面包括第一下表面與第二下表面，其中第一側表面較第二側表面遠離承載座的中心，第二下表面較第一下表面遠離上表面。In an embodiment of the invention, the above-mentioned bearing base further has a first recess. The first depression causes the side surface to include a first side surface and a second side surface, and the lower surface includes a first lower surface and a second lower surface, wherein the first side surface is farther from the center of the carrier than the second side surface, and the second lower surface The surface is farther from the upper surface than the first lower surface.

在本發明的一實施例中，上述的膠層包覆承載座的所述第一側表面。In an embodiment of the invention, the above-mentioned adhesive layer covers the first side surface of the carrier.

在本發明的一實施例中，上述的膠層進一步包覆第一下表面。In an embodiment of the invention, the above-mentioned adhesive layer further covers the first lower surface.

在本發明的一實施例中，上述的各引腳具有頂面、相對於頂面的底面、連接頂面的側壁、位於頂面與側壁之間的第二轉角以及第二凹陷。第二凹陷使側壁包括第一側壁與第二側壁，且底面包括第一底面與第二底面，其中第二側壁較第一側壁遠離承載座，第二底面較第一底面遠離頂面，晶片與膠層延伸至部分多個引腳的頂面，膠層包覆部分多個引腳的第二轉角。In an embodiment of the present invention, each of the pins described above has a top surface, a bottom surface opposite to the top surface, a side wall connecting the top surface, a second corner between the top surface and the side wall, and a second recess. The second recess causes the side wall to include the first side wall and the second side wall, and the bottom surface includes the first bottom surface and the second bottom surface, wherein the second side wall is farther away from the carrier than the first side wall, and the second bottom surface is farther away from the top surface than the first bottom surface. The adhesive layer extends to the top surfaces of some of the leads, and the adhesive layer covers the second corners of some of the leads.

在本發明的一實施例中，上述的膠層包覆承載座的第一側表面與部分多個引腳的第一側壁。In an embodiment of the invention, the above-mentioned adhesive layer covers the first side surface of the carrier and the first side walls of some of the pins.

在本發明的一實施例中，上述的膠層進一步包覆承載座的第一下表面部分多個與引腳的第一底面。In an embodiment of the invention, the above-mentioned adhesive layer further covers the first bottom surface portion of the carrier and the first bottom surface of the pins.

基於上述，本發明的半導體封裝結構利用彈性較佳的膠層包覆承載座的第一轉角，幫助消散易集中於第一轉角的應力，以降低封裝膠體於溫度循環測試或後續之產品運作時因熱脹冷縮而自第一轉角處破裂的現象，進而提升半導體封裝結構的可靠度。Based on the above, the semiconductor package structure of the present invention wraps the first corner of the carrier with a better elastic layer to help dissipate the stress that tends to concentrate on the first corner, so as to reduce the packaging gel during temperature cycle testing or subsequent product operation The phenomenon of cracking from the first corner due to thermal expansion and contraction further improves the reliability of the semiconductor packaging structure.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。The invention is explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

圖1至圖8是本發明一些實施例的半導體封裝結構的剖面示意圖。請先參考圖1，半導體封裝結構100包括導線架110，其中導線架110包括承載座120與多個引腳130。承載座120具有上表面121、相對於上表面121的下表面122、連接上表面121的側表面123以及位於上表面121與側表面123之間的第一轉角R1。另一方面，引腳130具有頂面131、相對於頂面131的底面132、連接頂面131的側壁133以及位於頂面131與側壁133之間的第二轉角R2。此外，多個引腳130以一間隙G設置於承載座120的周圍。多個引腳130可以是設置於承載座120的相對兩邊，也可包圍承載座120的四邊，本發明對此不作限制。1 to 8 are schematic cross-sectional views of semiconductor package structures according to some embodiments of the present invention. Please refer to FIG. 1 first. The semiconductor package structure 100 includes a lead frame 110, wherein the lead frame 110 includes a carrier 120 and a plurality of pins 130. The carrier 120 has an upper surface 121, a lower surface 122 opposite to the upper surface 121, a side surface 123 connecting the upper surface 121, and a first corner R1 between the upper surface 121 and the side surface 123. On the other hand, the pin 130 has a top surface 131, a bottom surface 132 opposite to the top surface 131, a side wall 133 connecting the top surface 131, and a second corner R2 between the top surface 131 and the side wall 133. In addition, a plurality of pins 130 are disposed around the carrier 120 with a gap G. The multiple pins 130 may be disposed on opposite sides of the carrier 120, or may surround four sides of the carrier 120, which is not limited in the present invention.

在本實施例中，半導體封裝結構100還包括晶片140。晶片140設置於承載座120的上表面121。另一方面，如圖1所示，晶片140可延伸超出承載座120的第一轉角R1，但不與引腳130的頂面131接觸。換句話說，晶片140可以僅延伸至間隙G的上方。特別說明的是，本發明不限制晶片140的種類，可視實際設計需求而定。此外，如圖1所示，晶片140可採用打線接合(wire bonding)的方式電性連接至引腳130。舉例來說，導線170可以連接位於晶片140的主動表面141的接墊(未繪示)與引腳130的頂面131，其中晶片140的主動表面141遠離承載座120的上表面121。特別說明的是，上述導線的連接方式可視實際製程需求而調整。In this embodiment, the semiconductor package structure 100 further includes a wafer 140. The wafer 140 is disposed on the upper surface 121 of the carrier 120. On the other hand, as shown in FIG. 1, the wafer 140 may extend beyond the first corner R1 of the carrier 120, but does not contact the top surface 131 of the pin 130. In other words, the wafer 140 may only extend above the gap G. In particular, the present invention does not limit the types of wafers 140, and may depend on actual design requirements. In addition, as shown in FIG. 1, the wafer 140 may be electrically connected to the pins 130 by wire bonding. For example, the wire 170 may connect the pad (not shown) on the active surface 141 of the wafer 140 and the top surface 131 of the pin 130, wherein the active surface 141 of the wafer 140 is away from the upper surface 121 of the carrier 120. In particular, the connection method of the above wires can be adjusted according to actual process requirements.

在本實施例中，半導體封裝結構100還包括膠層150。晶片140透過膠層150連接承載座120。膠層150覆蓋承載座120的上表面121及部分側表面123，且包覆承載座120的第一轉角R1。在本實施例中，膠層150可以是高彈性的膠膜，且膠層150可以先形成於晶片140的背表面(相對於主動表面141的面)，並且可在晶片接合製程中藉由熱壓方式使膠層150包覆住承載座120的上表面121及部分側表面123。換言之，承載座120的第一轉角R1會埋入膠層150中。另一方面，在本實施例中，膠層150的寬度是等於晶片140的寬度，但本發明不限於此。In this embodiment, the semiconductor package structure 100 further includes an adhesive layer 150. The wafer 140 is connected to the carrier 120 through the adhesive layer 150. The adhesive layer 150 covers the upper surface 121 and part of the side surfaces 123 of the carrier 120 and covers the first corner R1 of the carrier 120. In this embodiment, the adhesive layer 150 may be a highly elastic adhesive film, and the adhesive layer 150 may be formed on the back surface of the wafer 140 (relative to the surface of the active surface 141) first, and may be heated by heat during the wafer bonding process. In the pressing method, the adhesive layer 150 covers the upper surface 121 and part of the side surfaces 123 of the carrier 120. In other words, the first corner R1 of the carrier 120 is buried in the adhesive layer 150. On the other hand, in this embodiment, the width of the glue layer 150 is equal to the width of the wafer 140, but the invention is not limited thereto.

在本實施例中，半導體封裝結構100還包括封裝膠體160。封裝膠體160覆蓋導線架110、晶片140及膠層150。較佳地，膠層150的彈性模數(modulus of elasticity)可以是小於封裝膠體160的彈性模數。舉例而言，在25℃的溫度條件下，封裝膠體160的彈性模數例如是大於15GPa，膠層150的彈性模數例如是小於5GPa。換言之，膠層150較封裝膠體160具有較佳的彈性，藉由膠層150包覆承載座120的第一轉角R1，可幫助消散易集中於第一轉角R1的應力，降低封裝膠體160於溫度循環測試或後續之產品運作時因熱脹冷縮而自第一轉角R1處破裂的現象，進而提升半導體封裝結構100的可靠度。In this embodiment, the semiconductor packaging structure 100 further includes an encapsulant 160. The encapsulant 160 covers the lead frame 110, the wafer 140 and the adhesive layer 150. Preferably, the modulus of elasticity of the glue layer 150 may be smaller than the modulus of elasticity of the encapsulating glue 160. For example, under a temperature condition of 25° C., the elastic modulus of the encapsulating colloid 160 is, for example, greater than 15 GPa, and the elastic modulus of the adhesive layer 150 is, for example, less than 5 GPa. In other words, the adhesive layer 150 has better elasticity than the encapsulant 160. By covering the first corner R1 of the carrier 120 with the adhesive layer 150, it can help to dissipate the stress that tends to concentrate on the first corner R1 and reduce the temperature of the encapsulant 160 to the temperature The phenomenon of cracking from the first corner R1 due to thermal expansion and contraction during the cycle test or subsequent product operation, thereby improving the reliability of the semiconductor packaging structure 100.

請參考圖2，本實施例的半導體封裝結構100A與上述實施例的半導體封裝結構100略有不同，進一步而言，本實施例的半導體封裝結構100A的晶片140A與膠層150A可延伸至部分引腳130的頂面131，且膠層150A進一步包覆部分引腳130的第二轉角R2。由於膠層150A亦包覆引腳130的第二轉角R2，集中於第二轉角R2處的應力可藉由膠層150A消散，因此可以進一步降低封裝膠體160於溫度循環測試或後續之產品運作時因熱脹冷縮而自第二轉角R2處破裂的現象，進而更提升半導體封裝結構100A的可靠度。Please refer to FIG. 2. The semiconductor package structure 100A of this embodiment is slightly different from the semiconductor package structure 100 of the above embodiment. Further, the wafer 140A and the adhesive layer 150A of the semiconductor package structure 100A of this embodiment may extend to some The top surface 131 of the foot 130, and the adhesive layer 150A further covers a part of the second corner R2 of the pin 130. Since the adhesive layer 150A also covers the second corner R2 of the lead 130, the stress concentrated at the second corner R2 can be dissipated by the adhesive layer 150A, which can further reduce the packaging gel 160 during temperature cycle testing or subsequent product operation The phenomenon of cracking from the second corner R2 due to thermal expansion and contraction further improves the reliability of the semiconductor package structure 100A.

請參考圖3，本實施例的半導體封裝結構100B與上述實施例的半導體封裝結構100略有不同，進一步而言，半導體封裝結構100B的承載座120還具有第一凹陷124。第一凹陷124使側表面123包括第一側表面123a與第二側表面123b，且下表面122包括第一下表面122a與第二下表面122b。第一側表面123a較第二側表面123b遠離承載座120的中心。第二下表面122b較第一下表面122a遠離上表面121。在本實施例中，膠層150B包覆承載座120的第一側表面123a。進一步來說，膠層150B部分覆蓋承載座120的第一側表面123a。Referring to FIG. 3, the semiconductor package structure 100B of this embodiment is slightly different from the semiconductor package structure 100 of the above embodiment. Further, the carrier 120 of the semiconductor package structure 100B further has a first recess 124. The first recess 124 causes the side surface 123 to include a first side surface 123a and a second side surface 123b, and the lower surface 122 includes a first lower surface 122a and a second lower surface 122b. The first side surface 123a is farther from the center of the carrier 120 than the second side surface 123b. The second lower surface 122b is farther from the upper surface 121 than the first lower surface 122a. In this embodiment, the adhesive layer 150B covers the first side surface 123a of the carrier 120. Further, the adhesive layer 150B partially covers the first side surface 123a of the carrier 120.

請繼續參考圖3，引腳130的頂面131與側壁133之間還具有第二凹陷134。第二凹陷134使側壁133包括第一側壁133a與第二側壁133b，且底面132包括第一底面132a與第二底面132b。第二側壁133b較第一側壁133a遠離承載座120。第二底面132b較第一底面132a遠離頂面131。由於封裝膠體160可填入第一凹陷124與第二凹陷134中，因此可降低承載座120與引腳130從封裝膠體160中脫落的機率。Please continue to refer to FIG. 3, there is a second recess 134 between the top surface 131 of the pin 130 and the side wall 133. The second recess 134 makes the side wall 133 include the first side wall 133a and the second side wall 133b, and the bottom surface 132 includes the first bottom surface 132a and the second bottom surface 132b. The second side wall 133b is farther from the carrier 120 than the first side wall 133a. The second bottom surface 132b is farther from the top surface 131 than the first bottom surface 132a. Since the encapsulant 160 can be filled into the first recess 124 and the second recess 134, the probability of the carrier 120 and the pins 130 falling out of the encapsulant 160 can be reduced.

請參考圖4，本實施例的半導體封裝結構100C與上述實施例的半導體封裝結構100B略有不同，進一步而言，半導體封裝結構100C的膠層150C進一步延伸包覆承載座120的第一側表面123a。更進一步而言，承載座120通常為四方形，故具有四個第一側表面123a，圖4為半導體封裝結構100C的剖面示意圖，僅示意地繪示出其中兩個第一側表面123a。在本實施例中，膠層150C完全覆蓋承載座120的四個第一側表面123a。在其他實施例中，膠層150C所覆蓋的第一側表面123a的數量或覆蓋第一側表面123a的面積可視需求調整，本發明對此不作限制。Referring to FIG. 4, the semiconductor package structure 100C of this embodiment is slightly different from the semiconductor package structure 100B of the above embodiment. Further, the adhesive layer 150C of the semiconductor package structure 100C further extends to cover the first side surface of the carrier 120 123a. Furthermore, the carrier 120 is generally rectangular, so it has four first side surfaces 123a. FIG. 4 is a schematic cross-sectional view of the semiconductor package structure 100C, and only two of the first side surfaces 123a are schematically shown. In this embodiment, the adhesive layer 150C completely covers the four first side surfaces 123a of the carrier 120. In other embodiments, the number of the first side surfaces 123a covered by the adhesive layer 150C or the area covering the first side surfaces 123a can be adjusted according to requirements, and the present invention does not limit this.

請參考圖5，本實施例的半導體封裝結構100D與上述實施例的半導體封裝結構100C略有不同，進一步而言，半導體封裝結構100D的膠層150D進一步包覆承載座120的第一下表面122a。進一步來說，膠層150D可以是完全覆蓋承載座120的第一下表面122a，且部分覆蓋承載座120的第二側表面123b。更進一步而言，承載座120通常為四方形，故具有四個第一側表面123a以及四個第二側表面123b，圖5為半導體封裝結構100D的剖面示意圖，僅示意地繪示出其中兩個第一側表面123a以及兩個第二側表面123b。在本實施例中，膠層150D完全覆蓋承載座120的四個第一側表面123a，且部分覆蓋承載座120的四個第二側表面123b。在其他實施例中，膠層150D所覆蓋的第一側表面123a以及第二側表面123b的數量或覆蓋第一側表面123a以及第二側表面123b的面積可視需求調整。Please refer to FIG. 5. The semiconductor package structure 100D of this embodiment is slightly different from the semiconductor package structure 100C of the above embodiment. Further, the adhesive layer 150D of the semiconductor package structure 100D further covers the first lower surface 122 a of the carrier 120 . Further, the adhesive layer 150D may completely cover the first lower surface 122 a of the carrier 120 and partially cover the second side surface 123 b of the carrier 120. Furthermore, the carrier 120 is generally square, so it has four first side surfaces 123a and four second side surfaces 123b. FIG. 5 is a schematic cross-sectional view of the semiconductor package structure 100D, only two of which are schematically shown. A first side surface 123a and two second side surfaces 123b. In this embodiment, the adhesive layer 150D completely covers the four first side surfaces 123a of the carrier 120, and partially covers the four second side surfaces 123b of the carrier 120. In other embodiments, the number of the first side surface 123a and the second side surface 123b covered by the adhesive layer 150D or the area covering the first side surface 123a and the second side surface 123b can be adjusted according to requirements.

請參考圖6，本實施例的半導體封裝結構100E與上述實施例的半導體封裝結構100B略有不同，進一步而言，本實施例的半導體封裝結構100E的晶片140A與膠層150E可延伸至部分引腳130的頂面131，且膠層150E包覆部分引腳130的第二轉角R2。另一方面，膠層150E包覆承載座120的第一側表面123a與部分引腳130的第一側壁133a。應說明的是，膠層150E所覆蓋的第一側表面123a的數量或覆蓋第一側表面123a的面積可視需求調整，類似於圖4所述，於此不再贅述。Please refer to FIG. 6. The semiconductor package structure 100E of this embodiment is slightly different from the semiconductor package structure 100B of the above embodiment. Further, the wafer 140A and the adhesive layer 150E of the semiconductor package structure 100E of this embodiment may extend to some The top surface 131 of the leg 130, and the adhesive layer 150E covers a part of the second corner R2 of the pin 130. On the other hand, the adhesive layer 150E covers the first side surface 123a of the carrier 120 and the first side wall 133a of some of the pins 130. It should be noted that the number of the first side surfaces 123a covered by the adhesive layer 150E or the area covering the first side surfaces 123a can be adjusted according to requirements, similar to that described in FIG. 4, and will not be repeated here.

請參考圖7，本實施例的半導體封裝結構100F與上述實施例的半導體封裝結構100E略有不同，進一步而言，本實施例的半導體封裝結構100F的膠層150F進一步完全包覆承載座120的第一側表面123a與引腳130的第一側壁133a。應說明的是，膠層150F所覆蓋的第一側表面123a的數量或覆蓋第一側表面123a的面積可視需求調整，類似於圖4所述，於此不再贅述。Referring to FIG. 7, the semiconductor package structure 100F of this embodiment is slightly different from the semiconductor package structure 100E of the above embodiment. Further, the adhesive layer 150F of the semiconductor package structure 100F of this embodiment further completely covers the carrier 120 The first side surface 123a and the first side wall 133a of the pin 130. It should be noted that the number of the first side surfaces 123a covered by the adhesive layer 150F or the area covering the first side surfaces 123a can be adjusted according to requirements, similar to that described in FIG. 4, and will not be repeated here.

請參考圖8，本實施例的半導體封裝結構100G與上述實施例的半導體封裝結構100F略有不同，進一步而言，本實施例的半導體封裝結構100G的膠層150G進一步包覆承載座120的第一下表面122a與部分引腳130的第一底面132a。進一步來說，膠層150G可以是部分覆蓋引腳130的第一底面132a。在本實施例中，膠層150G完全覆蓋承載座120的第一下表面122a與部分覆蓋引腳130的第一底面132a。應說明的是，膠層150G所覆蓋的第一側表面123a以及第二側表面123b的數量或覆蓋第一側表面123a以及第二側表面123b的面積可視需求調整，類似於圖5所述，於此不再贅述。Referring to FIG. 8, the semiconductor package structure 100G of this embodiment is slightly different from the semiconductor package structure 100F of the above embodiment. Further, the adhesive layer 150G of the semiconductor package structure 100G of this embodiment further covers the first The lower surface 122a and the first bottom surface 132a of part of the pins 130. Further, the adhesive layer 150G may partially cover the first bottom surface 132a of the pin 130. In this embodiment, the adhesive layer 150G completely covers the first lower surface 122 a of the carrier 120 and partially covers the first bottom surface 132 a of the pin 130. It should be noted that the number of the first side surface 123a and the second side surface 123b covered by the adhesive layer 150G or the area covering the first side surface 123a and the second side surface 123b can be adjusted according to requirements, similar to that described in FIG. 5, I will not repeat them here.

特別說明的是，本發明不限制膠層延伸的覆蓋程度，上述所有實施例可以搭配組合，只要膠層有包覆到承載座的第一轉角，皆屬本發明所欲保護的範圍。In particular, the present invention does not limit the extent of coverage of the adhesive layer. All the above embodiments can be combined. As long as the adhesive layer covers the first corner of the carrier, it is within the scope of the present invention.

綜上所述，本發明的半導體封裝結構利用彈性較佳的膠層包覆承載座的第一轉角，幫助消散易集中於第一轉角的應力，以降低封裝膠體於溫度循環測試或後續之產品運作時因熱脹冷縮而自第一轉角處破裂的現象，進而提升半導體封裝結構的可靠度。In summary, the semiconductor package structure of the present invention covers the first corner of the carrier with a better elastic layer to help dissipate the stress that tends to concentrate on the first corner, so as to reduce the temperature of the encapsulating gel during the temperature cycle test or subsequent products The phenomenon of rupture from the first corner due to thermal expansion and contraction during operation, thereby improving the reliability of the semiconductor packaging structure.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100、100A~100G:半導體封裝結構100, 100A~100G: semiconductor packaging structure

110:導線架110: lead frame

120:承載座120: Carrier

121:上表面121: upper surface

122:下表面122: lower surface

122a:第一下表面122a: first lower surface

122b:第二下表面122b: Second lower surface

123:側表面123: Side surface

123a:第一側表面123a: first side surface

123b:第二側表面123b: Second side surface

124:第一凹陷124: The first depression

130:引腳130: pin

131:頂面131: top surface

132:底面132: Underside

132a:第一底面132a: the first bottom

132b:第二底面132b: Second bottom surface

133:側壁133: Side wall

133a:第一側壁133a: first side wall

133b:第二側壁133b: Second side wall

134:第二凹陷134: Second depression

140、140A:晶片140, 140A: chip

141:主動表面141: Active surface

150、150A~150G:膠層150, 150A~150G: adhesive layer

160:封裝膠體160: encapsulating colloid

170:導線170: wire

R1:第一轉角R1: first corner

R2:第二轉角R2: second corner

G:間隙G: gap

圖1至圖8是本發明一些實施例的半導體封裝結構的剖面示意圖。1 to 8 are schematic cross-sectional views of semiconductor package structures according to some embodiments of the present invention.

100:半導體封裝結構 100: Semiconductor packaging structure

110:導線架 110: lead frame

120:承載座 120: Carrier

121:上表面 121: upper surface

122:下表面 122: lower surface

123:側表面 123: Side surface

130:引腳 130: pin

131:頂面 131: top surface

132:底面 132: Underside

133:側壁 133: Side wall

140:晶片 140: chip

141:主動表面 141: Active surface

150:膠層 150: adhesive layer

160:封裝膠體 160: encapsulating colloid

170:導線 170: wire

R1:第一轉角 R1: first corner

R2:第二轉角 R2: second corner

G:間隙 G: gap

Claims (9)

一種半導體封裝結構，包括：導線架，包括承載座與多個引腳，其中所述承載座具有上表面、相對於所述上表面的下表面、連接所述上表面的側表面以及位於所述上表面與所述側表面之間的第一轉角；晶片，設置於所述承載座的所述上表面，且電性連接所述多個引腳；膠層，所述晶片透過所述膠層連接所述承載座，其中所述膠層覆蓋所述承載座的所述上表面及部分所述側表面，且包覆所述承載座的所述第一轉角；以及封裝膠體，覆蓋所述導線架、所述晶片及所述膠層，其中所述膠層的彈性模數小於所述封裝膠體的彈性模數。 A semiconductor packaging structure includes: a lead frame, including a carrier and a plurality of pins, wherein the carrier has an upper surface, a lower surface opposite to the upper surface, a side surface connected to the upper surface, and located on the A first corner between the upper surface and the side surface; a chip, which is disposed on the upper surface of the carrier, and is electrically connected to the plurality of pins; an adhesive layer, the chip passes through the adhesive layer Connected to the bearing seat, wherein the adhesive layer covers the upper surface and part of the side surfaces of the bearing seat, and covers the first corner of the bearing seat; and encapsulates the gel to cover the wire The frame, the wafer and the adhesive layer, wherein the elastic modulus of the adhesive layer is smaller than the elastic modulus of the encapsulating colloid. 如申請專利範圍第1項所述的半導體封裝結構，其中所述晶片延伸超出所述承載座的所述第一轉角。 The semiconductor package structure according to item 1 of the patent application scope, wherein the wafer extends beyond the first corner of the carrier. 如申請專利範圍第2項所述的半導體封裝結構，其中各所述引腳具有頂面、連接所述頂面的側壁以及位於所述頂面與所述側壁之間的第二轉角，且所述晶片與所述膠層延伸至部分所述多個引腳的所述頂面，所述膠層包覆部分所述多個引腳的所述第二轉角。 The semiconductor package structure as described in item 2 of the patent application scope, wherein each of the pins has a top surface, a side wall connecting the top surface, and a second corner between the top surface and the side wall, and the The wafer and the glue layer extend to part of the top surfaces of the plurality of pins, and the glue layer covers part of the second corners of the plurality of pins. 如申請專利範圍第1項所述的半導體封裝結構，其中所述承載座還具有第一凹陷，所述第一凹陷使所述側表面包括第一 側表面與第二側表面，且所述下表面包括第一下表面與第二下表面，其中所述第一側表面較所述第二側表面遠離所述承載座的中心，所述第二下表面較所述第一下表面遠離所述上表面。 The semiconductor package structure as described in item 1 of the patent application range, wherein the carrier further has a first recess, the first recess causes the side surface to include a first A side surface and a second side surface, and the lower surface includes a first lower surface and a second lower surface, wherein the first side surface is farther from the center of the carrier than the second side surface, the second The lower surface is farther from the upper surface than the first lower surface. 如申請專利範圍第4項所述的半導體封裝結構，其中所述膠層包覆所述承載座的所述第一側表面。 The semiconductor packaging structure as described in item 4 of the patent application range, wherein the adhesive layer covers the first side surface of the carrier. 如申請專利範圍第5項所述的半導體封裝結構，其中所述膠層進一步包覆所述第一下表面。 The semiconductor packaging structure as described in item 5 of the patent application range, wherein the adhesive layer further covers the first lower surface. 如申請專利範圍第4項所述的半導體封裝結構，其中各所述引腳具有頂面、相對於所述頂面的底面、連接所述頂面的側壁、位於所述頂面與所述側壁之間的第二轉角以及第二凹陷，所述第二凹陷使所述側壁包括第一側壁與第二側壁，且所述底面包括第一底面與第二底面，其中所述第二側壁較所述第一側壁遠離所述承載座，所述第二底面較所述第一底面遠離所述頂面，所述晶片與所述膠層延伸至部分所述多個引腳的所述頂面，所述膠層包覆部分所述多個引腳的所述第二轉角。 The semiconductor package structure as described in item 4 of the patent application scope, wherein each of the pins has a top surface, a bottom surface opposite to the top surface, a side wall connecting the top surface, located on the top surface and the side wall Between the second corner and the second recess, the second recess causes the side wall to include a first side wall and a second side wall, and the bottom surface includes a first bottom surface and a second bottom surface, wherein the second side wall is The first side wall is away from the carrier, the second bottom surface is farther away from the top surface than the first bottom surface, the wafer and the adhesive layer extend to part of the top surfaces of the plurality of pins, The adhesive layer covers part of the second corners of the plurality of pins. 如申請專利範圍第7項所述的半導體封裝結構，其中所述膠層包覆所述承載座的所述第一側表面與部分所述多個引腳的所述第一側壁。 The semiconductor packaging structure as described in item 7 of the patent application range, wherein the adhesive layer covers the first side surface of the carrier and part of the first side walls of the plurality of pins. 如申請專利範圍第8項所述的半導體封裝結構，其中所述膠層進一步包覆所述承載座的所述第一下表面與部分所述多個引腳的所述第一底面。 The semiconductor packaging structure as described in item 8 of the patent application range, wherein the adhesive layer further covers the first lower surface of the carrier and part of the first bottom surfaces of the plurality of pins.
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