CN111312666B - Semiconductor packaging structure - Google Patents

Semiconductor packaging structure Download PDF

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Publication number
CN111312666B
CN111312666B CN201910148998.2A CN201910148998A CN111312666B CN 111312666 B CN111312666 B CN 111312666B CN 201910148998 A CN201910148998 A CN 201910148998A CN 111312666 B CN111312666 B CN 111312666B
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Prior art keywords
adhesive layer
semiconductor package
carrier
package structure
chip
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CN201910148998.2A
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CN111312666A (en
Inventor
周世文
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention provides a semiconductor packaging structure which comprises a lead frame, a chip, an adhesive layer and a packaging colloid. The lead frame comprises a bearing seat and a plurality of pins. The bearing seat is provided with an upper surface, a lower surface opposite to the upper surface, a side surface connecting the upper surface and a first corner between the upper surface and the side surface. The chip is arranged on the upper surface of the bearing seat and is electrically connected with the pins. The chip is connected with the bearing seat through the glue layer. The glue layer covers the upper surface and part of the side surface of the bearing seat and covers the first corner of the bearing seat. The packaging colloid covers the lead frame, the chip and the glue layer.

Description

Semiconductor packaging structure
Technical Field
The present invention relates to a package structure, and more particularly, to a semiconductor package structure.
Background
The semiconductor package technology includes many package types, among which the quad/quad flat no-lead (QFN/DFN) package belonging to the flat package series has a short signal transmission path and a relatively fast signal transmission speed, so that the quad/quad flat no-lead (QFN/DFN) package is suitable for chip packaging with high frequency transmission and is one of the mainstream low pin count (low pin count) package types. Generally, the lead frame used in QFN/DFN packages is manufactured by etching a metal thin plate to form a chip carrier and a plurality of leads. The etching liquid flows in from the bottom surface of the metal thin plate, so that the finally formed bearing seat or pin has a side wall which is slightly arc-shaped, and a sharper included angle is formed between the top surface of the bearing seat or pin and the side wall, so that stress is easily concentrated at the position. In a subsequent Temperature Cycle Test (TCT) or an actual product application, a molding compound (package) covering the lead frame is prone to crack from a relatively sharp corner of a carrier or a lead due to thermal expansion and contraction, and even to crack outside the semiconductor package, thereby reducing the reliability of the package. Therefore, how to overcome the above-mentioned technical problem of cracking of the semiconductor package after being heated becomes one of the problems to be solved.
Disclosure of Invention
The invention provides a semiconductor packaging structure with good reliability.
The semiconductor packaging structure comprises a lead frame, a chip, an adhesive layer and a packaging colloid. The lead frame comprises a bearing seat and a plurality of pins. The bearing seat is provided with an upper surface, a lower surface opposite to the upper surface, a side surface connecting the upper surface and a first corner between the upper surface and the side surface. The chip is arranged on the upper surface of the bearing seat and is electrically connected with the pins. The chip is connected with the bearing seat through the glue layer. The glue layer covers the upper surface and part of the side surface of the bearing seat and covers the first corner of the bearing seat. The packaging colloid covers the lead frame, the chip and the glue layer.
In an embodiment of the invention, an elastic modulus of the adhesive layer is smaller than an elastic modulus of the encapsulant.
In an embodiment of the invention, the chip extends beyond the first corner of the carrier.
In an embodiment of the invention, each of the leads has a top surface, a sidewall connected to the top surface, and a second corner located between the top surface and the sidewall, and the chip and the adhesive layer extend to the top surfaces of a portion of the leads, and the adhesive layer covers the second corners of the portion of the leads.
In an embodiment of the invention, the carrying seat further has a first recess. The first recess enables the side surface to include a first side surface and a second side surface, and the lower surface includes a first lower surface and a second lower surface, wherein the first side surface is farther from the center of the carrier seat than the second side surface, and the second lower surface is farther from the upper surface than the first lower surface.
In an embodiment of the invention, the adhesive layer covers the first side surface of the carrier.
In an embodiment of the invention, the adhesive layer further covers the first lower surface.
In an embodiment of the invention, each of the leads has a top surface, a bottom surface opposite to the top surface, a sidewall connecting the top surfaces, a second corner between the top surface and the sidewall, and a second recess. The second recess enables the side wall to comprise a first side wall and a second side wall, and the bottom surface comprises a first bottom surface and a second bottom surface, wherein the second side wall is far away from the bearing seat compared with the first side wall, the second bottom surface is far away from the top surface compared with the first bottom surface, the chip and the adhesive layer extend to the top surfaces of a part of the plurality of pins, and the adhesive layer covers the second corners of the part of the plurality of pins.
In an embodiment of the invention, the adhesive layer covers the first side surface of the carrier and the first side walls of a portion of the plurality of leads.
In an embodiment of the invention, the adhesive layer further covers a plurality of first lower surface portions of the carrier and the first bottom surfaces of the leads.
Based on the above, the semiconductor package structure of the present invention utilizes the adhesive layer with better elasticity to cover the first corner of the carrier, which helps dissipate the stress that is easily concentrated on the first corner, so as to reduce the phenomenon that the encapsulant is cracked from the first corner due to thermal expansion and contraction during the temperature cycle test or the subsequent product operation, thereby improving the reliability of the semiconductor package structure.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 to 8 are schematic cross-sectional views of semiconductor package structures according to some embodiments of the invention.
The reference numbers illustrate:
100. 100A to 100G: semiconductor packaging structure
110: lead frame
120: bearing seat
121: upper surface of
122: lower surface
122 a: a first lower surface
122 b: second lower surface
123: side surface
123 a: first side surface
123 b: second side surface
124: first recess
130: pin
131: the top surface
132: bottom surface
132 a: first bottom surface
132 b: second bottom surface
133: side wall
133 a: first side wall
133 b: second side wall
134: second recess
140. 140A: chip and method for manufacturing the same
141: active surface
150. 150A to 150G: glue layer
160: packaging colloid
170: conducting wire
R1: first angle of rotation
R2: second corner
G: gap
Detailed Description
The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness, dimensions, or dimensions of layers or regions in the figures may be exaggerated for clarity. The same or similar reference numbers refer to the same or similar elements, and the following paragraphs will not be repeated.
Fig. 1 to 8 are schematic cross-sectional views of semiconductor package structures according to some embodiments of the invention. Referring to fig. 1, a semiconductor package 100 includes a lead frame 110, wherein the lead frame 110 includes a carrier base 120 and a plurality of leads 130. The carrier 120 has an upper surface 121, a lower surface 122 opposite to the upper surface 121, a side surface 123 connecting the upper surface 121, and a first corner R1 between the upper surface 121 and the side surface 123. On the other hand, the lead 130 has a top surface 131, a bottom surface 132 opposite to the top surface 131, a sidewall 133 connecting the top surface 131, and a second corner R2 between the top surface 131 and the sidewall 133. In addition, the plurality of leads 130 are disposed around the carrier 120 with a gap G. The plurality of leads 130 may be disposed on two opposite sides of the carrier 120, or may surround four sides of the carrier 120, which is not limited in the present invention.
In the present embodiment, the semiconductor package structure 100 further includes a chip 140. The chip 140 is disposed on the upper surface 121 of the carrier 120. On the other hand, as shown in fig. 1, the chip 140 may extend beyond the first corner R1 of the carrier 120, but not contact the top surfaces 131 of the leads 130. In other words, the chip 140 may extend only above the gap G. It should be noted that the present invention is not limited to the kind of the chip 140, and may depend on the actual design requirement. In addition, as shown in fig. 1, the chip 140 may be electrically connected to the leads 130 by wire bonding. For example, the wires 170 may connect pads (not shown) on the active surface 141 of the chip 140 and the top surfaces 131 of the leads 130, wherein the active surface 141 of the chip 140 is away from the upper surface 121 of the carrier 120. In particular, the connection method of the conductive wires can be adjusted according to the actual process requirements.
In the present embodiment, the semiconductor package structure 100 further includes a glue layer 150. The chip 140 is connected to the carrier 120 through the adhesive layer 150. The adhesive layer 150 covers the upper surface 121 and a portion of the side surface 123 of the carrier 120, and covers the first corner R1 of the carrier 120. In the embodiment, the adhesive layer 150 may be a high-elasticity adhesive film, and the adhesive layer 150 may be formed on the back surface (the surface opposite to the active surface 141) of the chip 140 first, and the adhesive layer 150 may cover the upper surface 121 and a portion of the side surface 123 of the carrier 120 by a hot pressing method in the chip bonding process. In other words, the first corner R1 of the carrier 120 is embedded in the adhesive layer 150. On the other hand, in the embodiment, the width of the glue layer 150 is equal to the width of the chip 140, but the invention is not limited thereto.
In the present embodiment, the semiconductor package structure 100 further includes an encapsulant 160. The encapsulant 160 covers the leadframe 110, the chip 140 and the adhesive layer 150. Preferably, the elastic modulus (modulus of elasticity) of the adhesive layer 150 may be smaller than that of the encapsulant 160. For example, under the temperature condition of 25 ℃, the elastic modulus of the encapsulant 160 is greater than 15GPa, and the elastic modulus of the adhesive layer 150 is less than 5 GPa. In other words, the adhesive layer 150 has better elasticity than the encapsulant 160, and the first corner R1 of the carrier 120 is covered by the adhesive layer 150, so as to help dissipate the stress easily concentrated at the first corner R1, reduce the phenomenon that the encapsulant 160 cracks from the first corner R1 due to thermal expansion and contraction during the temperature cycling test or the subsequent product operation, and further improve the reliability of the semiconductor package structure 100.
Referring to fig. 2, a semiconductor package structure 100A of the present embodiment is slightly different from the semiconductor package structure 100 of the previous embodiment, and further, the chip 140A and the adhesive layer 150A of the semiconductor package structure 100A of the present embodiment may extend to a portion of the top surface 131 of the leads 130, and the adhesive layer 150A further covers a portion of the second corners R2 of the leads 130. Since the adhesive layer 150A also covers the second corners R2 of the leads 130, the stress concentrated at the second corners R2 can be dissipated through the adhesive layer 150A, so that the phenomenon that the encapsulant 160 cracks from the second corners R2 due to thermal expansion and contraction during temperature cycle test or subsequent product operation can be further reduced, and the reliability of the semiconductor package structure 100A can be further improved.
Referring to fig. 3, a semiconductor package structure 100B of the present embodiment is slightly different from the semiconductor package structure 100 of the previous embodiment, and further, the carrier 120 of the semiconductor package structure 100B further has a first recess 124. The first recess 124 allows the side surface 123 to include a first side surface 123a and a second side surface 123b, and the bottom surface 122 to include a first bottom surface 122a and a second bottom surface 122 b. The first side surface 123a is farther from the center of the carrier 120 than the second side surface 123 b. The second lower surface 122b is farther from the upper surface 121 than the first lower surface 122 a. In the present embodiment, the adhesive layer 150B covers the first side surface 123a of the carrier base 120. Further, the adhesive layer 150B partially covers the first side surface 123a of the carrier 120.
With continued reference to fig. 3, a second recess 134 is formed between the top surface 131 and the sidewall 133 of the lead 130. The second recess 134 allows the sidewall 133 to include a first sidewall 133a and a second sidewall 133b, and the bottom 132 includes a first bottom 132a and a second bottom 132 b. The second sidewall 133b is farther from the susceptor 120 than the first sidewall 133 a. The second bottom surface 132b is farther from the top surface 131 than the first bottom surface 132 a. Since the molding compound 160 can be filled in the first recess 124 and the second recess 134, the probability that the carrier 120 and the leads 130 will fall off from the molding compound 160 can be reduced.
Referring to fig. 4, the semiconductor package structure 100C of the present embodiment is slightly different from the semiconductor package structure 100B of the previous embodiment, and further, the adhesive layer 150C of the semiconductor package structure 100C further extends to cover the first side surface 123a of the carrier base 120. Furthermore, the carrier 120 is generally square and has four first side surfaces 123a, and fig. 4 is a cross-sectional view of the semiconductor package 100C, only two of the first side surfaces 123a are schematically shown. In the present embodiment, the adhesive layer 150C completely covers the four first side surfaces 123a of the carrier base 120. In other embodiments, the number of the first side surfaces 123a covered by the glue layer 150C or the area covering the first side surfaces 123a may be adjusted according to the requirement, which is not limited in the present invention.
Referring to fig. 5, the semiconductor package structure 100D of the present embodiment is slightly different from the semiconductor package structure 100C of the previous embodiment, and further, the adhesive layer 150D of the semiconductor package structure 100D further encapsulates the first lower surface 122a of the carrier 120. Further, the adhesive layer 150D may completely cover the first lower surface 122a of the carrier 120 and partially cover the second side surface 123b of the carrier 120. Furthermore, the carrier base 120 is generally square and has four first side surfaces 123a and four second side surfaces 123b, and fig. 5 is a cross-sectional view of the semiconductor package structure 100D, only two of the first side surfaces 123a and two of the second side surfaces 123b are schematically shown. In the embodiment, the adhesive layer 150D completely covers the four first side surfaces 123a of the carrier 120 and partially covers the four second side surfaces 123b of the carrier 120. In other embodiments, the number of the first side surface 123a and the second side surface 123b covered by the glue layer 150D or the area covering the first side surface 123a and the second side surface 123b can be adjusted according to requirements.
Referring to fig. 6, a semiconductor package structure 100E of the present embodiment is slightly different from the semiconductor package structure 100B of the previous embodiment, and further, the chip 140A and the adhesive layer 150E of the semiconductor package structure 100E of the present embodiment may extend to the top surface 131 of a portion of the leads 130, and the adhesive layer 150E covers a portion of the second corners R2 of the leads 130. On the other hand, the adhesive layer 150E covers the first side surface 123a of the carrier 120 and the first sidewalls 133a of a portion of the leads 130. It should be noted that the number of the first side surfaces 123a covered by the glue layer 150E or the area covering the first side surfaces 123a may be adjusted as required, similar to that described in fig. 4, and is not repeated herein.
Referring to fig. 7, a semiconductor package structure 100F of the present embodiment is slightly different from the semiconductor package structure 100E of the previous embodiment, and further, the adhesive layer 150F of the semiconductor package structure 100F of the present embodiment further completely covers the first side surface 123a of the carrier base 120 and the first side walls 133a of the leads 130. It should be noted that the number of the first side surfaces 123a covered by the glue layer 150F or the area covering the first side surfaces 123a can be adjusted as required, similar to that described in fig. 4, and is not repeated herein.
Referring to fig. 8, a semiconductor package structure 100G of the present embodiment is slightly different from the semiconductor package structure 100F of the previous embodiment, and further, the adhesive layer 150G of the semiconductor package structure 100G of the present embodiment further encapsulates the first lower surface 122a of the carrier 120 and the first bottom surfaces 132a of the leads 130. Further, the glue layer 150G may partially cover the first bottom surface 132a of the lead 130. In the present embodiment, the adhesive layer 150G completely covers the first lower surface 122a of the carrier 120 and partially covers the first bottom surfaces 132a of the leads 130. It should be noted that the number of the first side surface 123a and the second side surface 123b covered by the glue layer 150G or the area covering the first side surface 123a and the second side surface 123b can be adjusted as required, similar to the description of fig. 5, and is not repeated herein.
It should be noted that the present invention does not limit the coverage of the extending adhesive layer, and all the above embodiments can be combined together, as long as the adhesive layer covers the first corner of the carrying seat, which all fall within the intended protection scope of the present invention.
In summary, the semiconductor package structure of the present invention utilizes the adhesive layer with better elasticity to cover the first corner of the carrier, which helps dissipate the stress that is easily concentrated on the first corner, so as to reduce the phenomenon that the encapsulant is cracked from the first corner due to thermal expansion and contraction during the temperature cycling test or the subsequent product operation, thereby improving the reliability of the semiconductor package structure.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (9)

1. A semiconductor package structure, comprising:
the lead frame comprises a bearing seat and a plurality of pins, wherein the bearing seat is provided with an upper surface, a lower surface opposite to the upper surface, a side surface connected with the upper surface and a first corner positioned between the upper surface and the side surface;
the chip is arranged on the upper surface of the bearing seat and is electrically connected with the pins;
the chip is connected with the bearing seat through the adhesive layer, wherein the adhesive layer covers the upper surface and part of the side surface of the bearing seat and covers the first corner of the bearing seat; and
and the packaging colloid covers the lead frame, the chip and the adhesive layer, and the elastic modulus of the adhesive layer is smaller than that of the packaging colloid.
2. The semiconductor package structure of claim 1, wherein the chip extends beyond the first corner of the carrier.
3. The semiconductor package structure of claim 2, wherein each of the leads has a top surface, a sidewall connected to the top surface, and a second corner between the top surface and the sidewall, and wherein the chip and the adhesive layer extend to a portion of the top surface of the leads, and the adhesive layer covers a portion of the second corners of the leads.
4. The semiconductor package structure of claim 1, wherein the carrier further has a first recess, the first recess causes the side surface to include a first side surface and a second side surface, and the bottom surface includes a first bottom surface and a second bottom surface, wherein the first side surface is farther from the center of the carrier than the second side surface, and the second bottom surface is farther from the top surface than the first bottom surface.
5. The semiconductor package structure of claim 4, wherein the adhesive layer covers the first side surface of the carrier.
6. The semiconductor package structure of claim 5, wherein the glue layer further encapsulates the first lower surface.
7. The semiconductor package structure according to claim 4, wherein each of the leads has a top surface, a bottom surface opposite to the top surface, a sidewall connecting the top surface, a second corner between the top surface and the sidewall, and a second recess, the second recess causes the sidewall to include a first sidewall and a second sidewall, and the bottom surface includes a first bottom surface and a second bottom surface, wherein the second sidewall is farther away from the carrier than the first sidewall, the second bottom surface is farther away from the top surface than the first bottom surface, the chip and the adhesive layer extend to a portion of the top surfaces of the leads, and the adhesive layer covers a portion of the second corner of the leads.
8. The semiconductor package structure of claim 7, wherein the adhesive layer covers the first side surface of the carrier and a portion of the first sidewalls of the plurality of leads.
9. The semiconductor package structure of claim 8, wherein the adhesive layer further covers the first lower surface of the carrier and a portion of the first bottom surfaces of the plurality of leads.
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TW107144415A TWI688057B (en) 2018-12-11 2018-12-11 Semiconductor package structure

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TWI758051B (en) * 2021-01-04 2022-03-11 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof
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