KR100762878B1 - Planner stack package - Google Patents

Planner stack package Download PDF

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KR100762878B1
KR100762878B1 KR1020060007008A KR20060007008A KR100762878B1 KR 100762878 B1 KR100762878 B1 KR 100762878B1 KR 1020060007008 A KR1020060007008 A KR 1020060007008A KR 20060007008 A KR20060007008 A KR 20060007008A KR 100762878 B1 KR100762878 B1 KR 100762878B1
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South Korea
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chip
chips
stack package
substrate
package
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KR1020060007008A
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Korean (ko)
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KR20070077404A (en
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현성호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Abstract

개시된 플래너 스택 패키지는, 기판 상에 다수의 칩이 서로 이격 적층되며, 기판과 다수의 칩 사이에 와이어 본딩되고, 칩과 와이어를 외부로부터 보호하기 위하여 EMC에 의하여 밀봉되며, 와이어는 칩 전면에 도포된 코팅액에 의하여 고정됨으로써, 칩과 칩 주변의 수축률 차이에 기인한 스트레스를 코팅액에 의하여 완충하여 칩에 크랙이 발생하는 것을 방지함에 의해 패키지의 신뢰성을 향상시킬 수 있는 효과를 제공한다.The disclosed planar stack package includes a plurality of chips spaced apart from one another on a substrate, wire bonded between the substrate and the plurality of chips, sealed by EMC to protect the chips and wires from the outside, and the wires applied to the front of the chip. By being fixed by the coated liquid, the stress caused by the difference in shrinkage between the chip and the chip is buffered by the coating liquid to prevent cracks from occurring in the chip, thereby providing an effect of improving the reliability of the package.

Description

플래너 스택 패키지{Planner stack package}Planner stack package

도 1a 및 도 1b는 종래 플래너 스택 패키지를 나타낸 평면도,1a and 1b are a plan view showing a conventional planner stack package,

도 2a 내지 도 2b는 도 1의 칩 상에 발생한 크랙을 나타낸 사진,2A and 2B are photographs showing cracks occurring on the chip of FIG. 1,

도 3은 본 발명의 일 실시예에 따른 플래너 스택 패키지를 나타낸 평면도,3 is a plan view showing a planner stack package according to an embodiment of the present invention,

도 4는 본 발명의 또 다른 실시예에 따른 플래너 스택 패키지를 나타낸 평면도.Figure 4 is a plan view showing a planner stack package according to another embodiment of the present invention.

본 발명은 플래너 스택 패키지에 관한 것으로서, 특히 칩과 칩 주변 사이의 수축률 차이에 의한 스트레스에 의하여 발생되는 칩의 크랙을 방지할 수 있는 플래너 스택 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar stack package, and more particularly, to a planar stack package capable of preventing a crack of a chip caused by stress caused by a difference in shrinkage between a chip and a chip surrounding.

일반적으로 패키지는 개개의 칩을 실제 전자 제품으로써 사용할 수 있도록 전기적인 연결을 하고, 외부의 충격에 보호되도록 밀봉 포장된 것을 말하는 것으로서, 최종 반도체 제품의 크기와 무게는 패키지(package)에 의하여 결정된다고 할 수 있다. In general, a package is a package that is electrically sealed so that individual chips can be used as actual electronic products, and is sealed to protect against external shock. The size and weight of the final semiconductor product are determined by the package. can do.

그리고 최근 전자 제품이 점차 소형화 되면서 반도체가 실장될 공간은 더욱 줄어든 반면, 전자 제품은 더욱 다기능화되고, 고성능화되기 때문에 이를 뒷받침해 줄 반도체의 종류 및 개수는 늘어나는 추세이며, 따라서 단위 체적당 실장 효율을 높이기 위하여 패키지는 얇고, 작으며, 가벼워지는 박형 패키지의 형태로 개발되고 있다.In recent years, as electronic products become smaller and smaller, space for semiconductors to be mounted is further reduced, while electronic products become more versatile and higher in performance, and thus the number and type of semiconductors to support them are increasing, thus increasing the mounting efficiency per unit volume. To increase, packages are being developed in the form of thinner, smaller and lighter packages.

이와 같은 요구에 부응하기 위하여 적층형 패키지가 출현하였는데, 그 중 플래너 스택 패키지는 기판 상에 수평적으로 다수의 칩이 실장된 형태를 말한다.In order to meet such demands, a stack type package has appeared, and a planar stack package refers to a form in which a plurality of chips are mounted horizontally on a substrate.

그런데, 이와 같은 플래너 스택 패키지에서 기판과 칩 사이의 전기적 연결을 위해 마련된 다수의 와이어의 경우, 몰딩 공정 등에서 와이어 스윕 현상이 발생되어 인접한 와이어와의 쇼트나 파손 등에 의한 패키지 불량을 일으키는 문제점이 있다.However, in the planar stack package, a plurality of wires provided for the electrical connection between the substrate and the chip have a problem in that a wire sweep occurs in a molding process, thereby causing a package defect due to shorting or breakage with an adjacent wire.

따라서, 이를 방지하기 위하여 도 1a 또는 도 1b와 같이 와이어(13) 상에 코팅액(14)을 칩(12)의 중심축 양측에 라인 형태로 도포하여 와이어(13)의 스윕(swip) 현상을 방지하고 있다.Therefore, in order to prevent this, as shown in FIG. 1A or 1B, the coating liquid 14 is applied to both sides of the central axis of the chip 12 in the form of lines on the wire 13 to prevent the sweep of the wire 13. Doing.

그런데, 이와 같은 방식에 의하여 와이어(13)를 고정하는 경우, 이어지는 후속 공정에서의 고온 흡습 테스트 시, 코팅액(14)이 도포되지 않은 칩(12)의 중심축 일측단부에 도 2a 및 도 2b와 같이 크랙(A)이 발생되는 문제점이 있다.However, in the case of fixing the wire 13 by such a method, in the subsequent high-temperature moisture absorption test in the subsequent step, the central axis one end of the chip 12 is not coated with the coating liquid 14 and 2A and 2B As a result, there is a problem that the crack (A) occurs.

여기서, 칩(12)의 중심축 일측단부는 인접한 칩(12)에 마주하는 부분으로, 이 부분에서 크랙이 발생하는 이유는 칩(12)과 칩(12) 주변 사이의 수축률 변화에 따른 스트레스의 집중에 의한 것이다. Here, one side end of the central axis of the chip 12 is a portion facing the adjacent chip 12, and the reason for cracking in this part is due to the stress caused by the change of shrinkage between the chip 12 and the periphery of the chip 12. It is by concentration.

즉, 스트레스에 대한 완충작용을 할 수 있는 코팅액(14)이 칩(12)의 중심축 에 존재하지 않아 칩(12)의 중심축 일측단부에서 크랙이 발생하는 문제점이 있다.That is, there is a problem that the coating solution 14 that can buffer the stress does not exist in the central axis of the chip 12, so that a crack occurs at one end of the central axis of the chip 12.

미설명 부호 10,10'는 플래너 스택 패키지, 15,16은 본딩 패드이다.Reference numerals 10, 10 'are planar stack packages, and 15 and 16 are bonding pads.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 칩에 크랙 발생을 방지하여 패키지의 신뢰성을 유지할 수 있도록 개선된 플래너 스택 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an improved planar stack package that can prevent cracks on a chip and maintain reliability of the package.

상기의 목적을 달성하기 위한 본 발명의 플래너 스택 패키지는, 기판 상에 다수의 칩이 서로 이격 적층되며, 상기 기판과 상기 다수의 칩 사이에 와이어 본딩되고, 상기 칩과 상기 와이어를 외부로부터 보호하기 위하여 EMC에 의하여 밀봉된 플래너 스택 패키지에 있어서, 상기 와이어는 상기 칩들 전면을 포함하여 칩들 사이에 도포된 코팅액에 의하여 고정된 것이 바람직하다.A planar stack package of the present invention for achieving the above object, a plurality of chips are stacked apart from each other on a substrate, wire bonded between the substrate and the plurality of chips, to protect the chip and the wire from the outside In the planar stack package sealed by EMC, the wire is preferably fixed by a coating liquid applied between the chips including the front of the chips.

삭제delete

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 일 실시예에 따른 플래너 스택 패키지를 나타낸 평면도이다.3 is a plan view showing a planner stack package according to an embodiment of the present invention.

도면을 참조하면, 플래너 스택 패키지(100)는 기판(110)과, 이 기판(110) 상에 서로 이격되어 적층된 다수의 칩(120)과, 기판(110)과 다수의 칩(120) 사이를 전기적으로 연결하는 다수의 와이어(130)와, 와이어(130)의 스윕 현상을 방지하기 위하여 칩(120) 상에 도포된 코팅액(140) 및 상기 칩(120)과 상기 와이어(130)를 외부로부터 보호하기 위하여 밀봉하는 EMC(미도시)를 포함한다.Referring to the drawings, the planar stack package 100 includes a substrate 110, a plurality of chips 120 stacked on the substrate 110 and spaced apart from each other, and between the substrate 110 and the plurality of chips 120. A plurality of wires 130 electrically connecting the wires, the coating liquid 140 applied on the chip 120, and the chip 120 and the wire 130 to prevent the sweeping phenomenon of the wire 130. Includes an EMC (not shown) seal to protect against.

여기서, 칩(120) 상에 도포된 코팅액(140)은 와이어(130)들을 고정시켜, 와이어(130)들 사이에 쇼트 등을 방지하기 위한 것으로, 칩(120) 상에 전면적으로 도포되거나, 도 4와 같이 칩(120) 상뿐만 아니라 칩(120)과 칩(120) 사이의 기판(110) 상에도 도포될 수 있다.Here, the coating liquid 140 applied on the chip 120 is to fix the wires 130 to prevent shorts between the wires 130, and is coated on the chip 120 entirely. As shown in FIG. 4, it may be applied not only on the chip 120 but also on the substrate 110 between the chip 120 and the chip 120.

이와 같이 와이어(130)를 고정시키기 위한 코팅액(140)을 칩(120) 상의 전면 또는 칩(120) 전면과 칩(120)들 사이의 기판(110)에도 도포하는 이유는 칩(120)과 칩(120) 주변 사이의 수축률 차이에 의한 스트레스 발생을 칩(120) 전면 등에 도포된 코팅액(140)이 완충작용을 하여 칩(120)의 중심 일측단부에서 크랙이 발생되는 것을 방지하기 위한 것이다.The reason why the coating liquid 140 for fixing the wire 130 is also applied to the front surface on the chip 120 or the substrate 110 between the front surface of the chip 120 and the chips 120 is the chip 120 and the chip. (120) This is to prevent the occurrence of cracks at the central end of the chip 120 by buffering the coating liquid 140 applied to the front surface of the chip 120, the stress generated by the difference in shrinkage between the peripheral.

즉, 칩(120) 중심의 일측단부에서 발생되는 스트레스를 코팅액(140)에 의하여 완충함으로써, 칩(120)에의 크랙 발생을 방지하여 패키지(100,100')의 신뢰성을 향상시킬 수 있게 된다.That is, by buffering the stress generated at one end of the center of the chip 120 by the coating liquid 140, it is possible to prevent the cracks generated in the chip 120 to improve the reliability of the package (100, 100 ').

미설명 부호 131은 본딩 패드이다.Reference numeral 131 is a bonding pad.

상술한 바와 같이 본 발명의 플래너 스택 패키지에 의하면, 칩 상에 코팅액을 전면 도포하여 칩과 칩 주변의 수축률 차이에 기인한 스트레스를 코팅액에 의하여 완충하여 칩에 크랙이 발생하는 것을 방지함에 의해 패키지의 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, according to the planar stack package of the present invention, the coating liquid is completely coated on the chip to prevent stress caused by the difference in shrinkage between the chip and the chip around the chip by the coating liquid to prevent cracks in the chip. It provides the effect of improving the reliability.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (2)

기판 상에 다수의 칩이 서로 이격 적층되며, 상기 기판과 상기 다수의 칩 사이에 와이어 본딩되고, 상기 칩과 상기 와이어를 외부로부터 보호하기 위하여 EMC에 의하여 밀봉된 플래너 스택 패키지에 있어서,A planar stack package in which a plurality of chips are spaced apart from each other on a substrate, wire bonded between the substrate and the plurality of chips, and sealed by EMC to protect the chips and the wires from the outside. 상기 와이어는 상기 칩들 전면을 포함하여 칩들 사이에 도포된 코팅액에 의하여 고정된 것을 특징으로 하는 플래너 스택 패키지.And the wire is fixed by a coating liquid applied between the chips, including the front of the chips. 삭제delete
KR1020060007008A 2006-01-23 2006-01-23 Planner stack package KR100762878B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9111913B2 (en) 2013-06-25 2015-08-18 Samsung Electronics Co., Ltd. Semiconductor package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
KR20040022584A (en) * 2002-09-09 2004-03-16 삼성전자주식회사 Wire bonder and wire coater in-line apparatus and manufacturing method for chip stack type multi chip package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
KR20040022584A (en) * 2002-09-09 2004-03-16 삼성전자주식회사 Wire bonder and wire coater in-line apparatus and manufacturing method for chip stack type multi chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9111913B2 (en) 2013-06-25 2015-08-18 Samsung Electronics Co., Ltd. Semiconductor package

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