KR20100002868A - Semicondutor package - Google Patents

Semicondutor package Download PDF

Info

Publication number
KR20100002868A
KR20100002868A KR1020080062917A KR20080062917A KR20100002868A KR 20100002868 A KR20100002868 A KR 20100002868A KR 1020080062917 A KR1020080062917 A KR 1020080062917A KR 20080062917 A KR20080062917 A KR 20080062917A KR 20100002868 A KR20100002868 A KR 20100002868A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
wire
film
package
semiconductor
Prior art date
Application number
KR1020080062917A
Other languages
Korean (ko)
Inventor
조철호
정관호
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080062917A priority Critical patent/KR20100002868A/en
Publication of KR20100002868A publication Critical patent/KR20100002868A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package is provided to improve reliability and productivity of the overall package by preventing short between long wires when forming a semiconductor package using a semiconductor chip of a center pad. CONSTITUTION: A semiconductor chip is attached on a substrate. A wire(112) electrically connects the semiconductor chip with the substrate. A fixing film(114) is attached on the upper side of the semiconductor chip and fixes the wire inside. An encapsulant seals one side of the substrate including the semiconductor chip, a wire, and a film.

Description

반도체 패키지{SEMICONDUTOR PACKAGE}Semiconductor Package {SEMICONDUTOR PACKAGE}

본 발명은 반도체 패키지에 관한 것으로, 보다 자세하게는, 센터 패드형의 반도체 칩을 이용한 반도체 패키지 형성시, 긴(Long) 와이어 간의 쇼트(Short)를 방지하여 전체 패키지의 생산성 및 신뢰성을 향상시킬 수 있는 반도체 패키지에 관한 것이다. The present invention relates to a semiconductor package, and more particularly, when forming a semiconductor package using a center pad-type semiconductor chip, it is possible to prevent short between long wires to improve productivity and reliability of the entire package. A semiconductor package.

반도체 패키지는, 웨이퍼(Wafer)에서 양호한 반도체 칩을 선별하여 절단하는 절단 공정과, 상기 반도체 칩을 리드 프레임의 반도체 칩 탑재 판 또는 기판 상에 접착제로 접착시키는 다이 본딩(Die Bonding) 공정과, 상기 접착된 반도체 칩과 리드 프레임의 리드 또는 기판 간을 전도성 와이어로 본딩하는 와이어 본딩(Wire Bonding) 공정과, 상기 반도체 칩 등을 외부의 환경으로부터 보호하기 위해 봉지제로 밀봉하는 봉지 공정 등을 포함하여 이루어진다.The semiconductor package includes a cutting step of selecting and cutting a good semiconductor chip from a wafer, a die bonding step of bonding the semiconductor chip with an adhesive on a semiconductor chip mounting plate or a substrate of a lead frame, A wire bonding process of bonding the bonded semiconductor chip and the lead or substrate of the lead frame with a conductive wire, and an encapsulation process of sealing the semiconductor chip with an encapsulant to protect the semiconductor chip from an external environment. .

여기서, 상기 와이어 본딩 공정을 좀더 자세히 설명하면, 웨이퍼에서 분리된 개개의 반도체 칩이 전기적 신호를 통해 고유의 기능을 발휘할 수 있도록 와이어 본딩 장치를 이용하여 반도체 칩과 그 반도체 칩을 지지하고 있는 반도체 칩 탑재판 주변에 형성된 리드 또는 기판 상의 전극단자를 미세한 전도성 와이어를 이용해 전기적 연결을 하는 공정이다.Here, the wire bonding process will be described in more detail. The semiconductor chip and the semiconductor chip supporting the semiconductor chip by using the wire bonding device are used so that individual semiconductor chips separated from the wafer can exhibit unique functions through electrical signals. The electrode terminal on the lead or the substrate formed around the mounting plate is a process of electrical connection using a fine conductive wire.

한편, 상기와 같은 전도성 와이어를 이용하는 와이어 본딩 공정은, 센터 패드 형의 반도체 칩이나, 또는, 스택 패키지에서의 상부 반도체 칩에 적용할 경우, 긴 와이어 본딩을 수행해야 하는데, 이때, 상기 코팅 용액을 상기 와이어의 상부 면이 전부 감싸지도록 코팅 용액을 충분히 이용하여 코팅해야 한다.Meanwhile, in the wire bonding process using the conductive wire as described above, when applied to a center pad semiconductor chip or an upper semiconductor chip in a stack package, long wire bonding should be performed. The coating solution should be coated with a sufficient amount so that the upper surface of the wire is completely wrapped.

그 이유는, 상기 본딩된 와이어를 코팅 용액으로 코팅 후, 상기 코팅 용액을 경화시키기 위한 큐어링 공정 수행 중, 상기 반도체 칩과 와이어 간의 상호 작용 및 상기 코팅 용액의 표면 장력에 의해 상기 코팅 용액이 와이어 앵글(Angle)이 협소한 반도체 칩 방향으로 끌려가 소망하는 와이어 부분을 지지해주지 못하는 현상인 스위핑(Sweeping)이 발생하기 때문이다. The reason is that, after coating the bonded wire with a coating solution, during the curing process for curing the coating solution, the coating solution is wired due to the interaction between the semiconductor chip and the wire and the surface tension of the coating solution. This is because sweeping, a phenomenon in which an angle is pulled toward a narrow semiconductor chip and cannot support a desired wire part, occurs.

따라서, 상기와 같은 스위핑 현상을 서로 이웃한 긴 와이어들 간의 쇼트(Short)를 발생시키게 된다.Therefore, the above sweeping phenomenon causes short between the long wires adjacent to each other.

게다가, 와이어를 고정시키기 위해 전술한 바와 같이 코팅 용액을 사용하게 되면, 상기 코팅 용액을 경화시키기 위한 고온의 큐어링 공정이 필수적으로 요구되기 때문에, 그에 따른 생산성 저하 및 패키지의 신뢰성을 저하시키게 된다.In addition, the use of the coating solution as described above to fix the wire, since a high temperature curing process for curing the coating solution is essentially required, thereby lowering productivity and reliability of the package.

한편, 상기와 같은 와이어의 스위핑의 발생을 방지하고자, 코팅 용액을 너무 적게 코팅할 경우, 소망하는 와이어 부분을 고정시키지 못하게 되어 와이어 불량의 또 다른 문제점을 야기시키게 된다.On the other hand, in order to prevent the occurrence of the sweeping of the wire, when coating the coating solution too little, it is impossible to fix the desired wire portion, causing another problem of the wire failure.

따라서, 와이어의 스위핑 현상을 방지하면서도 전체 패키지의 신뢰성 저하를 방지할 수 있는 반도체 패키지가 요구되고 있는 실정이다.Therefore, there is a demand for a semiconductor package capable of preventing a wire sweeping phenomenon and preventing a decrease in reliability of the entire package.

본 발명은 와이어의 스위핑 현상에 따른 긴 와이어 간의 쇼트를 방지할 수 있는 반도체 패키지를 제공한다.The present invention provides a semiconductor package that can prevent a short between the long wires due to the sweeping phenomenon of the wire.

또한, 본 발명은 큐어링 공정을 수행하지 않고도 생산성 및 신뢰성 저하를 방지할 수 있는 반도체 패키지를 제공한다.In addition, the present invention provides a semiconductor package capable of preventing productivity and reliability deterioration without performing a curing process.

본 발명에 따른 반도체 패키지는, 기판; 상기 기판 상에 부착된 반도체 칩; 상기 반도체 칩과 기판 간을 전기적으로 연결하는 와이어; 상기 반도체 칩 상면에 부착되며, 상기 와이어를 내부에 고정시키는 고정 필름; 및 상기 고정 필름, 와이어 및 반도체 칩을 포함한 기판의 일면을 밀봉하는 봉지제;를 포함한다.The semiconductor package according to the present invention, the substrate; A semiconductor chip attached on the substrate; A wire electrically connecting the semiconductor chip to a substrate; A fixing film attached to an upper surface of the semiconductor chip and fixing the wire therein; And an encapsulant for sealing one surface of the substrate including the fixing film, the wire, and the semiconductor chip.

상기 고정 필름은 열 경화성 필름을 포함한다.The fixed film includes a thermosetting film.

상기 고정 필름은 열 경화성 필름으로 이루어진 단일 층 구조를 포함한다.The fixed film includes a single layer structure consisting of a heat curable film.

상기 고정 필름은 제1필름과, 상기 제1필름 보다 경도가 높은 제2필름의 적층 구조를 포함한다.The fixed film includes a laminated structure of a first film and a second film having a higher hardness than the first film.

상기 고정 필름은 상기 와이어를 포함한 상기 반도체 칩의 상면 일부분 상에 아일랜드(Island) 타입으로 부착된 것을 특징으로 한다.The fixing film is attached to an island type on a portion of the upper surface of the semiconductor chip including the wire.

상기 고정 필름은 상기 반도체 칩의 가장자리를 제외한 상면 전체에 부착된 것을 특징으로 한다.The fixing film is attached to the entire upper surface except the edge of the semiconductor chip.

본 발명은 센터 패드형의 반도체 칩을 이용한 반도체 패키지 형성시, 상기 반도체 칩과 기판 간을 연결하는 와이어를 상기 반도체 칩 상에 형성시킨 열 경화성 필름과 같은 고정 필름을 매개로 하여 고정시킴으로써, 종래의 코팅 용액을 사용함에 따른 와이어의 스위핑 발생을 방지할 수 있다.According to the present invention, when the semiconductor package is formed using a center pad semiconductor chip, the wire connecting the semiconductor chip and the substrate is fixed through a fixing film such as a thermosetting film formed on the semiconductor chip. It is possible to prevent the occurrence of sweeping of the wire by using the coating solution.

따라서, 본 발명은 상기와 같이 스위핑 현상을 방지할 수 있으므로, 긴 와이어 간의 쇼트를 방지할 수 있다.Therefore, the present invention can prevent the sweeping phenomenon as described above, it is possible to prevent the short between the long wires.

게다가, 본 발명은 열 경화성 필름만을 이용하여 와이어를 고정시킴으로써, 코팅 용액을 이용한 종래의 반도체 패키지와 같이 상기 코팅 용액을 경화시키기 위한 큐어링 공정을 수행하지 않아도 되므로, 그에 따른 전체 생산성 및 패키지의 신뢰성을 향상시킬 수 있다.In addition, the present invention does not require a curing process for curing the coating solution, such as a conventional semiconductor package using a coating solution, by fixing the wire using only a heat curable film, thereby resulting in overall productivity and package reliability. Can improve.

본 발명은, 센터 패드형의 반도체 칩을 이용한 반도체 패키지 형성시, 상기 반도체 칩과 기판 간을 연결하는 와이어를 상기 반도체 칩 상에 형성시킨 열 경화성 필름과 같은 고정 필름을 매개로 하여 고정시킨다.When forming a semiconductor package using the center pad type semiconductor chip, this invention fixes the wire which connects the said semiconductor chip and a board | substrate through the fixing film like the thermosetting film formed on the said semiconductor chip.

이렇게 하면, 상기 와이어를 고정시키기 위해 코팅 용액을 이용하는 종래의 반도체 패키지와 달리, 상기와 같이 반도체 칩 상에 형성하는 열 경화성 필름과 같은 고정 필름을 매개로 고정시킴으로써, 상기 코팅 용액을 경화시키기 위한 큐어링 공정 수행 중, 상기 반도체 칩과 와이어 간의 상호 작용 및 상기 코팅 용액의 표면 장력에 의해 상기 코팅 용액이 와이어 앵글이 협소한 반도체 칩 방향으로 끌려가 소망하는 와이어 부분을 지지해주지 못하는 스위핑의 발생을 방지할 수 있다.In this way, unlike a conventional semiconductor package that uses a coating solution to fix the wire, a curing film for curing the coating solution by fixing a fixing film such as a thermosetting film formed on a semiconductor chip as described above. During the ring process, due to the interaction between the semiconductor chip and the wire and the surface tension of the coating solution, the coating solution is attracted toward the semiconductor chip having a narrow wire angle, thereby preventing the occurrence of sweeping that does not support the desired wire portion. can do.

따라서, 상기와 같이 스위핑 현상을 방지할 수 있으므로, 긴 와이어 간의 쇼트를 방지할 수 있다.Therefore, the sweeping phenomenon can be prevented as described above, so that short between long wires can be prevented.

게다가, 상기와 같이 열 경화성 필름만을 이용하여 와이어를 고정시킴으로써, 코팅 용액을 이용한 종래의 반도체 패키지와 같이 상기 코팅 용액을 경화시키기 위한 큐어링 공정을 수행하지 않아도 되므로, 그에 따른 전체 생산성 및 패키지의 신뢰성을 향상시킬 수 있다.In addition, by fixing the wire using only the heat curable film as described above, it is not necessary to perform a curing process for curing the coating solution as in the conventional semiconductor package using the coating solution, thereby resulting in overall productivity and package reliability Can improve.

이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

자세하게, 도 1은 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도시된 바와 같이 본 발명의 실시예에 따른 반도체 패키지(100)는, 일면에 다수의 전극단자(104)를 갖는 기판(102) 상에 센터 패드 타입의 다수의 본딩패드(110)를 갖는 반도체 칩(108)이 접착제(106)를 매개로 부착되며, 상기 접착제(106)를 매개로 부착된 상기 반도체 칩(108)과 상기 기판(102) 간은, 상기 반도체 칩(108)의 본딩패드(110)와 상기 기판(102)의 전극단자(104) 간을 연결하는 와이어(112)에 의해 전기적으로 연결된다.As shown, the semiconductor package 100 according to the embodiment of the present invention includes a semiconductor chip having a plurality of bonding pads 110 of a center pad type on a substrate 102 having a plurality of electrode terminals 104 on one surface thereof. A bond 108 is attached via the adhesive 106, and the bonding pad 110 of the semiconductor chip 108 is disposed between the semiconductor chip 108 and the substrate 102 attached via the adhesive 106. ) And the wire 112 connecting the electrode terminal 104 of the substrate 102 is electrically connected.

상기 반도체 칩(108) 상면에는 그 내부에 상기 와이어(112)를 통과함과 아울러, 상기 반도체 칩(108)의 상면 가장자리 부분을 제외한 반도체 칩(108)의 상면 전체 부착되는 구조로 이루어져, 상기 와이어(112)를 고정시키는 고정 필름(114)이 형성된다.An upper surface of the semiconductor chip 108 is formed to pass through the wire 112 therein and to attach the entire upper surface of the semiconductor chip 108 except for an upper edge portion of the semiconductor chip 108. A fixing film 114 for fixing 112 is formed.

또한,상기 고정 필름(114), 와이어(112) 및 반도체 칩(108)을 포함하는 기판(120)의 일면을 상기 반도체 칩(108)을 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy Molding Compound)와 같은 봉지제(116)로 밀봉된다.In addition, in order to protect the semiconductor chip 108 from external stress on one surface of the substrate 120 including the fixing film 114, the wire 112, and the semiconductor chip 108, an EMC molding compound (EMC) may be used. The same encapsulant 116 is sealed.

이때, 상기 고정 필름(114)은 열 경화성 필름으로 이루어진다.At this time, the fixing film 114 is made of a thermosetting film.

게다가, 상기 기판(102)의 타면에는 실장수단으로서 솔더 볼과 같은 다수의 외부 접속 단자(118)가 부착된다.In addition, a plurality of external connection terminals 118 such as solder balls are attached to the other surface of the substrate 102 as mounting means.

한편, 도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도로서, 본 발명의 다른 실시예에 따른 반도체 패키지(200)는 상기 고정 필름(114)을, 전술한 본 발명의 실시예에서와 같은 단일 층 구조가 아닌 제1필름(114a)과, 상기 제1필름(114a) 보다 경도가 높은 제2필름(114b)의 적층 구조로도 형성될 수 있다.2 is a cross-sectional view illustrating a semiconductor package according to another exemplary embodiment of the present invention, and the semiconductor package 200 according to another exemplary embodiment of the present invention may include the fixing film 114 as described above. It may also be formed as a laminated structure of the first film 114a and the second film 114b having a higher hardness than the first film 114a, rather than a single layer structure as in the embodiment of the present invention.

이 경우, 본 발명은 상기 제1필름(114a) 상에 형성된, 상기 제1필름(114a) 보다 경도가 높은 제2필름(114b)으로 인해, 상기 와이어(112)가 상기 고정 필름(114)을 통과하지 못하게 할 수 있으므로, 상기 와이어(112)의 높이를 인위적으로 제한할 수 있다.In this case, according to the present invention, due to the second film 114b having higher hardness than the first film 114a formed on the first film 114a, the wire 112 may be used to fix the fixed film 114. Since it can not be passed through, it is possible to artificially limit the height of the wire (112).

따라서, 상기와 같이 와이어(112)의 높이를 인위적으로 제한할 수 있으므로, 상기 제1필름(114a) 및 제2필름(114b)으로 이루어진 고정 필름(114)을 적용한 반도체 패키지 형성시, 상기 와이어(112)의 높이를 항상 일정하게 조절할 수 있다.Therefore, since the height of the wire 112 may be artificially limited as described above, the wire (when forming a semiconductor package to which the fixing film 114 consisting of the first film 114a and the second film 114b is applied) is formed. The height of 112 can always be adjusted constantly.

또한, 도 3은 본 발명의 또 다른 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도로서, 본 발명의 또 다른 실시예에 따른 반도체 패키지(300)는 전술한 바와 같은 상기 반도체 칩(108)의 상면 가장자리 부분을 제외한 반도체 칩(108)의 상면 전체 부착되는 구조를 갖는 고정 필름(114)이 아닌 와이어(112)를 포함한 반도체 칩(108)의 상부에 선택적인 아일랜드 타입으로 형성되어 상기 와이어(112)를 고정시킬 수 있다.3 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention. The semiconductor package 300 according to another embodiment of the present invention may include the semiconductor chip 108 as described above. An island type is formed on the upper portion of the semiconductor chip 108 including the wire 112 instead of the fixing film 114 having the structure attached to the entire upper surface of the semiconductor chip 108 except for the upper edge portion of the wire. 112) can be fixed.

전술한 바와 같이 본 발명은, 상기와 같이 반도체 칩과 기판 간을 연결하는 와이어를 상기 반도체 칩 상에 형성시킨 열 경화성 필름과 같은 고정 필름을 매개로 하여 고정시킴으로써, 종래의 코팅 용액을 경화시키기 위한 큐어링 공정 수행 중, 상기 반도체 칩과 와이어 간의 상호 작용 및 상기 코팅 용액의 표면 장력에 의해 상기 코팅 용액이 와이어 앵글이 협소한 반도체 칩 방향으로 끌려가 소망하는 와이어 부분을 지지해주지 못하는 스위핑의 발생을 방지할 수 있다.As described above, the present invention provides a method for curing a conventional coating solution by fixing a wire connecting a semiconductor chip and a substrate as described above through a fixing film such as a thermosetting film formed on the semiconductor chip. During the curing process, due to the interaction between the semiconductor chip and the wire and the surface tension of the coating solution, the coating solution is dragged in the direction of the semiconductor chip having a narrow wire angle to prevent the occurrence of sweeping that does not support the desired wire portion. It can prevent.

따라서, 상기와 같이 스위핑 현상을 방지할 수 있으므로, 긴 와이어 간의 쇼트를 방지할 수 있다.Therefore, the sweeping phenomenon can be prevented as described above, so that short between long wires can be prevented.

게다가, 상기와 같이 열 경화성 필름만을 이용하여 와이어를 고정시킴으로써, 코팅 용액을 이용한 종래의 반도체 패키지와 같이 상기 코팅 용액을 경화시키기 위한 큐어링 공정을 수행하지 않아도 되므로, 그에 따른 전체 생산성 및 패키지의 신뢰성을 향상시킬 수 있다.In addition, by fixing the wire using only the heat-curable film as described above, it is not necessary to perform a curing process for curing the coating solution as in the conventional semiconductor package using the coating solution, thereby resulting in overall productivity and package reliability Can improve.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있 다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도.1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도2 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

도 3은 본 발명의 또 다른 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도3 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

Claims (6)

기판;Board; 상기 기판 상에 부착된 반도체 칩;A semiconductor chip attached on the substrate; 상기 반도체 칩과 기판 간을 전기적으로 연결하는 와이어;A wire electrically connecting the semiconductor chip to a substrate; 상기 반도체 칩 상면에 부착되며, 상기 와이어를 내부에 고정시키는 고정 필름; 및A fixing film attached to an upper surface of the semiconductor chip and fixing the wire therein; And 상기 고정 필름, 와이어 및 반도체 칩을 포함한 기판의 일면을 밀봉하는 봉지제;An encapsulant for sealing one surface of a substrate including the fixing film, a wire, and a semiconductor chip; 를 포함하는 것을 특징으로 하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 고정 필름은 열 경화성 필름을 포함하는 것을 특징으로 하는 반도체 패키지.The fixing film comprises a thermosetting film. 제 1 항에 있어서,The method of claim 1, 상기 고정 필름은 열 경화성 필름으로 이루어진 단일 층 구조를 포함하는 것을 특징으로 하는 반도체 패키지.The fixing film comprises a single layer structure consisting of a thermosetting film. 제 1 항에 있어서,The method of claim 1, 상기 고정 필름은 제1필름과, 상기 제1필름 보다 경도가 높은 제2필름의 적층 구조를 포함하는 것을 특징으로 하는 반도체 패키지.The fixing film is a semiconductor package, characterized in that it comprises a laminated structure of the first film and the second film having a higher hardness than the first film. 제 1 항에 있어서,The method of claim 1, 상기 고정 필름은 상기 와이어를 포함한 상기 반도체 칩의 상면 일부분 상에 아일랜드(Island) 타입으로 부착된 것을 특징으로 하는 반도체 패키지.The fixing film is a semiconductor package, characterized in that attached to the island portion (Island) type on the upper portion of the semiconductor chip including the wire. 제 1 항에 있어서,The method of claim 1, 상기 고정 필름은 상기 반도체 칩의 가장자리를 제외한 상면 전체에 부착된 것을 특징으로 하는 반도체 패키지.The fixing film is a semiconductor package, characterized in that attached to the entire upper surface except the edge of the semiconductor chip.
KR1020080062917A 2008-06-30 2008-06-30 Semicondutor package KR20100002868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080062917A KR20100002868A (en) 2008-06-30 2008-06-30 Semicondutor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080062917A KR20100002868A (en) 2008-06-30 2008-06-30 Semicondutor package

Publications (1)

Publication Number Publication Date
KR20100002868A true KR20100002868A (en) 2010-01-07

Family

ID=41812846

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080062917A KR20100002868A (en) 2008-06-30 2008-06-30 Semicondutor package

Country Status (1)

Country Link
KR (1) KR20100002868A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281267B1 (en) 2014-08-21 2016-03-08 SK Hynix Inc. Semiconductor package having overhang portion
US11133287B2 (en) 2019-08-20 2021-09-28 SK Hynix Inc. Semiconductor package including stacked semiconductor chips and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281267B1 (en) 2014-08-21 2016-03-08 SK Hynix Inc. Semiconductor package having overhang portion
US11133287B2 (en) 2019-08-20 2021-09-28 SK Hynix Inc. Semiconductor package including stacked semiconductor chips and method for fabricating the same

Similar Documents

Publication Publication Date Title
JP5227501B2 (en) Stack die package and method of manufacturing the same
US8049339B2 (en) Semiconductor package having isolated inner lead
US6208018B1 (en) Piggyback multiple dice assembly
JP5543086B2 (en) Semiconductor device and manufacturing method thereof
KR20040024163A (en) Semiconductor chip package that adhesive tape is attached on the bonding wire
KR100825784B1 (en) Semiconductor package suppressing a warpage and wire open defects and manufacturing method thereof
US20090051019A1 (en) Multi-chip module package
JP2012009655A (en) Semiconductor package and method of manufacturing the semiconductor package
US7161232B1 (en) Apparatus and method for miniature semiconductor packages
TW200504963A (en) Multi-chip semiconductor package and manufacturing method thereof
KR20020068709A (en) Dual die package and manufacturing method thereof
KR20100002868A (en) Semicondutor package
TWI692042B (en) Semiconductor package structure and manufacturing method thereof
KR100923999B1 (en) Fabrication method of Structure of Stack Semiconductor Package Without PCB
JP2005327967A (en) Semiconductor device
KR20090056561A (en) Semiconductor package
KR20070028067A (en) Semiconductor package
US7781898B2 (en) IC package reducing wiring layers on substrate and its chip carrier
US7638880B2 (en) Chip package
KR20070079654A (en) Printed circuit board for flip chip bonding and ball grid array package manufacturing method using the same
JP4096778B2 (en) Multi-chip package
KR20040059902A (en) Method for packaging double side stack in semiconductor
KR20220064562A (en) Multi-chip stack semiconductor package and method of manufacturing the same
KR100668865B1 (en) Fbga package with dual bond finger
KR20090098074A (en) Method of fabricating stack package

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid