KR100650769B1 - Stack type package - Google Patents

Stack type package Download PDF

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Publication number
KR100650769B1
KR100650769B1 KR1020050110709A KR20050110709A KR100650769B1 KR 100650769 B1 KR100650769 B1 KR 100650769B1 KR 1020050110709 A KR1020050110709 A KR 1020050110709A KR 20050110709 A KR20050110709 A KR 20050110709A KR 100650769 B1 KR100650769 B1 KR 100650769B1
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South Korea
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sub
package
substrate
stacked
chip
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KR1020050110709A
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Korean (ko)
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임상준
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A stacked package is provided to improve joint reliability and to easily obtain package assembly by using a first and a second sub-packages having the same design pattern. A stacked package(100) comprises a substrate(110) having a solder ball(111), a first sub-package(120), and a second sub-package(130). The first sub-package is provided with an upper chip(122) and a lower chip(123) having each center pad(124). The lower chip is bonded downward to a sub substrate(121) through an opening of the sub substrate, and the upper chip is bonded upward to the sub substrate. The second sub-package has the same structure to the first sub-package.

Description

적층형 패키지{Stack type package}Stack type package

도 1은 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도,1 is a cross-sectional view showing a stacked package according to an embodiment of the present invention;

도 2는 본 발명의 또 다른 실시예에 따른 적층형 패키지를 나타낸 단면도.2 is a cross-sectional view showing a stacked package according to another embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100... 적층형 패키지 110... 기판100 ... Stacked Package 110 ... Board

120... 제1 서브 패키지 130... 제2 서브 패키지120 ... first subpackage 130 ... second subpackage

본 발명은 적층형 패키지에 관한 것으로서, 특히 다수의 칩이 내장된 서브 패키지 다수를 적층하여 마련된 적층형 패키지에 관한 것이다. The present invention relates to a stacked package, and more particularly, to a stacked package provided by stacking a plurality of sub-packages in which a plurality of chips are embedded.

반도체 패키지는 웨이퍼 공정에 의해 만들어진 개개의 다이를 실제 전자 부품으로써 사용할 수 있도록 전기적 연결을 해주고, 외부의 충격으로부터 보호되도록 밀봉 포장한 것을 말하며, 최근 고용량, 고집적, 초소형화된 반도체 제품에 대한 요구에 부응하기 위해 다양한 반도체 패키지들이 개발되고 있다.A semiconductor package is a package that is electrically sealed so that individual dies made by a wafer process can be used as actual electronic components, and is sealed to protect against external shocks. Various semiconductor packages are being developed to meet this.

이러한 다양한 반도체 패키지 중 고용량, 고집적화 등을 만족시키기 위하여 다수의 칩이 적층되거나, 또는 다수의 패키지를 적층한 적층형 패키지가 출현하였 다.Among these various semiconductor packages, in order to satisfy high capacity, high integration, etc., a plurality of chips are stacked or a stacked package in which a plurality of packages are stacked.

그런데, 이러한 적층형 패키지 중 다수의 패키지가 적층된 적층형 패키지의 경우, 4개의 칩을 포함하기 위하여는 4개의 패키지를 제조한 후, 이 4개의 패키지를 적층함에 의하여 적층형 패키지를 제조하였는데, 이는 패키지 간에 전기적 연결을 솔더 볼에 의하기 때문에 층간 패키지의 디자인 패턴이 서로 상이하여 서로 쇼트될 염려가 있고, 또한 많은 솔더 볼을 사용하기 때문에 볼 크랙과 같은 볼 접합 신뢰성이 떨어져 불량 발생률이 증가되는 문제점이 있다.However, in the case of a stacked package in which a plurality of packages of these stacked packages are stacked, four packages are manufactured to include four chips, and then a stacked package is manufactured by stacking the four packages. Since the electrical connection is made by solder balls, there is a concern that the design patterns of the interlayer packages are different from each other and may be shortened to each other. Also, since a large number of solder balls are used, ball joint reliability, such as ball cracks, may be degraded, resulting in an increase in defect rate.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 패키지 적층 구조를 변경하여 적층형 패키지의 신뢰성 향상 및 불량 발생을 줄일 수 있는 개선된 적층형 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an improved stacked package that can improve package reliability by reducing package stack structure and reducing defects.

상기의 목적을 달성하기 위한 본 발명의 적층형 패키지는, 일측에 솔더 볼이 마련된 기판; 상기 기판 타측 상에 적층되고, 중앙에 개구부가 형성된 서브 기판 상에 서로 반대 방향을 향하도록 센터 패드가 마련된 상하부 칩이 적층되며, 상기 하부 칩은 상기 서브 기판의 개구부를 통해 상기 서브 기판과 와이어 본딩되며, 상기 상부 칩은 상기 서브 기판과 와이어 본딩되는 제1 서브 패키지; 및 상기 제1 서브 패키지와 동일한 구조로, 상기 제1 서브 패키지 타측 상에 적층되는 제2 서브 패키지를 포함한 것이 바람직하다.Laminated package of the present invention for achieving the above object, the substrate is provided with a solder ball on one side; The upper and lower chips stacked on the other side of the substrate and provided with center pads facing each other on the sub substrate having an opening formed in the center thereof are stacked, and the lower chip is wire-bonded with the sub substrate through the opening of the sub substrate. The upper chip may include a first sub package wire-bonded with the sub substrate; And a second subpackage having the same structure as the first subpackage and stacked on the other side of the first subpackage.

여기서, 상기 제1,2 서브 패키지 각각은 상기 서브 기판 각각이 상부에 위치 하도록 상기 기판 일측에 적층된 것이 바람직하다.Here, each of the first and second sub-packages is preferably stacked on one side of the substrate such that each of the sub-substrates is located above.

그리고 본 발명의 또 다른 적층형 패키지는, 일측에 솔더 볼이 마련된 기판; 상기 기판 타측에 적층되며, 서브 기판과, 상기 서브 기판 양측 각각에 실장되며, 범프에 의하여 상기 서브 기판과 전기적으로 연결된 칩 및 상기 기판 측에 실장된 칩을 밀봉하는 EMC를 포함한 제1 서브 패키지; 및 상기 제1 서브 패키지와 동일한 구조로, 상기 제1 서브 패키지 상에 적층되는 제2 서브 패키지를 포함한 것이 바람직하다.And another laminated package of the present invention, the substrate is provided with a solder ball on one side; A first sub package stacked on the other side of the substrate, the first sub package including a sub substrate, a chip mounted on each side of the sub substrate, the chip electrically connected to the sub substrate by bumps, and an EMC sealing the chip mounted on the substrate side; And a second sub-package stacked on the first sub-package in the same structure as the first sub-package.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도이다.1 is a cross-sectional view showing a stacked package according to an embodiment of the present invention.

도면을 참조하면, 적층형 패키지(100)는 일측에 솔더 볼(111)이 마련된 기판(110)과, 이 기판(110) 타측 상에 적층된 제1 서브 패키지(120) 및 제1 서브 패키지(120) 타측 상에 적층된 제2 서브 패키지(130)를 포함한다.Referring to the drawings, the stacked package 100 includes a substrate 110 having a solder ball 111 on one side thereof, a first sub package 120 and a first sub package 120 stacked on the other side of the substrate 110. ) A second sub-package 130 stacked on the other side.

제1 서브 패키지(120)는 중앙에 개구부(126)가 형성된 서브 기판(121)과, 이 서브 기판(121) 상에 접착 테입(128)에 의하여 적층된 하부 칩(122) 및 이 하부 칩(122) 상에 적층된 상부 칩(123)을 포함한다.The first sub-package 120 includes a sub-substrate 121 having an opening 126 formed in the center thereof, a lower chip 122 and a lower chip 122 stacked on the sub-substrate 121 by adhesive tape 128. And an upper chip 123 stacked on 122.

하부 칩(122)과 상부 칩(123)에는 모두 센터 패드(124)가 마련되는데, 상부 칩(123)의 경우 에지 패드도 가능하다.Both the lower chip 122 and the upper chip 123 are provided with a center pad 124. In the case of the upper chip 123, an edge pad is also possible.

이 하부 칩(122)과 서브 기판(121)은 와이어(125a) 본딩에 의하여 전기적으로 연결되는데, 이 전기적 연결은 서브 기판(121)에 형성된 개구부(126)를 통해 이 루어진다.The lower chip 122 and the sub-substrate 121 are electrically connected by wire 125a bonding, and the electrical connection is made through the opening 126 formed in the sub-substrate 121.

그리고 상부 칩(123)은 상부 칩에 마련된 센터 패드(124) 또는 에지 패드와 서브 기판(121)이 와이어(125b) 본딩에 의하여 전기적으로 연결된다.In addition, the upper chip 123 is electrically connected to the center pad 124 or the edge pad and the sub substrate 121 provided in the upper chip by the wire 125b bonding.

따라서, 하부 칩(122)에 마련된 센터 패드(124a)와 상부 칩(123)에 마련된 센터 패드(124b) 또는 에지 패드는 서로 반대 방향을 향하도록, 즉 하부 칩(122)에 마련된 센터 패드(124a)는 하부를, 상부 칩(123)에 마련된 센터 패드(124b) 또는 에지 패드는 상부를 향하도록 마련된다.Therefore, the center pad 124a provided in the lower chip 122 and the center pad 124b or the edge pad provided in the upper chip 123 face the opposite directions, that is, the center pad 124a provided in the lower chip 122. ) Is provided at the lower side, and the center pad 124b or the edge pad provided at the upper chip 123 is provided upward.

그리고 이와 같이 서브 기판(121) 상에 적층된 상하부 칩(122,123) 및 와이어(125)를 외부로부터 보호하기 위하여 EMC(127)에 의하여 몰딩된다.The upper and lower chips 122 and 123 and the wire 125 stacked on the sub-substrate 121 are molded by the EMC 127 to protect them from the outside.

이와 같은 구조의 제1 서브 패키지(120)는 기판(110) 타측에 접착 테입(128)에 의하여 적층되는데, 이 기판(110) 타측에 적층 시, 그 구조는 서브 기판(121)이 상부로 가도록 칩(122,123) 등을 몰딩한 EMC(127)가 접착 테입(128)에 의하여 기판(110)에 적층된 구조이다.The first sub-package 120 having such a structure is laminated by the adhesive tape 128 on the other side of the substrate 110, and when the other sub-package 110 is stacked on the other side of the substrate 110, the sub-substrate 121 goes upward. The EMC 127 molding the chips 122 and 123 is stacked on the substrate 110 by the adhesive tape 128.

제2 서브 패키지(130)는 제1 서브 패키지(120)와 동일한 구조로, 제1 서브 패키지(120) 상에 적층되며, 그 적층되는 방식도 기판(110) 상에 제1 서브 패키지(120)가 적층되는 형태와 같이 서브 기판(131)이 상부로 가도록 적층된다.The second subpackage 130 has the same structure as the first subpackage 120, and is stacked on the first subpackage 120, and the manner in which the second subpackage 130 is stacked is the first subpackage 120 on the substrate 110. Like the stacked form, the sub substrate 131 is stacked to go upward.

그리고 제1 서브 패키지(120)와 제2 서브 패키지(130)는 기판(110)과 전기적으로 연결되도록 와이어(125c) 본딩이 되고, 제1 서브 패키지(120)와 제2 서브 패키지(130) 및 와이어(125c)를 외부로부터 보호하기 위하여 EMC(140) 몰딩된다.The first sub-package 120 and the second sub-package 130 are bonded to the wire 125c to be electrically connected to the substrate 110, and the first sub-package 120 and the second sub-package 130 and The EMC 140 is molded to protect the wire 125c from the outside.

도 2는 본 발명의 또 다른 실시예에 따른 적층형 패키지를 나타낸 단면도이 다.2 is a cross-sectional view showing a stacked package according to another embodiment of the present invention.

도면을 참조하면, 적층형 패키지(200)는 일측에 솔더 볼(211)이 마련된 기판(210)과, 이 기판(210) 타측에 적층된 제1 서브 패키지(220) 및 제1 서브 패키지(220) 상에 적층된 제2 서브 패키지(230)를 포함한다.Referring to the drawings, the stacked package 200 includes a substrate 210 having a solder ball 211 provided at one side thereof, a first sub package 220 and a first sub package 220 stacked at the other side of the substrate 210. And a second sub-package 230 stacked on.

제1 서브 패키지(220)는 서브 기판(221)과, 이 서브 기판(221) 양측에 각각 적층된 칩(222) 및 서브 기판(221)과 칩(222) 사이를 전기적으로 연결하는 범프(224)를 포함한다.The first sub-package 220 includes a sub-substrate 221 and chips 222 stacked on both sides of the sub-substrate 221 and bumps 224 electrically connecting the sub-substrate 221 and the chip 222, respectively. ).

여기서, 칩(222)에는 센터 패드(223) 또는 에지 패드가 마련되며, 패드(223)의 위치에 따라 범프(224)의 위치도 센터 또는 에지 중 어느 한 곳에 마련된다.Here, the chip 222 is provided with a center pad 223 or an edge pad, and according to the position of the pad 223, the position of the bump 224 is also provided at either the center or the edge.

그리고 서브 기판(221) 하부에는 서브 기판(221) 하부에 적층된 칩(222)을 외부로부터 보호하기 위하여 EMC(225) 몰딩이 되어 있으며, 이 몰딩된 EMC(225)가 접착 테입(227)에 의하여 기판(210)에 부착 적층되며, 서브 기판(221)과 기판(210) 사이에는 전기적 연결을 위하여 와이어(226a) 본딩된다.In order to protect the chip 222 stacked under the sub-substrate 221 from the outside, an EMC 225 molding is performed on the lower part of the sub-substrate 221, and the molded EMC 225 is attached to the adhesive tape 227. By attaching and stacking the substrate 210, a wire 226a is bonded between the sub-substrate 221 and the substrate 210 for electrical connection.

제2 서브 패키지(230)는 제1 서브 패키지(220)와 동일한 구조로, 제1 서브 패키지(220) 상에 적층되는데, 그 적층되는 모습은 제1 서브 패키지(220)에서 EMC(225)에 의하여 몰딩되지 않은 칩(222b) 상에 제2 서브 패키지(230)의 EMC(235)가 접착 테입(227)에 의하여 부착 적층된 형태로 제2 서브 패키지(230)의 서브 기판(231)과 기판(210) 사이에는 전기적 연결을 위하여 와이어(226b) 본딩된다.The second subpackage 230 has the same structure as that of the first subpackage 220, and is stacked on the first subpackage 220. The stacking state of the second subpackage 230 is transferred from the first subpackage 220 to the EMC 225. The sub-substrate 231 and the substrate of the second sub-package 230 in a form in which the EMC 235 of the second sub-package 230 is adhered and laminated by the adhesive tape 227 on the chip 222b that is not molded by the chip. The wires 226b are bonded between the 210 for electrical connection.

그리고 제1,2 서브 패키지(220,230)를 외부로부터 보호하기 위하여 기판(210) 상에는 EMC(240)에 의하여 몰딩된다.In order to protect the first and second sub-packages 220 and 230 from the outside, the first and second sub-packages 220 and 230 are molded by the EMC 240 on the substrate 210.

이와 같은 구조의 적층형 패키지는 제1,2 서브 패키지의 디자인 패턴이 동일하기 때문에 접합 신뢰성 측면에서 우수하고, 패키지의 조립 또한 용이하게 할 수 있다.The stacked package having such a structure is excellent in terms of bonding reliability because of the same design pattern of the first and second sub-packages, and can also facilitate assembly of the package.

그리고 기판과 서브 패키지 사이의 최종적인 전기적 연결을 와이어 본딩에 의하므로 전기적 연결의 유연성을 증가시킬 수 있고, 솔더 볼 사용 개수가 일반 단품 패키지의 수량과 비슷하여 볼 신뢰성을 향상시킬 수 있다. And the final electrical connection between the substrate and the sub-package by wire bonding can increase the flexibility of the electrical connection, the number of solder balls used is similar to the number of single unit package can improve the ball reliability.

상술한 바와 같이 본 발명의 적층형 패키지에 의하면, 제1,2 서브 패키지의 디자인 패턴이 동일하기 때문에 접합 신뢰성 측면에서 우수하고, 패키지의 조립 또한 용이하게 할 수 있는 효과를 제공한다.As described above, according to the stacked package of the present invention, since the design patterns of the first and second sub-packages are the same, it is excellent in terms of bonding reliability and provides an effect of facilitating assembly of the package.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (3)

일측에 솔더 볼이 마련된 기판; A substrate provided with solder balls on one side; 상기 기판 타측 상에 적층되고, 중앙에 개구부가 형성된 서브 기판 상에 서로 반대 방향을 향하도록 센터 패드가 마련된 상하부 칩이 적층되며, 상기 하부 칩은 상기 서브 기판의 개구부를 통해 상기 서브 기판과 와이어 본딩되며, 상기 상부 칩은 상기 서브 기판과 와이어 본딩되는 제1 서브 패키지; 및 The upper and lower chips stacked on the other side of the substrate and provided with center pads facing each other on the sub substrate having an opening formed in the center thereof are stacked, and the lower chip is wire-bonded with the sub substrate through the opening of the sub substrate. The upper chip may include a first sub package wire-bonded with the sub substrate; And 상기 제1 서브 패키지와 동일한 구조로, 상기 제1 서브 패키지 타측 상에 적층되는 제2 서브 패키지를 포함한 것을 특징으로 하는 적층형 패키지.Stacked package, characterized in that the same structure as the first sub-package, comprising a second sub-package stacked on the other side of the first sub-package. 제1항에 있어서,The method of claim 1, 상기 제1,2 서브 패키지 각각은 상기 서브 기판 각각이 상부에 위치하도록 상기 기판 일측에 적층된 것을 특징으로 하는 적층형 패키지.Each of the first and second sub-packages is stacked on one side of the substrate such that each of the sub-substrates is located thereon. 일측에 솔더 볼이 마련된 기판; A substrate provided with solder balls on one side; 상기 기판 타측에 적층되며, 서브 기판과, 상기 서브 기판 양측 각각에 실장되며, 범프에 의하여 상기 서브 기판과 전기적으로 연결된 칩 및 상기 기판 측에 실장된 칩을 밀봉하는 EMC를 포함한 제1 서브 패키지; 및 A first sub package stacked on the other side of the substrate, the first sub package including a sub substrate, a chip mounted on each side of the sub substrate, the chip electrically connected to the sub substrate by bumps, and an EMC sealing the chip mounted on the substrate side; And 상기 제1 서브 패키지와 동일한 구조로, 상기 제1 서브 패키지 상에 적층되는 제2 서브 패키지를 포함한 것을 특징으로 하는 적층형 패키지.Stacked package, characterized in that the same structure as the first sub-package, comprising a second sub-package stacked on the first sub-package.
KR1020050110709A 2005-11-18 2005-11-18 Stack type package KR100650769B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8053879B2 (en) 2008-09-01 2011-11-08 Hynix Semiconductor Inc. Stacked semiconductor package and method for fabricating the same
US8441116B2 (en) 2007-12-13 2013-05-14 Hynix Semiconductor Inc. Semiconductor package having substrate for high speed semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441116B2 (en) 2007-12-13 2013-05-14 Hynix Semiconductor Inc. Semiconductor package having substrate for high speed semiconductor package
US8053879B2 (en) 2008-09-01 2011-11-08 Hynix Semiconductor Inc. Stacked semiconductor package and method for fabricating the same
US8445322B2 (en) 2008-09-01 2013-05-21 SK Hynix Inc. Method of fabricating semiconductor package

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