JP2000332162A - Resin-sealed semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance occupancy ratio of semiconductor elements, downsize and improve packing density on a circuit board by electrically independently placing a die pad at the center of a terminal laying surface and making the die pad back surface recessed to expose it to the outside. SOLUTION: A resin-sealed semiconductor device 1 comprises a semiconductor element 8 mounted via an electric insulative adhesive layer 7 on the front surface of a die pad 2 with the opposite surface adhered to its terminal laying surface. The die pad 2 is disposed electrically independently of a terminal part 4 at approximately the center of a plane, on which the terminal part 4 is arranged two-dimensionally. The terminal part 4 has an inner terminal 4A on the front surface and an outer terminal 4B on the back surface in one body with both surfaces. The back surface 2b of the pad 2 is formed with a recess formed into the outer terminal 4B surface and hence exposed to the outside, resulting in the back surface 2b of the pad 2 being located farther inside the semiconductor device than the back surface of the resin-sealed semiconductor device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device having a semiconductor element mounted thereon, and more particularly to a resin-encapsulated semiconductor device capable of reducing the size of a package and having excellent mountability.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been typified by LSI ASICs due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter, thinner and smaller electric appliances (current trend).
Higher integration and higher functionality are being increasingly achieved. Due to the demand for miniaturization and thinning described above, the trend of development of sealed semiconductor devices using lead frames
(Quad Flat Package) and SOJ (S
mall OutlineJ-Leaded Pack
age) through a surface mount type package
OP (Thin Small Outline Pac
LOC (Lead O) for the purpose of reducing the size of the package with the main axis of thinning due to the development of Kage) and improving the chip storage efficiency by making the package three-dimensional.
n Chip) structure.

Further, in such a highly integrated and sophisticated semiconductor device, heat generation of a chip due to high-speed processing of signals has become a situation that cannot be ignored. For this reason, a sealed semiconductor device has been developed in which a die pad included in the semiconductor device is exposed from the back surface to enhance heat dissipation.

[0004]

However, even in the above-mentioned conventional package, there is a limit to miniaturization of the package due to the routing of leads on the outer peripheral portion of the semiconductor element. Further, in a small package such as TSOP, there is a limit to the number of pins in terms of lead routing and pin pitch.

When a semiconductor device having a die pad exposed from the rear surface is mounted on a circuit board without using solder balls (LGA: LAND GRID ALLAY), the exposed die pad may come into contact with the circuit board or the like. For this reason, there has been a problem that an advanced control of the mounting height of the semiconductor device is required in the LGA.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high occupancy rate of a semiconductor element, can be reduced in size, and can improve a mounting density on a circuit board.
It is another object of the present invention to provide a resin-encapsulated semiconductor device having good mountability.

[0007]

In order to achieve the above object, a resin-encapsulated semiconductor device according to the present invention comprises a plurality of terminals having an internal terminal on the front side and an external terminal on the back side integrally formed front and back. Parts are arranged two-dimensionally and electrically independent of each other in a substantially plane, and the internal terminals of the terminal parts and the terminals of the semiconductor element are electrically connected by wires. A resin-sealed semiconductor device in which the entire portion is resin-sealed so as to expose the portion to the outside, wherein a die pad is electrically independent at a substantially central portion of a plane on which the plurality of terminal portions are two-dimensionally arranged. The semiconductor element is mounted on the surface of the die pad, and the rear surface of the die pad is exposed to the outside so as to form a recess with respect to the surface of the external terminal.

Further, the resin-encapsulated semiconductor device of the present invention comprises:
The die pad is thinner than the terminal portion, and the surface is substantially flush with the surface of the internal terminal of the terminal portion.

Further, the resin-encapsulated semiconductor device of the present invention is configured such that an external electrode made of solder is provided on the surface of the external terminal exposed to the outside.

According to the present invention, the occupancy of the semiconductor element is improved, and the back surface of the die pad has a concave shape with respect to the surface of the external terminal. Therefore, an LGA (Land Grid Array) that does not use solder balls is used. In mounting a resin-encapsulated semiconductor device on a circuit board, the die pad is prevented from coming into contact with the circuit board and the like, and the die pad has a function of radiating heat inside the semiconductor device from the back surface to the outside.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing one embodiment of the resin-sealed semiconductor device of the present invention, and FIG. 2 is a longitudinal sectional view of the resin-sealed semiconductor device shown in FIG. . Note that, for easy understanding of the configuration of the semiconductor device, a sealing member 10 described later is omitted in FIG. 1 and the sealing member 10 is indicated by a virtual line (two-dot chain line) in FIG.

1 and 2, in a resin-encapsulated semiconductor device 1 of the present invention, a semiconductor element 8 is provided on an upper surface 2a side of a die pad 2 with an electrically insulating adhesive layer 7 opposite to a terminal surface thereof. The surface is fixed and mounted. The terminals 8 a of the mounted semiconductor element 8 are arranged along each side of the semiconductor element 8.

The die pad 2 is arranged at substantially the center of the plane on which the terminal portions 4 are two-dimensionally arranged, independently of the terminal portions 4. The die pad 2 is thinner than the terminal portion 4 and can usually have a thickness of about 30 to 125 μm. The surface 2a of the die pad 2
It is substantially flush with the surface of an internal terminal 4A of the terminal portion 4 described later. In the illustrated example, the suspension leads 5 extend electrically independently from the four corners of the die pad 2 within a plane where the terminal portions 4 are two-dimensionally arranged.

The terminal section 4 has an internal terminal 4A on the front side.
The external terminals 4B are paired on the back side, and the terminal portions 4 are two-dimensionally and electrically independent of each other in a substantially one plane. The thickness of the terminal portion 4 is usually 80 to
It can be in the range of about 250 μm. In the illustrated example, a silver plating layer 6 is provided on the internal terminal 4A of each terminal portion 4, and a connection lead 3 extends toward the outside of the semiconductor device at each terminal portion 4.

The back surface 2b of the die pad 2 is exposed to the outside so as to form a recess with respect to the surface of the external terminal 4B. Therefore, the back surface 2b of the die pad 2
Are located inside the semiconductor device with respect to the back surface of the resin-sealed semiconductor device 1. The degree of the recess on the back surface 2b of the die pad 2 (the step between the back surface 2b of the die pad 2 and the surface of the external terminal 4B) can be set in a range of about 25 to 220 μm.

The material of the die pad 2 and the terminal portion 4 as described above can be 42 alloy (Ni 41% Fe alloy), copper, copper alloy or the like. Also, the die pad 2 and the terminal 4
A palladium plating layer may be interposed in at least a part of the contact portion with the sealing member 10. When the material is copper or a copper alloy, a palladium plating layer may be provided via a nickel plating layer. By providing the palladium plating layer in this manner, the adhesion of the sealing member 10 is greatly improved.

Each terminal 8a of the semiconductor element 8 mounted on the die pad 2 is connected to an internal terminal 4A (silver plating layer 6) of the terminal portion 4 by a bonding wire 9. Then, the back surface 2b of the die pad 2 and the external terminals 4
The die pad 2, the connection leads 3, the terminal portions 4, the suspension leads 5, the semiconductor element 8, and the bonding wires 9 are sealed by a sealing member 10 so that part of B is exposed to the outside. The sealing member 10 can be formed using a known resin material used for a resin-sealed semiconductor device, for example, a biphenyl-based epoxy resin or the like.

In such a resin-sealed semiconductor device 1,
Since the back surface 2b of the die pad 2 is located closer to the inside of the semiconductor device than the back surface of the resin-sealed semiconductor device 1, an LGA (land grid array) that does not use solder balls is used.
In mounting the resin-encapsulated semiconductor device on the circuit board as in y), the die pad 2 is prevented from contacting the circuit board or the like. For this reason, it is not necessary to control the mounting height at a high level, and the mountability is greatly improved.

Further, the resin-sealed semiconductor device 1 of the present invention
Is an external terminal 4 exposed to the outside as shown in FIG.
An external electrode 11 made of solder can be provided on B.
Thereby, BGA (Ball Grid Arra)
It becomes a y) type semiconductor device.

Furthermore, since the resin-sealed semiconductor device of the present invention is an area array type in which terminals are taken from the lower surface of the package, the package size and the area required for mounting on a circuit board are the same, Can be mounted on a substrate. The number of terminals, the terminal arrangement, and the like in the above-described resin-sealed semiconductor device 1 are merely examples, and the resin-sealed semiconductor device of the present invention is not limited thereto.

Next, a method for manufacturing the resin-sealed semiconductor device of the present invention will be described. 4 and 5 are process diagrams showing an example of manufacturing the resin-sealed semiconductor device 1 of the present invention shown in FIGS. 1 and 2. Each step is shown in a longitudinal sectional view corresponding to FIG. 2 described above.

First, a photosensitive resist is applied to the front and back surfaces of the conductive substrate 20, dried, exposed through a desired photomask, and then developed to form resist patterns 31A and 31A.
B is formed (FIG. 4A). As the conductive substrate 20, as described above, 42 alloy (Fe alloy of 41% Ni),
A metal substrate (thickness: 100 to 250 μm) of copper, a copper alloy, or the like can be used. It is preferable to use a conductive substrate 20 that has been subjected to a degreasing process and a cleaning process on both surfaces. Further, as the photosensitive resist, conventionally known ones can be used.

Next, the conductive substrate 20 is etched with a corrosion liquid using the resist patterns 31A and 31B as a corrosion-resistant film (FIG. 4B). The corrosion liquid is used for the conductive substrate 2
For example, when a 42 alloy is used as the conductive substrate 20, it is usually spray-etched from both surfaces of the conductive substrate 20 using an aqueous ferric chloride solution. The amount of etching in this etching step is such that the portion penetrated in the thickness direction at the portion etched from both surfaces of the conductive substrate, and about half of the thickness direction remains at the portion etched only from one surface of the conductive substrate. I do.

Next, the resist patterns 31A, 31B
The terminal portion 24 is integrally connected to the outer frame member 21 by the connection lead 23, and the die pad 22 supported by the suspension lead (not shown) from a predetermined position of the outer frame member 21 is removed. Lead frame 20 'provided
Is obtained (FIG. 4C). This lead frame 20 '
In this case, the die pad 22 is thinner (same thickness as the connection lead 23) than the terminal portion 24. Further, the terminal portion 24 has a pair of internal terminals 24A on the front side and external terminals 24B on the back side in a pair, and the front surface 22a of the die pad 22 has
It is substantially flush with the surface of the internal terminal 24A of the terminal portion 24.

The lead frame 20 'may be provided with a palladium plating layer on at least a part of a region sealed by the sealing member 10 in a sealing step of manufacturing a semiconductor device described later. In this case, it is preferable to perform a surface roughening treatment on the surface of the lead frame and form a palladium plating layer thereon. The above-mentioned roughening treatment includes, but is not limited to, chemical polishing treatment in which the surface of the lead frame is corroded with an etching solution such as an organic acid to form fine irregularities. When the material of the lead frame is copper or a copper alloy, a palladium plating layer may be formed via a nickel plating layer.

Next, a silver plating layer 6 is formed at the position of the internal terminal 24 A of the terminal portion 24,
a, an electrically insulating adhesive layer 7 is formed on the adhesive layer 7;
The semiconductor element 8 is mounted by fixing the back surface side of the circuit forming surface of the semiconductor element 8 through the substrate (FIG. 5A).

Next, the terminal 8a of the mounted semiconductor element 8
And the silver plating layer 6 on the internal terminals 24A of the lead frame 20 'are electrically connected by bonding wires 9,
The back surface 22b of the die pad 22 and a part of the external terminal 24B are exposed to the outside so that the die pad 22, the terminal portion 24, the connection lead 23, the suspension lead (not shown), the semiconductor element 8 and the bonding wire 9 are sealed. Stop member 10
(FIG. 5B). In the sealing step, for example, a convex portion is provided on the mold, and the convex portion is brought into contact with the rear surface of the die pad to prevent the rear surface of the die pad from being sealed by the sealing member 10.

Next, each connection lead 23 and each suspension lead of the lead frame 20 ′ exposed from the sealing member 10 are cut, and the outer frame member 21 is removed.
(FIG. 5C).

[0029]

Next, the present invention will be described in more detail with reference to specific examples.

EXAMPLE First, a copper alloy plate having a thickness of 0.15 mm (EFT manufactured by Furukawa Electric Co., Ltd.) was used as a conductive substrate.
EC64T-1 / 2H), and after performing degreasing and cleaning treatments, an etching-resistant UV-curable resist (PME manufactured by Tokyo Ohka Kogyo Co., Ltd.) is provided on both surfaces of the copper alloy plate.
R) was applied and dried. Next, the resist layers on the front side and the back side were respectively exposed through a predetermined photomask, and then developed to form a resist pattern. Thereafter, spray etching was performed from both sides of the copper alloy plate using an aqueous ferric chloride solution. This etching was performed so that the thickness of the die pad portion became 50 μm. Then
After the washing, the resist pattern was peeled off using an organic alkali solution. Thereby, the outer frame member, the die pad supported by the suspension lead from a predetermined position of the outer frame member,
A lead frame including a plurality of terminals integrally connected to the outer frame member by connection leads was obtained.

Next, a nickel plating layer (thickness: 5 μm) was formed on the entire surface of the lead frame, and a palladium plating layer (thickness: 1 μm) was formed thereon.

Next, the opposite side of the circuit forming surface of the semiconductor element is crimped and mounted on the die pad of the lead frame manufactured as described above using a die bonding agent (Able Bond 84-1 LMI manufactured by Able Stick Co., Ltd.). did. Thereafter, the internal terminal of the lead frame and the terminal of the mounted semiconductor element were connected by a gold wire (FA-30 manufactured by Tanaka Electronics Industry Co., Ltd.).

Next, the back surface of the die pad and the external terminal surface of the terminal portion are exposed to the outside, and the die pad, the terminal portion, the semiconductor element and the gold wire are made of a resin material (MP-7400 manufactured by Nitto Denko Corporation). Sealed. In this sealing step, a convex portion was provided on the mold and the convex portion was brought into contact with the rear surface of the die pad to prevent the resin material from flowing into the rear surface of the die pad.

Next, the outer frame member of the lead frame was removed by pressing to obtain a resin-sealed semiconductor device. This resin-encapsulated semiconductor device has 72 external terminals,
Its external dimensions were 10 mm square and 0.8 mm thick, and it was very small and thin. Also, the back surface of the die pad is approximately 100 times smaller than the back surface of the resin-encapsulated semiconductor device.
It was recessed by μm.

The resin-encapsulated semiconductor device manufactured as described above is mounted on a circuit board without using solder balls (LG
A: Land Grid Array, and a temperature cycle test (temperature change from -45 ° C to + 125 ° C
(Repeated every minute cycle), there was no problem even after 500 cycles.

COMPARATIVE EXAMPLE 1 A resin-encapsulated semiconductor device was manufactured using the same lead frame as in the example, without preventing the resin material from flowing into the back surface of the die pad. The back surface of the die pad of the resin-encapsulated semiconductor device thus manufactured was in a state of being covered with the resin member.

When this resin-encapsulated semiconductor device was mounted on a circuit board without using solder balls as in the embodiment, a package crack occurred during the solder reflow process.

Comparative Example 2 A lead frame similar to that of the example was prepared except that the thickness of the die pad was 150 μm, which was the same as that of the terminal portion, and a resin-sealed semiconductor device was prepared using this lead frame. The back surface of the die pad of the resin-encapsulated semiconductor device manufactured in this manner was exposed to the outside and was flush with the external terminal surface. This resin-encapsulated semiconductor device is mounted on a circuit board without using solder balls as in the embodiment (LGA: Land Gri)
d Array). However, when the application amount of the cream solder on the circuit board side was set to be 150 μm, a solder bridge occurred between the external terminal and the rear surface of the die pad.

[0039]

As described above in detail, according to the present invention, the occupancy of the semiconductor element is increased, the size of the semiconductor element can be reduced, and the mounting density on the circuit board can be improved. Has a concave shape with respect to the surface of the external terminal, so that an LGA (Land Gri)
d Array), when mounting a resin-sealed semiconductor device on a circuit board, the die pad is prevented from coming into contact with the circuit board, etc., and it is not necessary to control the mounting height to a high degree, and the mountability is greatly improved. I do. Further, since the heat in the semiconductor device is effectively released from the back surface of the die pad, the semiconductor device has high reliability even in the case where the number of terminals (pins) is increased due to high integration and high functionality of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a plan view showing one embodiment of a lead frame of the present invention.

FIG. 2 is a longitudinal sectional view taken along line AA of the lead frame shown in FIG.

FIG. 3 is a longitudinal sectional view showing another embodiment of the lead frame of the present invention.

FIG. 4 is a process chart showing an example of the production of the resin-sealed semiconductor device of the present invention.

FIG. 5 is a process chart showing an example of manufacturing the resin-sealed semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Resin sealing type semiconductor device 2 ... Die pad 2b ... Die pad back surface 4 ... Terminal part 4A ... Internal terminal 4B ... External terminal 8 ... Semiconductor element 8a ... Terminal 9 ... Wire 10 ... Sealing member 11 ... External electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H01L 23/12 H01L 23/12 L F term (Reference) 4M109 AA01 BA01 CA21 DA04 DA09 DA10 DB03 FA04 5F061 AA01 BA01 CA21 DA06 DD12 5F067 AA01 AA13 AB04 BB01 BC07 BC12 BD05 BE00 DA16 DF03 EA04

Claims (3)

[Claims] A plurality of terminal portions having an internal terminal on a front surface side and an external terminal on a back surface integrated front and back are two-dimensionally and electrically independent from each other in a substantially one plane. In the resin-encapsulated semiconductor device in which the terminals and the terminals of the semiconductor element are electrically connected by wires, and the entirety of the external terminals of each terminal portion is resin-encapsulated so as to expose a part of the external terminals, A die pad is electrically independently arranged at a substantially central portion of a plane in which the terminal portions are two-dimensionally arranged, the semiconductor element is mounted on a surface of the die pad, and a back surface of the die pad is formed on a surface of the external terminal. A resin-sealed semiconductor device, which is exposed to the outside so as to form a recess. 2. The resin encapsulation according to claim 1, wherein the die pad is thinner than the terminal portion, and has a surface substantially flush with a surface of an internal terminal of the terminal portion. Type semiconductor device. 3. The resin-encapsulated semiconductor device according to claim 1, further comprising an external electrode made of solder on a surface of the external terminal exposed to the outside.