JP3947292B2 - Manufacturing method of resin-encapsulated semiconductor device - Google Patents

Manufacturing method of resin-encapsulated semiconductor device Download PDF

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JP3947292B2
JP3947292B2 JP4466398A JP4466398A JP3947292B2 JP 3947292 B2 JP3947292 B2 JP 3947292B2 JP 4466398 A JP4466398 A JP 4466398A JP 4466398 A JP4466398 A JP 4466398A JP 3947292 B2 JP3947292 B2 JP 3947292B2
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terminal
resin
die pad
semiconductor device
terminals
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JPH11233683A (en
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裕 八木
和義 富樫
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Priority to US09/111,374 priority patent/US6025640A/en
Priority to KR1019980027517A priority patent/KR100300665B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体素子を搭載した樹脂封止型の半導体装置とそれに用いられる回路部材および樹脂封止型半導体装置の製造方法に関する。
【０００２】
【従来の技術】
近年、半導体装置は、高集積化や小型化技術の進歩、電気機器の高性能化と軽薄短小化の傾向（時流）から、ＬＳＩのＡＳＩＣに代表されるように、ますます高集積化、高機能化が進んできている。このように高集積化、高機能化された半導体装置においては、信号の高速処理を行うために、チップの発熱、および、パッケージ内のインダクタンスが無視できない状況になってきている。このため、サーマルビアを配設してチップの熱をパッケージ外に逃がしたり、電源、グランドの接続端子数を多くして実質的なインダクタンスを下げ、パッケージ内のインダクタンスを低減することで対応がなされている。このように、半導体装置の高集積化、高機能化は、外部端子（ピン）の総和の増加を来すとともに、更なる多端子（ピン）化が要請されている。
【０００３】
上記のような多端子（ピン）化の要請に応えるものとして、多端子（ピン）ＩＣ、特にゲートアレイやスタンダードセルに体表されるＡＳＩＣ、あるいは、ＤＳＰ（Ｄｉｇｉｔａｌ Ｓｉｇｎａｌ Ｐｒｏｃｅｓｓｏｒ）等の半導体装置の製造においてリードフレームを用いたものがある。具体的には、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）等の表面実装型パッケージがあり、ＱＦＰでは、３００ピンクラスのものまで実用化されている。
【０００４】
しかし、近年の半導体素子の信号処理の高速化および高性能（機能）化は、更に多くの端子を必要としている。ＱＦＰでは、外部端子ピッチを狭めることにより更なる多端子化に対応できるが、外部端子を狭ピッチ化した場合、外部端子自体の幅も狭める必要があり、外部端子強度の低下を来すことになる。その結果、端子形成（ガルウイング化）の位置精度あるいは平坦精度において問題を生じることになる。また、ＱＦＰでは、外部端子のピッチが０．３〜０．４ｍｍへと更に狭くなるにつれて、実装工程が難しくなり、高度なボード実装技術を実現する必要がある等の障害（問題）を生じている。
【０００５】
また、リードフレームを用いた封止型の半導体装置に対する小型化・薄型化の要請から、その開発のトレンドが、ＱＦＰやＳＯＪ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｊ−Ｌｅａｄｅｄ Ｐａｃｋａｇｅ）のような表面実装型のパッケージを経て、ＴＳＯＰ（Ｔｈｉｎ Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）の開発による薄型化を主軸としたパッケージの小型化へ、さらにはパッケージ内部の３次元化によるチップ収納効率向上を目的としたＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）の構造へと進展してきた。
【０００６】
【発明が解決しようとする課題】
しかし、上記従来のパッケージにおいても半導体素子外周部分のリードの引き回しがあるため、パッケージの小型化に限界が見えてきた。また、ＴＳＯＰ等の小型パッケージにおいては、リードの引き回し、ピンピッチの点で、多ピン化に対しても限界が見えてきた。一方で、リードフレームを用いた樹脂封止型の半導体装置パッケージには、より高集積化、高機能化が求められており、これに伴い更なる多ピン化、薄型化、小型化に加え、パッケージの高放熱特性、パッケージ内のリードインダクタンスの低減が求められている。
【０００７】
本発明は、上記のような事情に鑑みてなされたものであり、半導体素子の占有率が高く小型化が可能で、回路基板への実装密度を向上させることができ、さらに、多ピン化への対応が可能で、かつ、高放熱特性、低インダクタンスを兼ね備えた高速化対応が可能な樹脂封止型半導体装置と、これに用いられる回路部材、および、樹脂封止型半導体装置の製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
このような目的を達成するために、本発明は、表面側に内部端子と裏面側に外部端子を表裏一体的に有する複数の端子部を一平面内に二次元的に互いに電気的に独立して配置し、端子部の内部端子と半導体素子の端子とをワイヤにて電気的に接続し、各端子部の外部端子の一部を外部に露出させるように全体を樹脂封止した樹脂封止型半導体装置の製造方法において、（Ａ）導電性基板をエッチングして、表面側に内部端子を裏面側に外部端子を表裏一体的に有する複数の端子部と、表面に内部端子を裏面に外部端子を一体的に備えた複数のダイパッド小片が相互に離間して配置されたダイパッドと、前記各端子部が相互に独立して接続リードを介して一体的に連結され、かつ、各ダイパッド小片が相互に独立して接続リードを介して一体的に連結された外枠部材と、を備えた回路部材を作成する回路部材作成工程と、（Ｂ）ダイパッドに半導体素子を電気的に絶縁して固着することにより搭載する半導体素子搭載工程と、（Ｃ）半導体素子の端子と回路部材の内部端子とをワイヤで電気的に接続するワイヤボンディング工程と、（Ｄ）各外部端子の一部を外部に露出させるように全体を樹脂封止する樹脂封止工程と、（Ｅ）回路部材の各接続リードを切断し、外枠部材を除去する外枠部材分離除去工程と、を備えるような構成とした。
【００１５】
そして、上記の樹脂封止型半導体装置の製造方法において、外部に露出した外部端子面に半田からなる外部電極を形成する半田外部電極形成工程を有するような構成とした。
【００１６】
このような本発明では、ダイパッドの裏面に一体的に設けられた外部端子が、半導体素子の回路形成面で発生した熱を外部に逃がす放熱経路としての作用、および、グランド用端子の作用をなし、また、ダイパッドが複数のダイパッド小片に分割されている場合、各ダイパッド小片の裏面に一体的に設けられた外部端子が、上記の作用に加えて電源用端子の作用をなし、さらに、外部端子に外部電極を形成することにより、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）タイプの半導体装置が可能となり取扱性、ショート防止性が向上する。
【００１７】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照して説明する。
樹脂封止型半導体装置の第１の発明
図１は樹脂封止型半導体装置の第１の発明の一実施形態を示す斜視図、図２は図１に示される半導体装置のＡ−Ａ線における縦断面図、図３は図１に示される半導体装置の裏面側からの斜視図である。尚、半導体装置の構成を理解しやすくするために、図１および図３では後述する封止部材９を省略し、図２では封止部材９を仮想線（２点鎖線）で示している。また、図２の断面形状は、実際のエッチング特性を考慮した形状となっている。
【００１８】
図１乃至図３において、本発明の樹脂封止型半導体装置１は、表面形状が長方形であるダイパッド２の表面側に電気絶縁性の両面接着テープ７を介して半導体素子６がその端子面と反対の面を固着され搭載されている。搭載される半導体素子６の端子６ａは、半導体素子６の端子面の一対の辺の略中心部線（図１に示される鎖線Ｌ）上に沿って配置されている。また、ダイパッド２の長辺方向に沿ってダイパッドを挟むように、複数の端子部４が略一平面内に二次元的に互いに電気的に独立して配設されている。すなわち、端子部４は、半導体素子６の端子面の上記中心部線（Ｌ）を挟むように対向する上記一対の各辺に沿って配設されている。
【００１９】
ダイパッド２は、表面（半導体素子６の搭載面）に複数の内部端子３Ａを一体的に備え、また、裏面に複数の外部端子３Ｂを一体的に備えている。図示例では、内部端子３Ａ上に銀めっき層５が設けられている。尚、図示例では、ダイパッド２の裏面に一体的に設けられた外部端子３Ｂは２行、２列の計４個であるが、これに限定されるものではない。
【００２０】
端子部４は、表面側に内部端子４Ａを裏面側に外部端子４Ｂを表裏一体的に有している。図示例では、内部端子４Ａ上に銀めっき層５が設けられており、各内部端子４Ａ面は、ダイパッド２の内部端子３Ａ面を含めて、略一平面上に位置している。
【００２１】
また、ダイパッド２に搭載されている半導体素子６の各端子６ａは、ダイパッド２の内部端子３Ａ（銀めっき層５）および端子部４の内部端子４Ａ（銀めっき層５）に、ワイヤ８によって接続されている。
【００２２】
そして、各外部端子４Ｂの一部を外部に露出させるように、ダイパッド２、端子部４、半導体素子６およびワイヤ８が封止部材９により封止されている。封止部材９は、封止型半導体装置に使用されている公知の樹脂材料を用いて形成することができる。図２に示される例では、外部に露出している外部端子４Ｂに、半田からなる外部電極１０が設けられている。これにより、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）タイプの半導体装置となっている。
【００２３】
このような半導体装置１では、半導体素子６で発生した熱は熱伝導率の高いダイパッド２へ伝わり、その後、ダイパッド２の外部端子３Ｂから効率よく除去されるので、半導体装置１は放熱性が極めて良好なものとなる。また、ダイパッド２が複数の外部端子３Ｂを備えるので、グランドの接続端子数を増やすことができ、半導体装置１のリードインダクタンスの低減が可能となる。
【００２４】
尚、上述の樹脂封止型半導体装置１における端子数、端子配列等は例示であり、本発明がこれに限定されないことは勿論である。例えば、半導体素子６の端子６ａを、その四辺に沿って二次元的に配置し、かつ、端子部４を半導体素子６（ダイパッド２）の周囲に沿って二次元的に配置することにより、樹脂封止型半導体装置１の更なる多ピン化が可能となる。
樹脂封止型半導体装置の第２の発明
図４は樹脂封止型半導体装置の第２の発明の一実施形態を示す斜視図、図５は図４に示される半導体装置のＢ−Ｂ線における縦断面図、図６は図４に示される半導体装置の裏面側からの斜視図である。尚、半導体装置の構成を理解しやすくするために、図４および図６では後述する封止部材１９を省略し、図５では封止部材１９を仮想線（２点鎖線）で示している。また、図５の断面形状は、実際のエッチング特性を考慮した形状となっている。
【００２５】
図４乃至図６において、本発明の樹脂封止型半導体装置１１は、表面形状が長方形である複数（図示例では４個）のダイパッド小片１２ａが電気的に独立して配設されたダイパッド１２の表面側に電気絶縁性の両面接着テープ１７を介して半導体素子１６がその端子面と反対の面を固着され搭載されている。搭載される半導体素子１６の端子１６ａは、半導体素子１６の端子面の一対の辺の略中心部線（図４に示される鎖線Ｌ）上に沿って配置されている。また、ダイパッド１２の長辺方向に沿ってダイパッドを挟むように、複数の端子部１４が略一平面内に二次元的に互いに電気的に独立して配設されている。すなわち、端子部１４は、半導体素子１６の端子面の上記中心部線（Ｌ）を挟むように対向する上記一対の各辺に沿って配設されている。
【００２６】
ダイパッド１２を構成する各ダイパッド小片１２ａは、表面（半導体素子１６の搭載面）に内部端子１３Ａを一体的に備え、また、裏面に外部端子１３Ｂを一体的に備えている。図示例では、内部端子１３Ａ上に銀めっき層１５が設けられている。尚、図示例では、ダイパッド１２を構成する各ダイパッド小片１２ａは２行、２列の計４個であるが、これに限定されるものではない。
【００２７】
端子部１４は、表面側に内部端子１４Ａを裏面側に外部端子１４Ｂを表裏一体的に有している。図示例では、内部端子１４Ａ上に銀めっき層１５が設けられており、各内部端子１４Ａ面は、ダイパッド１２の内部端子１３Ａ面を含めて、略一平面上に位置している。
【００２８】
また、ダイパッド１２に搭載されている半導体素子１６の各端子１６ａは、ダイパッド小片１２ａの内部端子１３Ａ（銀めっき層１５）および端子部１４の内部端子１４Ａ（銀めっき層１５）に、ワイヤ１８によって接続されている。
【００２９】
そして、各外部端子１４Ｂの一部を外部に露出させるように、ダイパッド１２、端子部１４、半導体素子１６およびワイヤ１８が封止部材１９により封止されている。封止部材１９は、封止型半導体装置に使用されている公知の樹脂材料を用いて形成することができる。図５に示される例では、外部に露出している外部端子１４Ｂに、半田からなる外部電極２０が設けられている。これにより、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）タイプの半導体装置となっている。
【００３０】
このような半導体装置１１では、半導体素子１６で発生した熱は熱伝導率の高い各ダイパッド小片１２ａへ伝わり、その後、ダイパッド小片１２ａの外部端子１３Ｂから効率よく除去されるので、半導体装置１１は放熱性が極めて良好なものとなる。また、ダイパッド１２が複数の外部端子１３Ｂを備えるので、グランドおよび電源の接続端子数を増やすことができ、半導体装置１１の高速化への対応が可能となる。
【００３１】
尚、上述の樹脂封止型半導体装置１１における端子数、端子配列等は例示であり、本発明がこれに限定されないことは勿論である。例えば、半導体素子１６の端子１６ａを、その四辺に沿って二次元的に配置し、かつ、端子部１４を半導体素子１６（ダイパッド１２）の周囲に沿って二次元的に配置することにより、樹脂封止型半導体装置１１の更なる多ピン化が可能となる。
回路部材の第１の発明
図７は回路部材の第１の発明の一実施形態を示す平面図、図８は図７に示される回路部材の裏面側を示す平面図、図９は図７に示される回路部材のＣ−Ｃ線における縦断面図である。尚、図７および図８中の鎖線で囲まれた領域は、半導体装置の製造に用いられる回路部材の領域を示している。
【００３２】
図７乃至図９において、本発明の回路部材２１は、外枠部材２２と、この外枠部材２２から接続リード２３を介して相互に独立して配設された複数の端子部２４と、外枠部材２２から接続リード２５を介して配設されたダイパッド２６とを備えるものである。
【００３３】
外枠部材２２は、外形形状および内側開口形状が矩形であり、各接続リード２３は外枠部材２２の内側開口の対向する一対の辺から同一平面内に突設されている。また、外枠部材２２の内側開口の対向する他の一対の辺からは、接続リード２５が同一平面内に突設されている。
【００３４】
端子部２４は、接続リード２３の先端に設けられ、表面側に内部端子２４Ａを裏面側に外部端子２４Ｂを表裏一体的に有している。図示例では、内部端子２４Ａ上に銀めっき層２９が設けられており、各内部端子２４Ａ面は同一平面上に位置している。
【００３５】
ダイパッド２６は、外枠部材２２の内側開口の対向する一対の辺から延設された２本の接続リード２５に支持されている。そして、このダイパッド２６は表面側に内部端子２７Ａを裏面側に外部端子２７Ｂを一体的に有している。図示例では、内部端子２７Ａ上に銀めっき層２９が設けられており、各内部端子２７Ａ面は、上記の内部端子２４Ａ面がなす平面と同じ平面上に位置している。
【００３６】
このような回路部材２１の材質は、４２合金（Ｎｉ４２％のＦｅ合金）、銅、銅合金等とすることができる。
【００３７】
また、本発明の回路部材２１は、ダイパッド２６の表面側に電気絶縁性の両面接着テープを設けたものであってもよい。使用する両面接着テープとしては、電気絶縁性のベースフィルムの両面に接着剤層を備えたもの、例えば、ユーピレックス（宇部興産（株）製の電気絶縁性のベースフィルム）の両面にＲＸＦ（（株）巴川製紙所製の接着剤）層を備えたＵＸＩＷ（（株）巴川製紙所製）のような両面接着テープを挙げることができる。
【００３８】
上記のような回路部材２１は、後述する本発明の樹脂封止型半導体装置の製造方法において使用することにより、上述の樹脂封止型半導体装置１を製造することができる。
【００３９】
尚、上述の回路部材２１における端子数、端子配列等は例示であり、本発明がこれに限定されないことは勿論である。
回路部材の第２の発明
図１０は回路部材の第２の発明の一実施形態を示す平面図、図１１は図１０に示される回路部材の裏面側を示す平面図、図１２は図１０に示される回路部材のＤ−Ｄ線における縦断面図である。尚、図１０および図１１中の鎖線で囲まれた領域は、半導体装置の製造に用いられる回路部材の領域を示している。
【００４０】
図１０乃至図１２において、本発明の回路部材３１は、外枠部材３２と、この外枠部材３２から接続リード３３を介して相互に独立して配設された複数の端子部３４と、外枠部材３２から接続リード３５を介して相互に離間して配設された複数のダイパッド小片３６ａからなるダイパッド３６とを備えるものである。
【００４１】
外枠部材３２は、外形形状および内側開口形状が矩形であり、各接続リード３３は外枠部材３２の内側開口の対向する一対の辺から同一平面内に突設されている。また、外枠部材３２の内側開口の対向する他の一対の辺からは、接続リード３５が同一平面内に突設されている。
【００４２】
端子部３４は、接続リード３３の先端に設けられ、表面側に内部端子３４Ａを裏面側に外部端子３４Ｂを表裏一体的に有している。図示例では、内部端子３４Ａ上に銀めっき層３９が設けられており、各内部端子３４Ａ面は同一平面上に位置している。
【００４３】
ダイパッド３６は、外枠部材３２の内側開口の対向する一対の辺から延設された４本の接続リード２５の各々に支持された４個のダイパッド小片３６ａからなっている。そして、各ダイパッド小片３６ａは表面側に内部端子３７Ａを裏面側に外部端子３７Ｂを一体的に有している。図示例では、内部端子３７Ａ上に銀めっき層３９が設けられており、各内部端子３７Ａ面は、上記の内部端子３４Ａ面がなす平面と同じ平面上に位置している。
【００４４】
このような回路部材３１の材質は、４２合金（Ｎｉ４２％のＦｅ合金）、銅、銅合金等とすることができる。
【００４５】
また、本発明の回路部材３１は、ダイパッド３６を構成する各ダイパッド小片３６ａの表面側に電気絶縁性の両面接着テープを設けたものであってもよい。使用する両面接着テープとしては、電気絶縁性のベースフィルムの両面に接着剤層を備えたもの、例えば、ユーピレックス（宇部興産（株）製の電気絶縁性のベースフィルム）の両面にＲＸＦ（（株）巴川製紙所製の接着剤）層を備えたＵＸＩＷ（（株）巴川製紙所製）のような両面接着テープを挙げることができる。
【００４６】
上記のような回路部材３１は、後述する本発明の樹脂封止型半導体装置の製造方法において使用することにより、上述の樹脂封止型半導体装置１１を製造することができる。
【００４７】
尚、上述の回路部材３１における端子数、端子配列等は例示であり、本発明がこれに限定されないことは勿論である。
樹脂封止型半導体装置の製造方法の第１の発明
次に、本発明の樹脂封止型半導体装置の製造方法について説明する。
【００４８】
図１３および図１４は、図１乃至図３に示される樹脂封止型半導体装置１を例とした本発明の樹脂封止型半導体装置の製造方法の一実施形態を示す工程図である。各工程は、上記の図２に対応する樹脂封止型半導体装置の縦断面図で示してある。
【００４９】
まず、導電性基板４１の表裏に感光性レジストを塗布、乾燥して感光性レジスト層４２を形成し（図１３（Ａ））、これを所望のフォトマスクを介して露光した後、現像してレジストパターン４２Ａ，４２Ｂを形成する（図１３（Ｂ））。導電性基板４１としては、上述のように４２合金（Ｎｉ４２％のＦｅ合金）、銅、銅合金等の金属基板（厚み１００〜２５０μｍ）を使用することができ、この導電性基板４１は、両面を脱脂等を行い洗浄処理を施したものを使用することが好ましい。また、感光性レジストとしては、従来公知のものを使用することができる。
【００５０】
次に、レジストパターン４２Ａ，４２Ｂを耐腐蝕膜として導電性基板４１に腐蝕液でエッチングを行う（図１３（Ｃ））。腐蝕液は、通常、塩化第二鉄水溶液を使用し、導電性基板４１の両面からスプレーエッチングにて行う。このエッチング工程におけるエッチング量を加減することにより、薄肉部４１ａの厚さを調整することができる。
【００５１】
次いで、レジストパターン４２Ａ，４２Ｂを剥離して除去することにより、端子部２４とダイパッド２６がそれぞれ接続リード２３と接続リード２５（図示せず）により外枠部材２２に一体的に連結された本発明の回路部材２１が得られる（図１３（Ｄ））。この回路部材２１では、図から明らかなように、端子部２４の内部端子２４Ａ面とダイパッド２６の内部端子２７Ａ面とは、同一平面内にある。
【００５２】
次に、上述のように製造した本発明の回路部材２１の端子部２４の内部端子２４Ａの位置、および、ダイパッド２６の内部端子２７Ａの位置に、銀めっき層２９（５）を形成し、さらに、ダイパッド２６の表面側に電気絶縁性の両面接着テープ７を貼付する（図１４（Ａ））。
【００５３】
次いで、ダイパッド２６の表面側に、半導体素子６の回路形成面と反対側を電気絶縁性の両面接着テープ７を介して固着することにより、半導体素子６を搭載する。そして、搭載した半導体素子６の端子６ａと、回路部材２１の端子部２４の内部端子２４Ａの銀めっき層２９（５）、および、ダイパッド２６の内部端子２７Ａの銀めっき層２９（５）とを、ワイヤ８で電気的に接続する（図１４（Ｂ））。
【００５４】
次いで、外部端子２４Ｂおよび外部端子２７Ｂの一部を外部に露出させるようにして、端子部２４、ダイパッド２６、半導体素子６およびワイヤ８を封止部材９で封止する（図１４（Ｃ））。
【００５５】
次に、回路部材２１の各接続リードを切断し外枠部材２２を除去して、本発明の半導体装置１とする（図１４（Ｄ））。また、外部に露出している外部端子４Ｂおよび外部端子３Ｂに半田からなる外部電極１０を形成することができる。
樹脂封止型半導体装置の製造方法の第２の発明
図１５および図１６は、図４乃至図６に示される樹脂封止型半導体装置１１を例とした本発明の樹脂封止型半導体装置の製造方法の一実施形態を示す工程図である。各工程は、上記の図５に対応する樹脂封止型半導体装置の縦断面図で示してある。
【００５６】
まず、導電性基板５１の表裏に感光性レジストを塗布、乾燥して感光性レジスト層５２を形成し（図１５（Ａ））、これを所望のフォトマスクを介して露光した後、現像してレジストパターン５２Ａ，５２Ｂを形成する（図１５（Ｂ））。導電性基板５１としては、上述のように４２合金（Ｎｉ４２％のＦｅ合金）、銅、銅合金等の金属基板（厚み１００〜２５０μｍ）を使用することができ、この導電性基板５１は、両面を脱脂等を行い洗浄処理を施したものを使用することが好ましい。また、感光性レジストとしては、従来公知のものを使用することができる。
【００５７】
次に、レジストパターン５２Ａ，５２Ｂを耐腐蝕膜として導電性基板５１に腐蝕液でエッチングを行う（図１５（Ｃ））。腐蝕液は、通常、塩化第二鉄水溶液を使用し、導電性基板５１の両面からスプレーエッチングにて行う。このエッチング工程におけるエッチング量を加減することにより、薄肉部５１ａの厚さを調整することができる。
【００５８】
次いで、レジストパターン５２Ａ，５２Ｂを剥離して除去することにより、端子部３４とダイパッド３６がそれぞれ接続リード３３と接続リード３５（図示せず）により外枠部材３２に一体的に連結された本発明の回路部材３１が得られる（図１５（Ｄ））。この回路部材３１では、ダイパッド３６は、外枠部材３２から接続リード３５を介して相互に離間して配設された複数のダイパッド小片３６ａからなる。そして、端子部３４の内部端子３４Ａ面と各ダイパッド小片３６ａの内部端子３７Ａ面とは、同一平面内にある。
【００５９】
次に、上述のように製造した本発明の回路部材３１の端子部３４の内部端子３４Ａの位置、および、ダイパッド３６を構成するダイパッド３６ａの内部端子３７Ａの位置に、銀めっき層３９（１５）を形成し、さらに、各ダイパッド小片３６ａの表面側に電気絶縁性の両面接着テープ１７を貼付する（図１６（Ａ））。
【００６０】
次いで、ダイパッド３６の表面側に、半導体素子１６の回路形成面と反対側を電気絶縁性の両面接着テープ１７を介して固着することにより、半導体素子１６を搭載する。そして、搭載した半導体素子１６の端子１６ａと、回路部材３１の端子部３４の内部端子３４Ａの銀めっき層３９（１５）、および、ダイパッド３６の内部端子３７Ａの銀めっき層３９（１５）とを、ワイヤ１８で電気的に接続する（図１６（Ｂ））。
【００６１】
次いで、外部端子３４Ｂおよび外部端子３７Ｂの一部を外部に露出させるようにして、端子部３４、ダイパッド３６、半導体素子１６およびワイヤ１８を封止部材１９で封止する（図１６（Ｃ））。
【００６２】
次に、回路部材３１の各接続リードを切断し外枠部材３２を除去して、本発明の半導体装置３１とする（図１６（Ｄ））。また、外部に露出している外部端子１４Ｂおよび１３Ｂに半田からなる外部電極２０を形成することができる。
【００６３】
【実施例】
次に、具体的な実施例を挙げて本発明を更に詳細に説明する。
（回路部材の作製）
導電性基板として厚み０．１５ｍｍの銅板（古河電気工業（株）製ＥＦＴＥＣ６４Ｔ−１／２Ｈ）を準備し、脱脂処理、洗浄処理を行った後、この銅板の両面に紫外線硬化型レジスト（東京応化工業（株）製ＯＦＰＲ１３０５）を掛け流し法により塗布して乾燥した。次いで、表面側および裏面側のレジスト層をそれぞれ所定のフォトマスクを介して露光した後、現像してレジストパターンを形成した。その後、銅板の両面から塩化第二鉄水溶液を使用してスプレーエッチングを行い、洗浄後、有機アルカリ溶液を用いてレジストパターンを剥離除去した。これにより、ダイパッドの裏面に４個の外部端子が一体的に設けられた回路部材が得られた。
【００６４】
次に、ダイパッドの内部端子面および端子部の内部端子面とに、銀めっき層（厚み約５μｍ）を形成した後、このダイパッドの表面側の所定部位に電気絶縁性の両面接着テープ（巴川製紙所（株）製ＵＨ１Ｗ）を貼り付けた。
（半導体装置の作製）
上記の回路部材のダイパッド表面側の両面接着テープに半導体素子（厚み約０．２５ｍｍ）の回路形成面の反対側を圧着して加熱（１４０℃）することにより固着して半導体素子を搭載した。次いで、回路部材のダイパッドの内部端子上の銀めっき層、および、端子部の内部端子上の銀めっき層と、搭載した半導体素子の端子とを金線により結線した。その後、外部端子の一部を外部に露出させるようにして、端子部、ダイパッド、半導体素子および金線を樹脂材料（日東電工（株）製ＭＰ−７４００）で封止した。
【００６５】
次に、回路部材の各接続リードを切断して外枠部材を除去し、外部に露出している外部端子に半田からなるボールを接着して外部電極を形成した。
【００６６】
このようにして作製した樹脂封止型半導体装置は外部端子数が４８ピン（内、ダイパッド裏面の外部端子数は４ピン）であり、その外形寸法は６ｍｍ四方と小型であり、かつ、厚みが０．８ｍｍであり非常に薄いものであった。また、この樹脂封止型半導体装置のリードインダクタンスは５〜７ｎＨであった。
【００６７】
比較として、ダイパッドの裏面に外部端子を備えていない回路部材を、上記の回路部材と同様にして作製し、この回路部材を用いて外部端子数が４４ピンの樹脂封止型半導体装置を作製した。この樹脂封止型半導体装置のリードインダクタンスを測定した結果、７〜９ｎＨであり、上記の本発明の樹脂封止型半導体装置に比べ大きなものであった。
【００６８】
【発明の効果】
以上詳述したように、本発明によれば半導体素子の占有率が高くなり小型化が可能となって回路基板への実装密度を向上させることができ、また、ダイパッドの裏面に一体的に設けられた外部端子が放熱経路として作用するので半導体装置の放熱性が極めて良好なものとなり、かつ、上記の外部端子によりグランドの接続端子数を増やせるのでパッケージ内のリードインダクタンスの低減が可能となり、さらに、ダイパッドが複数のダイパッド小片に分割されている場合、各ダイパッド小片の裏面に一体的に設けられた外部端子により電源の接続端子数も増やせるので高速化への対応が可能となる。また、外部端子に半田電極を形成することにより、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）タイプの半導体装置が可能となり、実装作業性、ショート防止性が向上するとともにさらに、多ピン化への対応が可能となり、本発明の回路部材を使用することにより、上記のような効果を奏する樹脂封止型半導体装置を容易に作製することができ、このような樹脂封止型半導体装置は、本発明の製造方法により簡便に製造することができる。
【図面の簡単な説明】
【図１】樹脂封止型半導体装置の第１の発明の一実施形態を示す斜視図である。
【図２】図１に示される樹脂封止型半導体装置のＡ−Ａ線における縦断面図である。
【図３】図１に示される樹脂封止型半導体装置の裏面側からの斜視図である。
【図４】樹脂封止型半導体装置の第２の発明の一実施形態を示す斜視図である。
【図５】図４に示される樹脂封止型半導体装置のＢ−Ｂ線における縦断面図である。
【図６】図４に示される樹脂封止型半導体装置の裏面側からの斜視図である。
【図７】回路部材の第１の発明の一実施形態を示す平面図である。
【図８】図７に示される回路部材の裏面側を示す平面図である。
【図９】図７に示される回路部材のＣ−Ｃ線における縦断面図である。
【図１０】回路部材の第２の発明の一実施形態を示す平面図である。
【図１１】図１０に示される回路部材の裏面側を示す平面図である。
【図１２】図１０に示される回路部材のＤ−Ｄ線における縦断面図である。
【図１３】樹脂封止型半導体装置の製造方法の第１の発明の一実施形態を示す工程図である。
【図１４】樹脂封止型半導体装置の製造方法の第１の発明の一実施形態を示す工程図である。
【図１５】樹脂封止型半導体装置の製造方法の第２の発明の一実施形態を示す工程図である。
【図１６】樹脂封止型半導体装置の製造方法の第２の発明の一実施形態を示す工程図である。
【符号の説明】
１，１１…樹脂封止型半導体装置
２，１２…ダイパッド
１２ａ…ダイパッド小片
３Ａ，１３Ａ…内部端子
３Ｂ，１３Ｂ…外部端子
４，１４…端子部
４Ａ，１４Ａ…内部端子
４Ｂ，１４Ｂ…外部端子
６，１６…半導体素子
６ａ，１６ａ…端子
８，１８…ワイヤ
９，１９…封止部材
１０，２０…外部電極
２１，３１…回路部材
２２，３２…外枠部材
２３，２５，３３，３５…接続リード
２４，３４…端子部
２４Ａ，３４Ａ…内部端子
２４Ｂ，３４Ｂ…外部端子
２６，３６…ダイパッド
３６ａ…ダイパッド小片
２７Ａ，３７Ａ…内部端子
２７Ｂ，３７Ｂ…外部端子
４１，５１…導電性基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a resin-encapsulated semiconductor device on which a semiconductor element is mounted, a circuit member used therefor, and a method for manufacturing the resin-encapsulated semiconductor device.
[0002]
[Prior art]
In recent years, semiconductor devices are becoming increasingly integrated and highly integrated, as represented by LSI ASICs, due to the progress of high integration and miniaturization technologies, and the trend of high-performance and light and thin electronic devices (current). Functionalization is progressing. In such highly integrated and highly functional semiconductor devices, the heat generation of the chip and the inductance in the package cannot be ignored in order to perform high-speed signal processing. For this reason, thermal vias are arranged to release the heat of the chip outside the package, or the number of connection terminals of the power supply and ground is increased to reduce the substantial inductance, thereby reducing the inductance in the package. ing. As described above, higher integration and higher functionality of a semiconductor device increase the total number of external terminals (pins), and further demand for more terminals (pins).
[0003]
In order to meet the demand for multi-terminals (pins) as described above, multi-terminal (pin) ICs, particularly ASICs represented in gate arrays and standard cells, or DSPs (Digital Signal Processors) and other semiconductor devices Some manufactures use lead frames. Specifically, there is a surface mount type package such as QFP (Quad Flat Package), and the QFP has been put into practical use up to the 300 pin class.
[0004]
However, the recent increase in signal processing speed and performance (function) of semiconductor elements requires more terminals. QFP can cope with further multi-terminal by narrowing the external terminal pitch, but when the external terminal is narrowed, it is necessary to narrow the width of the external terminal itself, resulting in a decrease in strength of the external terminal. Become. As a result, a problem arises in the positional accuracy or flatness accuracy of terminal formation (gullwing). Also, in QFP, as the pitch of the external terminals is further reduced to 0.3 to 0.4 mm, the mounting process becomes difficult, resulting in problems (problems) such as the need to realize advanced board mounting technology. Yes.
[0005]
Also, due to the demand for miniaturization and thinning of encapsulated semiconductor devices using lead frames, the development trend has passed through surface mount type packages such as QFP and SOJ (Small Outline J-Leaded Package). , TSOP (Thin Small Outline Package) development to reduce the size of the package with the main axis being thin, and further to the LOC (Lead On Chip) structure for the purpose of improving chip storage efficiency by making the inside of the package three-dimensional Has progressed.
[0006]
[Problems to be solved by the invention]
However, even in the above-described conventional package, there is a limit in reducing the size of the package because there is a lead around the outer periphery of the semiconductor element. In addition, in a small package such as TSOP, there is a limit to increase the number of pins in terms of lead routing and pin pitch. On the other hand, resin-encapsulated semiconductor device packages that use lead frames are required to have higher integration and higher functionality, and in addition to this, in addition to further increasing the number of pins, making them thinner, and making them smaller, There is a demand for high heat dissipation characteristics of the package and reduction of lead inductance in the package.
[0007]
The present invention has been made in view of the circumstances as described above, has a high occupation ratio of semiconductor elements, can be miniaturized, can improve the mounting density on a circuit board, and further increase the number of pins. A resin-encapsulated semiconductor device capable of high-speed operation with high heat dissipation characteristics and low inductance, a circuit member used therefor, and a method for manufacturing the resin-encapsulated semiconductor device The purpose is to provide.
[0008]
[Means for Solving the Problems]
  In order to achieve such an object, the present invention includes a plurality of terminal portions integrally having an inner terminal on the front surface side and an outer terminal on the back surface side.In one planeAre arranged two-dimensionally and electrically independent from each other, electrically connect the internal terminals of the terminal portion and the terminals of the semiconductor element with wires, and expose a part of the external terminals of each terminal portion to the outside. In the method of manufacturing a resin-encapsulated semiconductor device in which the whole is resin-sealed, (A) a plurality of terminals having an internal terminal on the front surface side and an external terminal on the back surface side integrated with the front and back surfaces by etching the conductive substrate A plurality of die pads each having a plurality of die pad pieces integrally provided with an internal terminal on the front surface and an external terminal on the back surface, and the terminal portions independently from each other via connection leads A circuit member creating step for creating a circuit member comprising: an outer frame member that is integrally connected to each other, and each die pad piece is integrally connected to each other independently via a connection lead; and (B) a die pad The semiconductor element is electrically insulated and fixed. A semiconductor element mounting step to be mounted, (C) a wire bonding step of electrically connecting the terminal of the semiconductor element and the internal terminal of the circuit member with a wire, and (D) a part of each external terminal to the outside A resin sealing process for resin-sealing the whole so as to be exposed, and (E) an outer frame member separation / removal process for cutting each connection lead of the circuit member and removing the outer frame member. .
[0015]
In the method for manufacturing the resin-encapsulated semiconductor device described above, a solder external electrode forming step of forming an external electrode made of solder on the external terminal surface exposed to the outside is adopted.
[0016]
In the present invention, the external terminal integrally provided on the back surface of the die pad functions as a heat dissipation path for releasing the heat generated on the circuit formation surface of the semiconductor element to the outside, and also functions as a ground terminal. In addition, when the die pad is divided into a plurality of die pad pieces, the external terminals integrally provided on the back surface of each die pad piece serve as a power supply terminal in addition to the above-described actions. By forming an external electrode on the BGA, a BGA (Ball Grid Array) type semiconductor device becomes possible, and handling and short-circuit prevention are improved.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First invention of resin-encapsulated semiconductor device
1 is a perspective view showing an embodiment of a first invention of a resin-encapsulated semiconductor device, FIG. 2 is a longitudinal sectional view taken along line AA of the semiconductor device shown in FIG. 1, and FIG. 3 is shown in FIG. It is a perspective view from the back side of a semiconductor device. In order to facilitate understanding of the configuration of the semiconductor device, a sealing member 9 described later is omitted in FIGS. 1 and 3, and the sealing member 9 is indicated by a virtual line (two-dot chain line) in FIG. In addition, the cross-sectional shape of FIG. 2 is a shape that considers actual etching characteristics.
[0018]
1 to 3, a resin-encapsulated semiconductor device 1 according to the present invention has a semiconductor element 6 connected to its terminal surface via an electrically insulating double-sided adhesive tape 7 on the surface side of a die pad 2 having a rectangular surface shape. The opposite side is fixed and mounted. The terminal 6 a of the semiconductor element 6 to be mounted is arranged along a substantially central line (a chain line L shown in FIG. 1) of a pair of sides of the terminal surface of the semiconductor element 6. In addition, a plurality of terminal portions 4 are two-dimensionally and electrically independent from each other so as to sandwich the die pad along the long side direction of the die pad 2. That is, the terminal portion 4 is disposed along the pair of sides facing each other so as to sandwich the center line (L) of the terminal surface of the semiconductor element 6.
[0019]
The die pad 2 is integrally provided with a plurality of internal terminals 3A on the front surface (mounting surface of the semiconductor element 6), and is integrally provided with a plurality of external terminals 3B on the back surface. In the illustrated example, the silver plating layer 5 is provided on the internal terminal 3A. In the illustrated example, the number of external terminals 3B integrally provided on the back surface of the die pad 2 is four in two rows and two columns, but is not limited thereto.
[0020]
The terminal portion 4 has an internal terminal 4A on the front surface side and an external terminal 4B on the back surface side. In the illustrated example, the silver plating layer 5 is provided on the internal terminal 4 </ b> A, and the surface of each internal terminal 4 </ b> A is located on a substantially flat surface including the internal terminal 3 </ b> A surface of the die pad 2.
[0021]
Further, each terminal 6a of the semiconductor element 6 mounted on the die pad 2 is connected to the internal terminal 3A (silver plating layer 5) of the die pad 2 and the internal terminal 4A (silver plating layer 5) of the terminal portion 4 by wires 8. Has been.
[0022]
The die pad 2, the terminal portion 4, the semiconductor element 6, and the wire 8 are sealed with a sealing member 9 so that a part of each external terminal 4 </ b> B is exposed to the outside. The sealing member 9 can be formed using a known resin material used in a sealed semiconductor device. In the example shown in FIG. 2, an external electrode 10 made of solder is provided on the external terminal 4B exposed to the outside. As a result, the semiconductor device is a BGA (Ball Grid Array) type.
[0023]
In such a semiconductor device 1, the heat generated in the semiconductor element 6 is transmitted to the die pad 2 having a high thermal conductivity, and is then efficiently removed from the external terminal 3 </ b> B of the die pad 2. It will be good. Moreover, since the die pad 2 includes the plurality of external terminals 3B, the number of ground connection terminals can be increased, and the lead inductance of the semiconductor device 1 can be reduced.
[0024]
It should be noted that the number of terminals, the terminal arrangement, and the like in the above-described resin-encapsulated semiconductor device 1 are examples, and the present invention is of course not limited thereto. For example, the terminals 6a of the semiconductor element 6 are two-dimensionally arranged along the four sides, and the terminal portions 4 are two-dimensionally arranged around the semiconductor element 6 (die pad 2), whereby resin The number of pins of the sealed semiconductor device 1 can be further increased.
Second invention of resin-encapsulated semiconductor device
4 is a perspective view showing an embodiment of the second invention of the resin-encapsulated semiconductor device, FIG. 5 is a longitudinal sectional view taken along line BB of the semiconductor device shown in FIG. 4, and FIG. 6 is shown in FIG. It is a perspective view from the back side of a semiconductor device. In order to facilitate understanding of the configuration of the semiconductor device, a sealing member 19 to be described later is omitted in FIGS. 4 and 6, and the sealing member 19 is indicated by a virtual line (two-dot chain line) in FIG. Further, the cross-sectional shape of FIG. 5 is a shape that takes into account the actual etching characteristics.
[0025]
4 to 6, the resin-encapsulated semiconductor device 11 of the present invention has a die pad 12 in which a plurality of (four in the illustrated example) die pad pieces 12a having a rectangular surface shape are electrically arranged independently. A semiconductor element 16 is mounted on the surface side of the semiconductor element 16 with an opposite surface to the terminal surface thereof, with an electrically insulating double-sided adhesive tape 17 interposed therebetween. The terminal 16 a of the semiconductor element 16 to be mounted is arranged along a substantially central line (a chain line L shown in FIG. 4) of a pair of sides of the terminal surface of the semiconductor element 16. In addition, a plurality of terminal portions 14 are two-dimensionally and electrically independent of each other so as to sandwich the die pad along the long side direction of the die pad 12. That is, the terminal portion 14 is disposed along the pair of sides facing each other so as to sandwich the center line (L) of the terminal surface of the semiconductor element 16.
[0026]
Each die pad piece 12a constituting the die pad 12 is integrally provided with an internal terminal 13A on the front surface (mounting surface of the semiconductor element 16) and an external terminal 13B is integrally provided on the back surface. In the illustrated example, a silver plating layer 15 is provided on the internal terminal 13A. In the illustrated example, each die pad piece 12a constituting the die pad 12 has a total of four in two rows and two columns, but is not limited thereto.
[0027]
The terminal portion 14 has an internal terminal 14A on the front surface side and an external terminal 14B on the back surface side. In the illustrated example, the silver plating layer 15 is provided on the internal terminal 14 </ b> A, and the surface of each internal terminal 14 </ b> A is positioned on a substantially single plane including the internal terminal 13 </ b> A surface of the die pad 12.
[0028]
Further, each terminal 16a of the semiconductor element 16 mounted on the die pad 12 is connected to the internal terminal 13A (silver plating layer 15) of the die pad piece 12a and the internal terminal 14A (silver plating layer 15) of the terminal portion 14 by wires 18. It is connected.
[0029]
And the die pad 12, the terminal part 14, the semiconductor element 16, and the wire 18 are sealed with the sealing member 19 so that a part of each external terminal 14B may be exposed outside. The sealing member 19 can be formed using a known resin material used in a sealed semiconductor device. In the example shown in FIG. 5, an external electrode 20 made of solder is provided on the external terminal 14B exposed to the outside. As a result, the semiconductor device is a BGA (Ball Grid Array) type.
[0030]
In such a semiconductor device 11, the heat generated in the semiconductor element 16 is transferred to each die pad piece 12a having a high thermal conductivity, and then efficiently removed from the external terminal 13B of the die pad piece 12a. The property is extremely good. In addition, since the die pad 12 includes the plurality of external terminals 13B, the number of ground and power connection terminals can be increased, and the semiconductor device 11 can be increased in speed.
[0031]
It should be noted that the number of terminals, the terminal arrangement, and the like in the above-described resin-encapsulated semiconductor device 11 are examples, and the present invention is of course not limited thereto. For example, the terminals 16a of the semiconductor element 16 are two-dimensionally arranged along the four sides thereof, and the terminal portions 14 are two-dimensionally arranged around the semiconductor element 16 (die pad 12), whereby resin The number of pins of the sealed semiconductor device 11 can be further increased.
1st invention of a circuit member
7 is a plan view showing an embodiment of the first invention of the circuit member, FIG. 8 is a plan view showing the back side of the circuit member shown in FIG. 7, and FIG. 9 is a C- of the circuit member shown in FIG. It is a longitudinal cross-sectional view in the C line. 7 and 8, the region surrounded by the chain line indicates the region of the circuit member used for manufacturing the semiconductor device.
[0032]
7 to 9, the circuit member 21 of the present invention includes an outer frame member 22, a plurality of terminal portions 24 arranged independently from each other through the connection leads 23 from the outer frame member 22, and an outer frame member 22. A die pad 26 disposed from the frame member 22 via the connection lead 25 is provided.
[0033]
The outer frame member 22 has a rectangular outer shape and inner opening shape, and each connection lead 23 projects from the pair of opposing sides of the inner opening of the outer frame member 22 in the same plane. In addition, connection leads 25 project from the other pair of opposing sides of the inner opening of the outer frame member 22 in the same plane.
[0034]
The terminal portion 24 is provided at the tip of the connection lead 23, and has an internal terminal 24A on the front surface side and an external terminal 24B on the back surface in an integrated manner. In the example of illustration, the silver plating layer 29 is provided on the internal terminal 24A, and the surface of each internal terminal 24A is located on the same plane.
[0035]
The die pad 26 is supported by two connection leads 25 extending from a pair of opposite sides of the inner opening of the outer frame member 22. The die pad 26 has an internal terminal 27A on the front side and an external terminal 27B on the back side. In the illustrated example, the silver plating layer 29 is provided on the internal terminal 27A, and the surface of each internal terminal 27A is located on the same plane as the plane formed by the surface of the internal terminal 24A.
[0036]
The material of the circuit member 21 can be 42 alloy (Ni 42% Fe alloy), copper, copper alloy, or the like.
[0037]
The circuit member 21 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface side of the die pad 26. As the double-sided adhesive tape to be used, a tape having an adhesive layer on both sides of an electrically insulating base film, for example, RXF ((Co., Ltd.), Upilex (an electrically insulating base film manufactured by Ube Industries, Ltd.) is used. A double-sided adhesive tape such as UXIW (manufactured by Yodogawa Paper Co., Ltd.) provided with an adhesive) layer manufactured by Yodogawa Paper Mill.
[0038]
By using the circuit member 21 as described above in a method for manufacturing a resin-encapsulated semiconductor device of the present invention described later, the above-described resin-encapsulated semiconductor device 1 can be manufactured.
[0039]
In addition, the number of terminals, the terminal arrangement, and the like in the circuit member 21 described above are examples, and the present invention is not limited to this.
Second invention of circuit member
FIG. 10 is a plan view showing an embodiment of the second invention of the circuit member, FIG. 11 is a plan view showing the back side of the circuit member shown in FIG. 10, and FIG. 12 is a D- of the circuit member shown in FIG. It is a longitudinal cross-sectional view in the D line. 10 and 11, the region surrounded by the chain line indicates the region of the circuit member used for manufacturing the semiconductor device.
[0040]
10 to 12, a circuit member 31 according to the present invention includes an outer frame member 32, a plurality of terminal portions 34 arranged independently from each other through the connection lead 33 from the outer frame member 32, and an outer frame member 32. The die pad 36 includes a plurality of die pad pieces 36 a that are spaced apart from the frame member 32 via connection leads 35.
[0041]
The outer frame member 32 has a rectangular outer shape and inner opening shape, and each connection lead 33 projects from a pair of opposing sides of the inner opening of the outer frame member 32 in the same plane. In addition, connection leads 35 project from the other pair of opposite sides of the inner opening of the outer frame member 32 in the same plane.
[0042]
The terminal portion 34 is provided at the tip of the connection lead 33, and has an internal terminal 34A on the front surface side and an external terminal 34B on the back surface side. In the illustrated example, a silver plating layer 39 is provided on the internal terminal 34A, and the surfaces of the internal terminals 34A are located on the same plane.
[0043]
The die pad 36 includes four die pad pieces 36 a supported by each of the four connection leads 25 extending from a pair of opposing sides of the inner opening of the outer frame member 32. Each die pad piece 36a integrally has an internal terminal 37A on the front surface side and an external terminal 37B on the back surface side. In the illustrated example, a silver plating layer 39 is provided on the internal terminal 37A, and the surface of each internal terminal 37A is located on the same plane as the plane formed by the surface of the internal terminal 34A.
[0044]
The material of the circuit member 31 can be 42 alloy (Ni 42% Fe alloy), copper, copper alloy, or the like.
[0045]
Further, the circuit member 31 of the present invention may be one in which an electrically insulating double-sided adhesive tape is provided on the surface side of each die pad piece 36 a constituting the die pad 36. As the double-sided adhesive tape to be used, a tape having an adhesive layer on both sides of an electrically insulating base film, for example, RXF ((Co., Ltd.), Upilex (an electrically insulating base film manufactured by Ube Industries, Ltd.) is used. A double-sided adhesive tape such as UXIW (manufactured by Yodogawa Paper Co., Ltd.) provided with an adhesive) layer manufactured by Yodogawa Paper Mill.
[0046]
By using the circuit member 31 as described above in a method for manufacturing a resin-encapsulated semiconductor device of the present invention described later, the above-described resin-encapsulated semiconductor device 11 can be manufactured.
[0047]
In addition, the number of terminals, the terminal arrangement, and the like in the circuit member 31 described above are examples, and the present invention is not limited to this.
First invention of manufacturing method of resin-encapsulated semiconductor device
Next, a method for manufacturing the resin-encapsulated semiconductor device of the present invention will be described.
[0048]
13 and 14 are process diagrams showing an embodiment of a method for manufacturing a resin-encapsulated semiconductor device of the present invention, taking the resin-encapsulated semiconductor device 1 shown in FIGS. 1 to 3 as an example. Each step is shown in a longitudinal sectional view of the resin-encapsulated semiconductor device corresponding to FIG.
[0049]
First, a photosensitive resist is applied to the front and back of the conductive substrate 41 and dried to form a photosensitive resist layer 42 (FIG. 13A), which is exposed through a desired photomask and then developed. Resist patterns 42A and 42B are formed (FIG. 13B). As the conductive substrate 41, a metal substrate (thickness: 100 to 250 μm) such as 42 alloy (Ni 42% Fe alloy), copper, or copper alloy can be used as described above. It is preferable to use a product that has been degreased and washed. As the photosensitive resist, conventionally known resists can be used.
[0050]
Next, the resist pattern 42A, 42B is used as an anti-corrosion film, and the conductive substrate 41 is etched with an etching solution (FIG. 13C). As the corrosive liquid, a ferric chloride aqueous solution is usually used and spray etching is performed from both surfaces of the conductive substrate 41. By adjusting the etching amount in this etching step, the thickness of the thin portion 41a can be adjusted.
[0051]
Next, the resist patterns 42A and 42B are peeled and removed, whereby the terminal portion 24 and the die pad 26 are integrally connected to the outer frame member 22 by the connection lead 23 and the connection lead 25 (not shown), respectively. Circuit member 21 is obtained (FIG. 13D). In this circuit member 21, as is clear from the figure, the surface of the internal terminal 24A of the terminal portion 24 and the surface of the internal terminal 27A of the die pad 26 are in the same plane.
[0052]
Next, a silver plating layer 29 (5) is formed at the position of the internal terminal 24A of the terminal portion 24 of the circuit member 21 of the present invention manufactured as described above and the position of the internal terminal 27A of the die pad 26, and Then, the electrically insulating double-sided adhesive tape 7 is affixed to the surface side of the die pad 26 (FIG. 14A).
[0053]
Next, the semiconductor element 6 is mounted on the surface side of the die pad 26 by fixing the opposite side of the circuit formation surface of the semiconductor element 6 with an electrically insulating double-sided adhesive tape 7. And the terminal 6a of the mounted semiconductor element 6, the silver plating layer 29 (5) of the internal terminal 24A of the terminal portion 24 of the circuit member 21, and the silver plating layer 29 (5) of the internal terminal 27A of the die pad 26 are provided. The wires 8 are electrically connected (FIG. 14B).
[0054]
Next, the terminal portion 24, the die pad 26, the semiconductor element 6 and the wire 8 are sealed with the sealing member 9 so that a part of the external terminal 24B and the external terminal 27B are exposed to the outside (FIG. 14C). .
[0055]
Next, each connection lead of the circuit member 21 is cut, and the outer frame member 22 is removed to obtain the semiconductor device 1 of the present invention (FIG. 14D). Further, the external electrode 10 made of solder can be formed on the external terminals 4B and the external terminals 3B exposed to the outside.
Second invention of manufacturing method of resin-encapsulated semiconductor device
15 and 16 are process diagrams showing an embodiment of a method for manufacturing a resin-encapsulated semiconductor device of the present invention, taking the resin-encapsulated semiconductor device 11 shown in FIGS. 4 to 6 as an example. Each step is shown in a longitudinal sectional view of the resin-encapsulated semiconductor device corresponding to FIG.
[0056]
First, a photosensitive resist is applied to the front and back of the conductive substrate 51 and dried to form a photosensitive resist layer 52 (FIG. 15A), which is exposed through a desired photomask and then developed. Resist patterns 52A and 52B are formed (FIG. 15B). As the conductive substrate 51, a metal substrate (thickness: 100 to 250 μm) such as 42 alloy (Ni 42% Fe alloy), copper, or copper alloy can be used as described above. It is preferable to use a product that has been degreased and washed. As the photosensitive resist, conventionally known resists can be used.
[0057]
Next, the resist pattern 52A, 52B is used as an anticorrosion film, and the conductive substrate 51 is etched with an etching solution (FIG. 15C). As the corrosive liquid, a ferric chloride aqueous solution is usually used and spray etching is performed from both surfaces of the conductive substrate 51. By adjusting the etching amount in this etching step, the thickness of the thin portion 51a can be adjusted.
[0058]
Next, the resist patterns 52A and 52B are peeled and removed, whereby the terminal portion 34 and the die pad 36 are integrally connected to the outer frame member 32 by the connection lead 33 and the connection lead 35 (not shown), respectively. Circuit member 31 is obtained (FIG. 15D). In this circuit member 31, the die pad 36 is composed of a plurality of die pad pieces 36 a that are spaced apart from each other via the connection leads 35 from the outer frame member 32. The internal terminal 34A surface of the terminal portion 34 and the internal terminal 37A surface of each die pad piece 36a are in the same plane.
[0059]
Next, the silver plating layer 39 (15) is provided at the position of the internal terminal 34A of the terminal portion 34 of the circuit member 31 of the present invention manufactured as described above and the position of the internal terminal 37A of the die pad 36a constituting the die pad 36. Further, an electrically insulating double-sided adhesive tape 17 is attached to the surface side of each die pad piece 36a (FIG. 16A).
[0060]
Next, the semiconductor element 16 is mounted on the surface side of the die pad 36 by fixing the opposite side of the circuit formation surface of the semiconductor element 16 with an electrically insulating double-sided adhesive tape 17. Then, the terminal 16 a of the mounted semiconductor element 16, the silver plating layer 39 (15) of the internal terminal 34 A of the terminal portion 34 of the circuit member 31, and the silver plating layer 39 (15) of the internal terminal 37 A of the die pad 36. The wires 18 are electrically connected (FIG. 16B).
[0061]
Next, the terminal portion 34, the die pad 36, the semiconductor element 16, and the wire 18 are sealed with the sealing member 19 so that a part of the external terminal 34B and the external terminal 37B are exposed to the outside (FIG. 16C). .
[0062]
Next, each connection lead of the circuit member 31 is cut, and the outer frame member 32 is removed to obtain the semiconductor device 31 of the present invention (FIG. 16D). Further, the external electrode 20 made of solder can be formed on the external terminals 14B and 13B exposed to the outside.
[0063]
【Example】
Next, the present invention will be described in more detail with specific examples.
(Production of circuit members)
A 0.15 mm thick copper plate (EFTEC64T-1 / 2H manufactured by Furukawa Electric Co., Ltd.) was prepared as a conductive substrate, and after degreasing and cleaning, an ultraviolet curable resist (Tokyo Ohka Kogyo) was applied to both sides of the copper plate. Kogyo Co., Ltd. OFPR1305) was applied by a pouring method and dried. Subsequently, after exposing the resist layer of the surface side and the back surface side through a predetermined photomask, it developed and formed the resist pattern. Thereafter, spray etching was performed from both sides of the copper plate using an aqueous ferric chloride solution, and after cleaning, the resist pattern was peeled and removed using an organic alkali solution. As a result, a circuit member in which four external terminals were integrally provided on the back surface of the die pad was obtained.
[0064]
Next, after a silver plating layer (thickness of about 5 μm) is formed on the internal terminal surface of the die pad and the internal terminal surface of the terminal portion, an electrically insulating double-sided adhesive tape (Yodogawa Paper) is applied to a predetermined portion on the surface side of the die pad. UH1W manufactured by Tokoro Co., Ltd.
(Fabrication of semiconductor devices)
The opposite side of the circuit forming surface of the semiconductor element (thickness: about 0.25 mm) was pressed on the double-sided adhesive tape on the die pad surface side of the circuit member and heated (140 ° C.) to fix and mount the semiconductor element. Subsequently, the silver plating layer on the internal terminal of the die pad of the circuit member, the silver plating layer on the internal terminal of the terminal portion, and the terminal of the mounted semiconductor element were connected by a gold wire. Then, the terminal part, the die pad, the semiconductor element, and the gold wire were sealed with a resin material (MP-7400 manufactured by Nitto Denko Corporation) so that a part of the external terminal was exposed to the outside.
[0065]
Next, each connection lead of the circuit member was cut to remove the outer frame member, and a ball made of solder was bonded to the external terminal exposed to the outside to form an external electrode.
[0066]
The resin-encapsulated semiconductor device fabricated in this way has 48 external terminals (including 4 external terminals on the back side of the die pad), its external dimensions are as small as 6 mm square, and the thickness is small. It was 0.8 mm and very thin. Moreover, the lead inductance of this resin-encapsulated semiconductor device was 5 to 7 nH.
[0067]
As a comparison, a circuit member having no external terminals on the back surface of the die pad was produced in the same manner as the above circuit member, and a resin-sealed semiconductor device having 44 pins of external terminals was produced using this circuit member. . As a result of measuring the lead inductance of this resin-encapsulated semiconductor device, it was 7 to 9 nH, which was larger than the resin-encapsulated semiconductor device of the present invention.
[0068]
【The invention's effect】
As described above in detail, according to the present invention, the occupation ratio of the semiconductor element is increased, the size can be reduced, and the mounting density on the circuit board can be improved. Since the external terminals act as heat dissipation paths, the heat dissipation of the semiconductor device is extremely good, and the number of ground connection terminals can be increased by the above external terminals, so that the lead inductance in the package can be reduced. When the die pad is divided into a plurality of die pad pieces, the number of connection terminals of the power supply can be increased by external terminals integrally provided on the back surface of each die pad piece. In addition, by forming solder electrodes on the external terminals, a BGA (Ball Grid Array) type semiconductor device can be realized, and mounting workability and short circuit prevention can be improved. By using the circuit member of the present invention, it is possible to easily produce a resin-encapsulated semiconductor device that exhibits the above-described effects. It can be easily manufactured.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an embodiment of a first invention of a resin-encapsulated semiconductor device.
2 is a longitudinal sectional view taken along line AA of the resin-encapsulated semiconductor device shown in FIG.
3 is a perspective view from the back side of the resin-encapsulated semiconductor device shown in FIG. 1. FIG.
FIG. 4 is a perspective view showing an embodiment of a second invention of a resin-encapsulated semiconductor device.
5 is a longitudinal sectional view taken along line BB of the resin-encapsulated semiconductor device shown in FIG.
6 is a perspective view from the back side of the resin-encapsulated semiconductor device shown in FIG. 4. FIG.
FIG. 7 is a plan view showing an embodiment of the first invention of the circuit member.
8 is a plan view showing a back surface side of the circuit member shown in FIG. 7. FIG.
9 is a longitudinal sectional view taken along line CC of the circuit member shown in FIG.
FIG. 10 is a plan view showing an embodiment of the second invention of the circuit member.
11 is a plan view showing the back side of the circuit member shown in FIG.
12 is a longitudinal sectional view taken along line DD of the circuit member shown in FIG.
FIG. 13 is a process diagram showing one embodiment of the first invention of a method for manufacturing a resin-encapsulated semiconductor device.
FIG. 14 is a process diagram showing one embodiment of the first invention of a method for manufacturing a resin-encapsulated semiconductor device.
FIG. 15 is a process diagram showing an embodiment of a second invention of a method for manufacturing a resin-encapsulated semiconductor device.
FIG. 16 is a process diagram showing one embodiment of a second invention of a method for producing a resin-encapsulated semiconductor device.
[Explanation of symbols]
1,11 ... Resin-sealed semiconductor device
2,12 ... Die pad
12a ... Die pad piece
3A, 13A ... internal terminals
3B, 13B ... External terminal
4,14 ... Terminal part
4A, 14A ... Internal terminals
4B, 14B ... External terminal
6, 16 ... Semiconductor element
6a, 16a ... terminals
8, 18 ... Wire
9, 19 ... Sealing member
10, 20 ... External electrode
21, 31 ... Circuit members
22, 32 ... Outer frame member
23, 25, 33, 35 ... connection leads
24, 34 ... terminal portion
24A, 34A ... internal terminals
24B, 34B ... External terminal
26, 36 ... Die pad
36a ... Die pad piece
27A, 37A ... internal terminals
27B, 37B ... External terminal
41, 51 ... conductive substrate

Claims (2)

表面側に内部端子と裏面側に外部端子を表裏一体的に有する複数の端子部を一平面内に二次元的に互いに電気的に独立して配置し、端子部の内部端子と半導体素子の端子とをワイヤにて電気的に接続し、各端子部の外部端子の一部を外部に露出させるように全体を樹脂封止した樹脂封止型半導体装置の製造方法において、
（Ａ）導電性基板をエッチングして、表面側に内部端子を裏面側に外部端子を表裏一体的に有する複数の端子部と、表面に内部端子を裏面に外部端子を一体的に備えた複数のダイパッド小片が相互に離間して配置されたダイパッドと、前記各端子部が相互に独立して接続リードを介して一体的に連結され、かつ、各ダイパッド小片が相互に独立して接続リードを介して一体的に連結された外枠部材と、を備えた回路部材を作成する回路部材作成工程と、（Ｂ）ダイパッドに半導体素子を電気的に絶縁して固着することにより搭載する半導体素子搭載工程と、（Ｃ）半導体素子の端子と回路部材の内部端子とをワイヤで電気的に接続するワイヤボンディング工程と、（Ｄ）各外部端子の一部を外部に露出させるように全体を樹脂封止する樹脂封止工程と、（Ｅ）回路部材の各接続リードを切断し、外枠部材を除去する外枠部材分離除去工程と、を備えることを特徴とする樹脂封止型半導体装置の製造方法。A plurality of terminal parts having internal terminals on the front side and external terminals on the back side are arranged two-dimensionally and electrically independent from each other in one plane, and the internal terminals of the terminal parts and the terminals of the semiconductor element In a method for manufacturing a resin-encapsulated semiconductor device in which the whole is resin-sealed so that a part of the external terminals of each terminal portion is exposed to the outside,
(A) A plurality of terminal portions that have an internal terminal on the front surface side and an external terminal on the back surface side integrated with the front surface and the back surface, and a plurality of integrated internal terminals on the front surface and external terminals on the back surface. The die pad pieces are spaced apart from each other, and the terminal portions are integrally connected to each other through connection leads, and the die pad pieces are connected to each other independently. A circuit member creating step for creating a circuit member comprising an outer frame member integrally connected to each other, and (B) mounting a semiconductor element by electrically insulating and fixing the semiconductor element to the die pad A process, (C) a wire bonding process in which the terminals of the semiconductor element and the internal terminals of the circuit member are electrically connected by wires, and (D) a resin-sealed whole so that a part of each external terminal is exposed to the outside. Resin seal to stop Process and, (E) cutting the respective connection leads of the circuit members, the production method of the resin-sealed semiconductor device for an outer frame member separating and removing step, further comprising a removing the outer frame member. 外部に露出した外部端子面に半田からなる外部電極を形成する半田外部電極形成工程を有することを特徴とする請求項１に記載の樹脂封止型半導体装置の製造方法。  2. The method of manufacturing a resin-encapsulated semiconductor device according to claim 1, further comprising a solder external electrode forming step of forming an external electrode made of solder on an external terminal surface exposed to the outside.
JP4466398A 1997-07-16 1998-02-10 Manufacturing method of resin-encapsulated semiconductor device Expired - Lifetime JP3947292B2 (en)

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JP4466398A JP3947292B2 (en) 1998-02-10 1998-02-10 Manufacturing method of resin-encapsulated semiconductor device
US09/111,374 US6025640A (en) 1997-07-16 1998-07-07 Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
KR1019980027517A KR100300665B1 (en) 1997-07-16 1998-07-08 Resin-sealed semiconductor device, circuit member used therefor and method of manufacturing resin-sealed semiconductor device

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