JP3953746B2 - Semiconductor package and semiconductor package manufacturing method - Google Patents

Semiconductor package and semiconductor package manufacturing method Download PDF

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Publication number
JP3953746B2
JP3953746B2 JP2001115381A JP2001115381A JP3953746B2 JP 3953746 B2 JP3953746 B2 JP 3953746B2 JP 2001115381 A JP2001115381 A JP 2001115381A JP 2001115381 A JP2001115381 A JP 2001115381A JP 3953746 B2 JP3953746 B2 JP 3953746B2
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Prior art keywords
semiconductor package
sealing
lead
peripheral lead
manufacturing
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JP2002314024A (en
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健一 白坂
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Yamaha Corp
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Yamaha Corp
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Priority to JP2001115381A priority Critical patent/JP3953746B2/en
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to CNB021055211A priority patent/CN1321455C/en
Priority to US10/120,391 priority patent/US7170149B2/en
Priority to KR1020020020076A priority patent/KR100677651B1/en
Priority to TW091107454A priority patent/TW543172B/en
Publication of JP2002314024A publication Critical patent/JP2002314024A/en
Priority to HK03101103A priority patent/HK1048890A1/en
Priority to US11/516,705 priority patent/US7554182B2/en
Priority to KR1020060095868A priority patent/KR100836303B1/en
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Publication of JP3953746B2 publication Critical patent/JP3953746B2/en
Priority to KR1020080005353A priority patent/KR100831818B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パッケージに関し、特に、リード数を増やして小型化することが可能な半導体パッケージ及び半導体パッケージの製造方法に関する。
【０００２】
【従来の技術】
近年、電子機器に搭載される半導体部品を高密度に実装する必要性から、半導体パッケージの小型化が求められ、これを目的とした半導体パッケージとして、ＱＦＮ（Quad Flatpack Non-leaded package）が用いられている。これは、半導体パッケージの側方に突出していたアウターリードをなくし、半導体パッケージの下面側に基板との電気的接続を行うための外部電極を設けた半導体パッケージである。
半導体パッケージは通常、その気密性を確保するために、封止樹脂でリードフレームを封止されて形成されている。特許第３０１２８１６号公報には、リードフレームの上面ばかりでなく、その下面をも樹脂封止して気密性を高めたＱＦＮが提案されている。また、放熱性の向上を図るために、半導体チップを支持するステージの下面を露出させて封止樹脂でリードフレームを封止したＱＦＮが特開２０００−２４３８９１号公報において提案されている。
【０００３】
【発明が解決しようとする課題】
しかし、このようにして封止を行うと、封止される部分の面積の大きさによって、リードを設けることができる数が制限され、これによって、必要なリード数を確保するためには封止樹脂の面積を大きくせざるを得ず、半導体パッケージの小型化を図ることが困難であった。
本発明は、このような事情を考慮してなされたもので、半導体パッケージの寸法を大きくせずにリード数を増やすことによって、小型化が可能な半導体パッケージを実現し、信頼性の高い半導体パッケージを製造することが可能な半導体パッケージの製造方法を提供することを目的とする。
【０００４】
【課題を解決するための手段】
以上の課題を解決するために、請求項１に記載の発明は、パッケージ底面側外周部に外周リードを設け、半導体チップを支持するステージの周辺部に内周リードを一体化して設け、該内周リードの底面がパッケージ外に露出された半導体パッケージの製造方法であって、該内周リード下面での樹脂バリ発生を防止して封止する工程を有することを特徴とする半導体パッケージの製造方法である。
請求項２に記載の発明は、前記樹脂バリ発生を防止して封止する工程は、前記内周リードの位置を前記外周リードの位置よりも下方に設定してモールド金型でクランプし封止する工程であることを特徴とする請求項１に記載の半導体パッケージの製造方法である。
請求項３に記載の発明は、前記樹脂バリ発生を防止して封止する工程は、前記内周リードの下面に封止テープを接触させて封止する工程であることを特徴とする請求項１に記載の半導体パッケージの製造方法である。
【０００５】
【発明の実施の形態】
以下、本発明を詳細に説明する。
図１は、本発明の半導体パッケージの例を示す図である。図１（ａ）は半導体パッケージ１の上面図であり、図１（ｂ）は図１（ａ）に示した半導体パッケージ１のＡ―Ａ´断面図である。
図１中、符号２は半導体チップであり、ステージ３によって支持されている。
符号４は、ステージ３の周辺部に設けられた内周リードであり、符号５は半導体パッケージ１の底面側外周部に設けられた外周リードである。内周リード４と外周リード５は、いずれも半導体チップ２上のボンディングパッドと金属細線６によって電気的に接続されている。また、ステージ３の下面は、内周リード４及び外周リード５の下面より上に位置している。これら半導体チップ２、ステージ３、内周リード４、外周リード５等は封止樹脂７によって封止されている。
【０００６】
このように、この例の半導体パッケージにおいては、通常のＱＦＮ(Quad Flatpack Non-leaded package)において設けられている外周リード５ばかりでなく、ステージ３の周辺部に内周リード４が設けられている。この内周リード４は、グランドピン等の同電位ピン同士をステージ３を介してショートさせることによって、ステージ３の周辺部をリードとして機能させるようにしたものである。このようにして設けられた内周リード４は、主にグランド端子として用いることができるため、半導体パッケージ１の外周部に設けられた外周リード５の数を減らすことができ、封止樹脂の面積を増大させることなく、半導体パッケージ１の大きさを保ったままで、半導体パッケージ１が有するリード数を増やすことができる。
このようにして設けられた内周リード４は、その全てが同電位となるようにして用いることができる。
この例によると、ステージ３の周辺部に内周リード４を設けることにより、半導体パッケージ１の大きさを保ったままで、半導体パッケージ１のリード数を増やすことができ、小型化が可能な半導体パッケージ１を実現することができる。
【０００７】
次に、本発明の半導体パッケージの製造方法の例について説明する。
内周リード４及び外周リード５は、その下面が基板との電気的接続を行うための外部電極となるため、封止樹脂７で封止する際、内周リード４及び外周リード５の下面に樹脂バリが発生しないことが必要となる。この樹脂バリの発生を防止することができる半導体パッケージの製造方法の例を図２に示す。
図２中、符号１１はモールド金型であり、符号１１ａはモールド金型の上型、符号１１ｂはモールド金型の下型である。ボンディング済みのリードフレームがモールド金型１１にセットされ、加熱された封止樹脂７がモールド金型１１に封入される。この封止工程において、外周リード５は、モールド金型の上型１１ａと下型１１ｂとに挟まれている位置から近いため、金型クランプが強く、そのため外周リード５下面への樹脂バリはほとんど発生しない。
【０００８】
しかし、内周リード４は、モールド金型の上型１１ａと下型１１ｂとに挟まれている位置から遠く、直接クランプされないため、樹脂封入時に内周リード４が内側に押され、内周リード４の下側に樹脂バリが発生しやすい。この樹脂バリの発生を防止するため、図２に示すように、下面と上面との間の厚さが、外周リードの下面と上面との間の厚さよりも厚くなっている内周リード４の位置を、外周リード５の位置よりも予めΔｄだけ下方に設定しておき、このようにオフセットされた状態でモールド金型１１の上型１１ａと下型１１ｂとでクランプし、封止樹脂７によって封止する。
この例によると、内周リード４の位置を外周リード５の位置よりも下方に設定してモールド金型でクランプし封止することにより、内周リード４も下型１１ｂに確実に接触させることができるので、内周リード４の下面での樹脂バリの発生を防止することができ、基板との電気的接続を確実に行うことのできる信頼性の高い半導体パッケージの製造が可能な半導体パッケージの製造方法を実現することができる。
【０００９】
次に、樹脂バリの発生を防止することができる半導体パッケージの製造方法の第２の例を図３に示す。
図３は、内周リード４の下面に封止テープ２０を接触させた状態でモールド金型１１にセットし、加熱された封止樹脂７をモールド金型に投入して封止する例である。この封止テープ２０は、ポリイミド、ポリエチレンテレフタレート、ポリカーボネート等を主成分とする樹脂をベースとしたテープであり、樹脂封止後は容易に剥がすことができ、樹脂封止時の高温環境に耐性のあるものが用いられる。この封止テープ２０を用いると、樹脂封止時に、内周リード４の下面に封止樹脂が回りこむことを防ぐことができ、樹脂バリの発生を防止することができる。
なお、ここでは、内周リード４の下面のみに封止テープ２０を接触させて封止する場合について説明したが、封止テープ２０を内周リード４ばかりでなく外周リード５の下面にも接触させて封止してもよい。
この例によると、内周リード４の下面に封止テープ２０を接触させて樹脂封止を行うことにより、内周リード４の下面での樹脂バリの発生を防止することができ、基板との電気的接続を確実に行うことのできる信頼性の高い半導体パッケージの製造が可能な半導体パッケージの製造方法を実現することができる。
【００１０】
【発明の効果】
以上説明したように、本発明によると、ステージの周辺部に内周リードを設けることにより、半導体パッケージの大きさを保ったままで、半導体パッケージのリード数を増やすことができ、小型化が可能な半導体パッケージを実現することができる。
また、内周リードの位置を外周リードの位置よりも下方に設定してモールド金型でクランプし封止することにより、内周リードの下面での樹脂バリの発生を防止することができ、基板との電気的接続を確実に行うことのできる信頼性の高い半導体パッケージの製造が可能な半導体パッケージの製造方法を実現することができる。
さらに、内周リードの下面に封止テープを接触させて樹脂封止を行うことにより、内周リードの下面での樹脂バリの発生を防止することができ、基板との電気的接続を確実に行うことのできる信頼性の高い半導体パッケージの製造が可能な半導体パッケージの製造方法を実現することができる。
【図面の簡単な説明】
【図１】本発明の半導体パッケージの例を示す図である。
【図２】本発明の半導体パッケージの製造方法の第１の例を示す図である。
【図３】本発明の半導体パッケージの製造方法の第２の例を示す図である。
【符号の説明】
１…半導体パッケージ、２…半導体チップ、３…ステージ、４…内周リード、
５…外周リード、６…金属細線、７…封止樹脂
１１…モールド金型、２０…封止テープ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package, and more particularly to a semiconductor package that can be reduced in size by increasing the number of leads and a method for manufacturing the semiconductor package.
[0002]
[Prior art]
In recent years, miniaturization of semiconductor packages has been required due to the necessity of mounting semiconductor components mounted on electronic devices at high density, and QFN (Quad Flatpack Non-leaded package) is used as a semiconductor package for this purpose. ing. This is a semiconductor package in which the outer leads protruding to the side of the semiconductor package are eliminated, and an external electrode is provided on the lower surface side of the semiconductor package for electrical connection with the substrate.
A semiconductor package is usually formed by sealing a lead frame with a sealing resin in order to ensure hermeticity. Japanese Patent No. 3012816 proposes a QFN in which not only the upper surface of the lead frame but also the lower surface thereof is resin-sealed to improve airtightness. Japanese Patent Laid-Open No. 2000-243891 proposes QFN in which the lower surface of a stage supporting a semiconductor chip is exposed and a lead frame is sealed with a sealing resin in order to improve heat dissipation.
[0003]
[Problems to be solved by the invention]
However, when sealing is performed in this way, the number of leads that can be provided is limited by the size of the area of the portion to be sealed, and in order to secure the necessary number of leads, sealing is required. The area of the resin has to be increased, and it has been difficult to reduce the size of the semiconductor package.
The present invention has been made in view of such circumstances, and by increasing the number of leads without increasing the size of the semiconductor package, a semiconductor package that can be miniaturized is realized, and a highly reliable semiconductor package An object of the present invention is to provide a method of manufacturing a semiconductor package capable of manufacturing the semiconductor package.
[0004]
[Means for Solving the Problems]
In order to solve the above problems, the invention according to claim 1, the outer peripheral lead provided on the package bottom side peripheral portion, provided by integrating the inner periphery lead to the periphery of the stage supporting the semiconductor chip, inner A method of manufacturing a semiconductor package in which a bottom surface of a peripheral lead is exposed to the outside of the package, the method including a step of sealing by preventing generation of a resin burr on a lower surface of the inner peripheral lead It is.
According to a second aspect of the present invention, the step of sealing by preventing the generation of the resin burrs is performed by setting the position of the inner peripheral lead below the position of the outer peripheral lead and clamping with a mold. The method of manufacturing a semiconductor package according to claim 1, wherein
The invention described in claim 3 is characterized in that the step of sealing by preventing the generation of the resin burrs is a step of sealing by bringing a sealing tape into contact with the lower surface of the inner peripheral lead. 1. A method for producing a semiconductor package according to 1 .
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail.
FIG. 1 is a diagram showing an example of a semiconductor package of the present invention. 1A is a top view of the semiconductor package 1, and FIG. 1B is a cross-sectional view taken along the line AA ′ of the semiconductor package 1 shown in FIG.
In FIG. 1, reference numeral 2 denotes a semiconductor chip, which is supported by a stage 3.
Reference numeral 4 is an inner peripheral lead provided in the peripheral part of the stage 3, and reference numeral 5 is an outer peripheral lead provided in the outer peripheral part on the bottom surface side of the semiconductor package 1. Both the inner peripheral lead 4 and the outer peripheral lead 5 are electrically connected to the bonding pads on the semiconductor chip 2 by the metal thin wires 6. Further, the lower surface of the stage 3 is located above the lower surfaces of the inner peripheral lead 4 and the outer peripheral lead 5. These semiconductor chip 2, stage 3, inner peripheral lead 4, outer peripheral lead 5 and the like are sealed with a sealing resin 7.
[0006]
Thus, in the semiconductor package of this example, not only the outer peripheral lead 5 provided in the normal QFN (Quad Flatpack Non-leaded package) but also the inner peripheral lead 4 is provided in the peripheral portion of the stage 3. . The inner peripheral lead 4 is configured such that the peripheral portion of the stage 3 functions as a lead by short-circuiting the same potential pins such as the ground pin via the stage 3. Since the inner peripheral leads 4 thus provided can be used mainly as ground terminals, the number of outer peripheral leads 5 provided on the outer peripheral portion of the semiconductor package 1 can be reduced, and the area of the sealing resin The number of leads of the semiconductor package 1 can be increased while maintaining the size of the semiconductor package 1 without increasing the size.
The inner circumferential leads 4 thus provided can be used so that all of them have the same potential.
According to this example, by providing the inner peripheral leads 4 around the stage 3, the number of leads of the semiconductor package 1 can be increased while maintaining the size of the semiconductor package 1, and the semiconductor package can be reduced in size. 1 can be realized.
[0007]
Next, an example of a method for manufacturing a semiconductor package of the present invention will be described.
Since the inner peripheral lead 4 and the outer peripheral lead 5 are external electrodes for making electrical connection with the substrate, the inner peripheral lead 4 and the outer peripheral lead 5 are formed on the lower surfaces of the inner peripheral lead 4 and the outer peripheral lead 5 when sealing with the sealing resin 7. It is necessary that no resin burrs are generated. An example of a method for manufacturing a semiconductor package capable of preventing the occurrence of this resin burr is shown in FIG.
In FIG. 2, reference numeral 11 denotes a mold, reference numeral 11a denotes an upper mold, and reference numeral 11b denotes a lower mold. The bonded lead frame is set in the mold 11, and the heated sealing resin 7 is sealed in the mold 11. In this sealing step, the outer peripheral lead 5 is close to the position sandwiched between the upper mold 11a and the lower mold 11b of the mold, so that the mold clamp is strong, and therefore there is almost no resin burr on the lower surface of the outer peripheral lead 5. Does not occur.
[0008]
However, since the inner circumferential lead 4 is far from the position sandwiched between the upper mold 11a and the lower mold 11b of the mold and is not directly clamped, the inner circumferential lead 4 is pushed inward when the resin is sealed, and the inner circumferential lead 4 Resin burrs are likely to occur on the lower side of 4. In order to prevent the occurrence of this resin burr, as shown in FIG. 2, the thickness of the inner circumferential lead 4 in which the thickness between the lower surface and the upper surface is larger than the thickness between the lower surface and the upper surface of the outer circumferential lead. The position is set in advance by Δd below the position of the outer peripheral lead 5, and clamped by the upper mold 11 a and the lower mold 11 b of the mold 11 in such an offset state, and the sealing resin 7 Seal.
According to this example, by setting the position of the inner peripheral lead 4 below the position of the outer peripheral lead 5 and clamping and sealing with a mold, the inner peripheral lead 4 can be surely brought into contact with the lower mold 11b. Therefore, the generation of resin burrs on the lower surface of the inner circumferential lead 4 can be prevented, and a highly reliable semiconductor package capable of reliably making electrical connection with the substrate can be manufactured. A manufacturing method can be realized.
[0009]
Next, FIG. 3 shows a second example of a semiconductor package manufacturing method capable of preventing the occurrence of resin burrs.
FIG. 3 shows an example in which the sealing tape 20 is in contact with the lower surface of the inner peripheral lead 4 and set in the mold 11 and the heated sealing resin 7 is put into the mold and sealed. . This sealing tape 20 is a tape based on a resin mainly composed of polyimide, polyethylene terephthalate, polycarbonate or the like, and can be easily peeled off after resin sealing, and is resistant to a high temperature environment during resin sealing. Some are used. If this sealing tape 20 is used, it can prevent that sealing resin wraps around the lower surface of the inner periphery lead 4 at the time of resin sealing, and can prevent generation | occurrence | production of a resin burr | flash.
Here, the case where the sealing tape 20 is brought into contact with and sealed only on the lower surface of the inner peripheral lead 4 has been described. However, the sealing tape 20 is contacted not only with the inner peripheral lead 4 but also with the lower surface of the outer peripheral lead 5. May be sealed.
According to this example, by causing the sealing tape 20 to come into contact with the lower surface of the inner peripheral lead 4 and performing resin sealing, the occurrence of resin burrs on the lower surface of the inner peripheral lead 4 can be prevented. A semiconductor package manufacturing method capable of manufacturing a highly reliable semiconductor package capable of reliably performing electrical connection can be realized.
[0010]
【The invention's effect】
As described above, according to the present invention, the number of leads of the semiconductor package can be increased and the size can be reduced while the size of the semiconductor package is maintained by providing the inner peripheral lead in the peripheral portion of the stage. A semiconductor package can be realized.
In addition, by setting the position of the inner peripheral lead below the position of the outer peripheral lead and clamping and sealing with a mold, it is possible to prevent the occurrence of resin burrs on the lower surface of the inner peripheral lead. It is possible to realize a semiconductor package manufacturing method capable of manufacturing a highly reliable semiconductor package capable of reliably performing electrical connection with.
Furthermore, by performing resin sealing by bringing the sealing tape into contact with the lower surface of the inner circumferential lead, it is possible to prevent the occurrence of resin burrs on the lower surface of the inner circumferential lead and to ensure electrical connection with the substrate. A semiconductor package manufacturing method capable of manufacturing a highly reliable semiconductor package that can be performed can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a semiconductor package of the present invention.
FIG. 2 is a diagram showing a first example of a method of manufacturing a semiconductor package according to the present invention.
FIG. 3 is a diagram showing a second example of a method of manufacturing a semiconductor package according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor package, 2 ... Semiconductor chip, 3 ... Stage, 4 ... Inner circumference lead | read | reed,
5 ... Outer peripheral lead, 6 ... Fine metal wire, 7 ... Sealing resin 11 ... Mold, 20 ... Sealing tape

Claims (3)

パッケージ底面側外周部に外周リードを設け、半導体チップを支持するステージの周辺部に内周リードを一体化して設け、該内周リードの底面がパッケージ外に露出された半導体パッケージの製造方法であって、該内周リード下面での樹脂バリ発生を防止して封止する工程を有することを特徴とする半導体パッケージの製造方法。An outer peripheral lead is provided on the outer peripheral portion of the bottom surface of the package, and an inner peripheral lead is integrally provided on the peripheral portion of the stage that supports the semiconductor chip, and the manufacturing method of the semiconductor package is such that the bottom surface of the inner peripheral lead is exposed outside the package. A method of manufacturing a semiconductor package, comprising the step of sealing by preventing generation of a resin burr on the lower surface of the inner peripheral lead. 前記樹脂バリ発生を防止して封止する工程は、前記内周リードの位置を前記外周リードの位置よりも下方に設定してモールド金型でクランプし封止する工程であることを特徴とする請求項１に記載の半導体パッケージの製造方法。The step of sealing by preventing the generation of the resin burrs is a step of setting the position of the inner peripheral lead below the position of the outer peripheral lead, and clamping and sealing with a mold. The manufacturing method of the semiconductor package of Claim 1. 前記樹脂バリ発生を防止して封止する工程は、前記内周リードの下面に封止テープを接触させて封止する工程であることを特徴とする請求項１に記載の半導体パッケージの製造方法。2. The method of manufacturing a semiconductor package according to claim 1, wherein the step of sealing by preventing the generation of resin burrs is a step of sealing by bringing a sealing tape into contact with the lower surface of the inner peripheral lead. .
JP2001115381A 2001-04-13 2001-04-13 Semiconductor package and semiconductor package manufacturing method Expired - Fee Related JP3953746B2 (en)

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JP2001115381A JP3953746B2 (en) 2001-04-13 2001-04-13 Semiconductor package and semiconductor package manufacturing method
US10/120,391 US7170149B2 (en) 2001-04-13 2002-04-12 Semiconductor device and package, and method of manufacture therefor
KR1020020020076A KR100677651B1 (en) 2001-04-13 2002-04-12 Semiconductor device and package, and method of manufacture therefor
TW091107454A TW543172B (en) 2001-04-13 2002-04-12 Semiconductor device and package, and method of manufacture therefor
CNB021055211A CN1321455C (en) 2001-04-13 2002-04-12 Semiconductor device and packaging and its manufacturing method
HK03101103A HK1048890A1 (en) 2001-04-13 2003-02-15 Semiconductor device and package, and method of manufacture therefor
US11/516,705 US7554182B2 (en) 2001-04-13 2006-09-07 Semiconductor device and package, and method of manufacturer therefor
KR1020060095868A KR100836303B1 (en) 2001-04-13 2006-09-29 Semiconductor device and package, and method of manufacture therefor
KR1020080005353A KR100831818B1 (en) 2001-04-13 2008-01-17 Semiconductor package

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