JP2002314024A - Semiconductor package and its manufacturing method - Google Patents
Semiconductor package and its manufacturing methodInfo
- Publication number
- JP2002314024A JP2002314024A JP2001115381A JP2001115381A JP2002314024A JP 2002314024 A JP2002314024 A JP 2002314024A JP 2001115381 A JP2001115381 A JP 2001115381A JP 2001115381 A JP2001115381 A JP 2001115381A JP 2002314024 A JP2002314024 A JP 2002314024A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- lead
- sealing
- manufacturing
- peripheral lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケージ
に関し、特に、リード数を増やして小型化することが可
能な半導体パッケージ及び半導体パッケージの製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package which can be reduced in size by increasing the number of leads and a method of manufacturing the semiconductor package.
【０００２】[0002]
【従来の技術】近年、電子機器に搭載される半導体部品
を高密度に実装する必要性から、半導体パッケージの小
型化が求められ、これを目的とした半導体パッケージと
して、ＱＦＮ（Quad Flatpack Non-leaded package）が
用いられている。これは、半導体パッケージの側方に突
出していたアウターリードをなくし、半導体パッケージ
の下面側に基板との電気的接続を行うための外部電極を
設けた半導体パッケージである。半導体パッケージは通
常、その気密性を確保するために、封止樹脂でリードフ
レームを封止されて形成されている。特許第３０１２８
１６号公報には、リードフレームの上面ばかりでなく、
その下面をも樹脂封止して気密性を高めたＱＦＮが提案
されている。また、放熱性の向上を図るために、半導体
チップを支持するステージの下面を露出させて封止樹脂
でリードフレームを封止したＱＦＮが特開２０００−２
４３８９１号公報において提案されている。2. Description of the Related Art In recent years, there has been a demand for miniaturization of semiconductor packages due to the necessity of mounting semiconductor components mounted on electronic devices at a high density. package) is used. This is a semiconductor package in which outer leads protruding to the side of the semiconductor package are eliminated, and external electrodes for making electrical connection with a substrate are provided on the lower surface side of the semiconductor package. A semiconductor package is usually formed by sealing a lead frame with a sealing resin in order to ensure airtightness. Patent No. 30128
No. 16 discloses not only the upper surface of the lead frame,
A QFN in which the lower surface is also sealed with a resin to improve airtightness has been proposed. Also, in order to improve heat dissipation, a QFN in which a lower surface of a stage supporting a semiconductor chip is exposed and a lead frame is sealed with a sealing resin is disclosed in JP-A-2000-2.
No. 4,389,91.
【０００３】[0003]
【発明が解決しようとする課題】しかし、このようにし
て封止を行うと、封止される部分の面積の大きさによっ
て、リードを設けることができる数が制限され、これに
よって、必要なリード数を確保するためには封止樹脂の
面積を大きくせざるを得ず、半導体パッケージの小型化
を図ることが困難であった。本発明は、このような事情
を考慮してなされたもので、半導体パッケージの寸法を
大きくせずにリード数を増やすことによって、小型化が
可能な半導体パッケージを実現し、信頼性の高い半導体
パッケージを製造することが可能な半導体パッケージの
製造方法を提供することを目的とする。However, when sealing is performed in this manner, the number of leads that can be provided is limited by the size of the area of the portion to be sealed. In order to secure the number, it is necessary to increase the area of the sealing resin, and it is difficult to reduce the size of the semiconductor package. The present invention has been made in view of such circumstances, and by increasing the number of leads without increasing the size of the semiconductor package, a semiconductor package that can be reduced in size is realized, and a highly reliable semiconductor package is realized. It is an object of the present invention to provide a method of manufacturing a semiconductor package capable of manufacturing a semiconductor package.
【０００４】[0004]
【課題を解決するための手段】以上の課題を解決するた
めに、請求項１記載の発明は、パッケージ底面側外周部
に基板との電気的接続のための外周リードを設けた半導
体パッケージにおいて、 半導体チップを支持するため
のステージの周辺部に、基板との電気的接続のための内
周リードを設けたことを特徴とする半導体パッケージで
ある。請求項２記載の発明は、請求項１記載の発明にお
いて、内周リードの全てが同電位であることを特徴とす
る。請求項３記載の発明は、パッケージ底面側外周部に
外周リードを設け、半導体チップを支持するステージの
周辺部に内周リードを設けた半導体パッケージを製造方
法する際、内周リード下面での樹脂バリ発生防止手段を
備えた封止工程を有することを特徴とする半導体パッケ
ージの製造方法である。請求項４記載の発明は、請求項
３記載の発明において、封止工程を、内周リードの位置
を外周リードの位置よりも下方に設定してモールド金型
でクランプし封止する工程としたことを特徴とする。請
求項５記載の発明は、請求項３記載の発明において、封
止工程を、内周リードの下面に封止テープを接触させて
封止する工程としたことを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor package having an outer peripheral lead for electrical connection with a substrate at an outer peripheral portion on a bottom surface side of the package. A semiconductor package characterized in that an inner peripheral lead for electrical connection with a substrate is provided at a periphery of a stage for supporting a semiconductor chip. According to a second aspect of the present invention, in the first aspect, all of the inner peripheral leads have the same potential. According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor package having an outer peripheral lead provided on an outer peripheral portion on a package bottom side and an inner peripheral lead provided on a peripheral portion of a stage supporting a semiconductor chip. A method of manufacturing a semiconductor package, comprising a sealing step including a burr generation preventing means. According to a fourth aspect of the present invention, in the third aspect of the present invention, the sealing step is a step of setting the position of the inner peripheral lead below the position of the outer peripheral lead, and clamping and sealing with a mold. It is characterized by the following. A fifth aspect of the present invention is characterized in that, in the third aspect of the invention, the sealing step is a step of sealing by bringing a sealing tape into contact with the lower surface of the inner peripheral lead.
【０００５】[0005]
【発明の実施の形態】以下、本発明を詳細に説明する。
図１は、本発明の半導体パッケージの例を示す図であ
る。図１（ａ）は半導体パッケージ１の上面図であり、
図１（ｂ）は図１（ａ）に示した半導体パッケージ１の
Ａ―Ａ´断面図である。図１中、符号２は半導体チップ
であり、ステージ３によって支持されている。符号４
は、ステージ３の周辺部に設けられた内周リードであ
り、符号５は半導体パッケージ１の底面側外周部に設け
られた外周リードである。内周リード４と外周リード５
は、いずれも半導体チップ２上のボンディングパッドと
金属細線６によって電気的に接続されている。これら半
導体チップ２、ステージ３、内周リード４、外周リード
５等は封止樹脂７によって封止されている。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.
FIG. 1 is a diagram showing an example of a semiconductor package of the present invention. FIG. 1A is a top view of the semiconductor package 1.
FIG. 1B is a cross-sectional view taken along the line AA ′ of the semiconductor package 1 shown in FIG. In FIG. 1, reference numeral 2 denotes a semiconductor chip, which is supported by a stage 3. Code 4
Reference numeral 5 denotes an inner peripheral lead provided at a peripheral portion of the stage 3, and reference numeral 5 denotes an outer peripheral lead provided at an outer peripheral portion on the bottom surface side of the semiconductor package 1. Inner circumference lead 4 and outer circumference lead 5
Are electrically connected to bonding pads on the semiconductor chip 2 by thin metal wires 6. The semiconductor chip 2, the stage 3, the inner leads 4, the outer leads 5, and the like are sealed with a sealing resin 7.
【０００６】このように、この例の半導体パッケージに
おいては、通常のＱＦＮ(Quad Flatpack Non-leaded pa
ckage)において設けられている外周リード５ばかりでな
く、ステージ３の周辺部に内周リード４が設けられてい
る。この内周リード４は、グランドピン等の同電位ピン
同士をステージ３を介してショートさせることによっ
て、ステージ３の周辺部をリードとして機能させるよう
にしたものである。このようにして設けられた内周リー
ド４は、主にグランド端子として用いることができるた
め、半導体パッケージ１の外周部に設けられた外周リー
ド５の数を減らすことができ、封止樹脂の面積を増大さ
せることなく、半導体パッケージ１の大きさを保ったま
まで、半導体パッケージ１が有するリード数を増やすこ
とができる。このようにして設けられた内周リード４
は、その全てが同電位となるようにして用いることがで
きる。この例によると、ステージ３の周辺部に内周リー
ド４を設けることにより、半導体パッケージ１の大きさ
を保ったままで、半導体パッケージ１のリード数を増や
すことができ、小型化が可能な半導体パッケージ１を実
現することができる。As described above, in the semiconductor package of this example, a normal QFN (Quad Flatpack Non-leaded pad) is used.
In addition to the outer leads 5 provided in the ckage), the inner leads 4 are provided around the stage 3. The inner lead 4 is configured such that the same potential pins such as ground pins are short-circuited via the stage 3 so that the peripheral portion of the stage 3 functions as a lead. Since the inner leads 4 provided in this manner can be used mainly as ground terminals, the number of outer leads 5 provided on the outer periphery of the semiconductor package 1 can be reduced, and the area of the sealing resin can be reduced. Without increasing the size, the number of leads of the semiconductor package 1 can be increased while the size of the semiconductor package 1 is maintained. Inner circumference lead 4 provided in this manner
Can be used so that all of them have the same potential. According to this example, the number of leads of the semiconductor package 1 can be increased while maintaining the size of the semiconductor package 1 by providing the inner peripheral leads 4 in the peripheral portion of the stage 3, and the semiconductor package which can be downsized. 1 can be realized.
【０００７】次に、本発明の半導体パッケージの製造方
法の例について説明する。内周リード４及び外周リード
５は、その下面が基板との電気的接続を行うための外部
電極となるため、封止樹脂７で封止する際、内周リード
４及び外周リード５の下面に樹脂バリが発生しないこと
が必要となる。この樹脂バリの発生を防止することがで
きる半導体パッケージの製造方法の例を図２に示す。図
２中、符号１１はモールド金型であり、符号１１ａはモ
ールド金型の上型、符号１１ｂはモールド金型の下型で
ある。ボンディング済みのリードフレームがモールド金
型１１にセットされ、加熱された封止樹脂７がモールド
金型１１に封入される。この封止工程において、外周リ
ード５は、モールド金型の上型１１ａと下型１１ｂとに
挟まれている位置から近いため、金型クランプが強く、
そのため外周リード５下面への樹脂バリはほとんど発生
しない。Next, an example of a method of manufacturing a semiconductor package according to the present invention will be described. Since the lower surfaces of the inner leads 4 and the outer leads 5 serve as external electrodes for making an electrical connection with the substrate, the inner leads 4 and the outer leads 5 It is necessary that resin burrs do not occur. FIG. 2 shows an example of a method of manufacturing a semiconductor package capable of preventing the occurrence of resin burrs. In FIG. 2, reference numeral 11 denotes a mold, reference numeral 11a denotes an upper mold, and reference numeral 11b denotes a lower mold. The bonded lead frame is set in the mold 11 and the heated sealing resin 7 is sealed in the mold 11. In this sealing step, since the outer peripheral lead 5 is close to the position between the upper mold 11a and the lower mold 11b of the mold, the mold clamp is strong,
Therefore, resin burrs on the lower surface of the outer leads 5 hardly occur.
【０００８】しかし、内周リード４は、モールド金型の
上型１１ａと下型１１ｂとに挟まれている位置から遠
く、直接クランプされないため、樹脂封入時に内周リー
ド４が内側に押され、内周リード４の下側に樹脂バリが
発生しやすい。この樹脂バリの発生を防止するため、図
２に示すように、内周リード４の位置を外周リード５の
位置よりも予めΔｄだけ下方に設定しておき、このよう
にオフセットされた状態でモールド金型１１の上型１１
ａと下型１１ｂとでクランプし、封止樹脂７によって封
止する。この例によると、内周リード４の位置を外周リ
ード５の位置よりも下方に設定してモールド金型でクラ
ンプし封止することにより、内周リード４も下型１１ｂ
に確実に接触させることができるので、内周リード４の
下面での樹脂バリの発生を防止することができ、基板と
の電気的接続を確実に行うことのできる信頼性の高い半
導体パッケージの製造が可能な半導体パッケージの製造
方法を実現することができる。However, since the inner lead 4 is far from the position between the upper mold 11a and the lower mold 11b of the mold and is not directly clamped, the inner lead 4 is pushed inward when the resin is filled. Resin burrs are easily generated below the inner lead 4. In order to prevent the occurrence of resin burrs, as shown in FIG. 2, the position of the inner peripheral lead 4 is previously set to be lower than the position of the outer peripheral lead 5 by Δd. Upper mold 11 of mold 11
a and the lower mold 11b are clamped and sealed with the sealing resin 7. According to this example, the position of the inner peripheral lead 4 is set lower than the position of the outer peripheral lead 5, and the inner peripheral lead 4 is also clamped and sealed with a mold so that the inner peripheral lead 4 is also in the lower mold 11 b.
, The occurrence of resin burrs on the lower surface of the inner peripheral lead 4 can be prevented, and the manufacture of a highly reliable semiconductor package capable of reliably performing electrical connection with the substrate. And a method of manufacturing a semiconductor package capable of performing the above.
【０００９】次に、樹脂バリの発生を防止することがで
きる半導体パッケージの製造方法の第２の例を図３に示
す。図３は、内周リード４の下面に封止テープ２０を接
触させた状態でモールド金型１１にセットし、加熱され
た封止樹脂７をモールド金型に投入して封止する例であ
る。この封止テープ２０は、ポリイミド、ポリエチレン
テレフタレート、ポリカーボネート等を主成分とする樹
脂をベースとしたテープであり、樹脂封止後は容易に剥
がすことができ、樹脂封止時の高温環境に耐性のあるも
のが用いられる。この封止テープ２０を用いると、樹脂
封止時に、内周リード４の下面に封止樹脂が回りこむこ
とを防ぐことができ、樹脂バリの発生を防止することが
できる。なお、ここでは、内周リード４の下面のみに封
止テープ２０を接触させて封止する場合について説明し
たが、封止テープ２０を内周リード４ばかりでなく外周
リード５の下面にも接触させて封止してもよい。この例
によると、内周リード４の下面に封止テープ２０を接触
させて樹脂封止を行うことにより、内周リード４の下面
での樹脂バリの発生を防止することができ、基板との電
気的接続を確実に行うことのできる信頼性の高い半導体
パッケージの製造が可能な半導体パッケージの製造方法
を実現することができる。Next, FIG. 3 shows a second example of a method of manufacturing a semiconductor package capable of preventing occurrence of resin burrs. FIG. 3 shows an example in which the sealing tape 20 is set in contact with the lower surface of the inner peripheral lead 4 in the mold 11 and the heated sealing resin 7 is put into the mold and sealed. . The sealing tape 20 is a tape based on a resin containing polyimide, polyethylene terephthalate, polycarbonate or the like as a main component, and can be easily peeled off after resin sealing, and is resistant to a high temperature environment at the time of resin sealing. Some are used. When this sealing tape 20 is used, it is possible to prevent the sealing resin from flowing around the lower surface of the inner peripheral lead 4 at the time of sealing the resin, and it is possible to prevent the occurrence of resin burrs. Here, the case where the sealing tape 20 is brought into contact with only the lower surface of the inner peripheral lead 4 for sealing is described, but the sealing tape 20 is brought into contact with the lower surface of not only the inner peripheral lead 4 but also the outer peripheral lead 5. And sealed. According to this example, resin sealing is performed by bringing the sealing tape 20 into contact with the lower surface of the inner peripheral lead 4, thereby preventing occurrence of resin burrs on the lower surface of the inner peripheral lead 4, and A semiconductor package manufacturing method capable of manufacturing a highly reliable semiconductor package capable of reliably performing electrical connection can be realized.
【００１０】[0010]
【発明の効果】以上説明したように、本発明によると、
ステージの周辺部に内周リードを設けることにより、半
導体パッケージの大きさを保ったままで、半導体パッケ
ージのリード数を増やすことができ、小型化が可能な半
導体パッケージを実現することができる。また、内周リ
ードの位置を外周リードの位置よりも下方に設定してモ
ールド金型でクランプし封止することにより、内周リー
ドの下面での樹脂バリの発生を防止することができ、基
板との電気的接続を確実に行うことのできる信頼性の高
い半導体パッケージの製造が可能な半導体パッケージの
製造方法を実現することができる。さらに、内周リード
の下面に封止テープを接触させて樹脂封止を行うことに
より、内周リードの下面での樹脂バリの発生を防止する
ことができ、基板との電気的接続を確実に行うことので
きる信頼性の高い半導体パッケージの製造が可能な半導
体パッケージの製造方法を実現することができる。As described above, according to the present invention,
By providing the inner peripheral lead at the periphery of the stage, the number of leads of the semiconductor package can be increased while the size of the semiconductor package is maintained, and a semiconductor package that can be reduced in size can be realized. Also, by setting the position of the inner peripheral lead below the position of the outer peripheral lead and clamping and sealing with a mold, it is possible to prevent the occurrence of resin burrs on the lower surface of the inner peripheral lead, A semiconductor package manufacturing method capable of manufacturing a highly reliable semiconductor package capable of reliably performing electrical connection with the semiconductor package can be realized. Furthermore, resin sealing is performed by bringing the sealing tape into contact with the lower surface of the inner lead, thereby preventing the occurrence of resin burrs on the lower surface of the inner lead and ensuring electrical connection with the substrate. It is possible to realize a semiconductor package manufacturing method capable of manufacturing a highly reliable semiconductor package.
【図１】本発明の半導体パッケージの例を示す図であ
る。FIG. 1 is a diagram showing an example of a semiconductor package of the present invention.
【図２】本発明の半導体パッケージの製造方法の第１の
例を示す図である。FIG. 2 is a diagram showing a first example of a method for manufacturing a semiconductor package according to the present invention.
【図３】本発明の半導体パッケージの製造方法の第２の
例を示す図である。FIG. 3 is a view showing a second example of the method of manufacturing a semiconductor package according to the present invention.
１…半導体パッケージ、２…半導体チップ、３…ステー
ジ、４…内周リード、５…外周リード、６…金属細線、
７…封止樹脂 １１…モールド金型、２０…封止テープDESCRIPTION OF SYMBOLS 1 ... Semiconductor package, 2 ... Semiconductor chip, 3 ... Stage, 4 ... Inner circumference lead, 5 ... Outer circumference lead, 6 ... Metal thin wire,
7 sealing resin 11 molding die 20 sealing tape
Claims (5)
的接続のための外周リードを設けた半導体パッケージに
おいて、 半導体チップを支持するためのステージの周辺部に、該
基板との電気的接続のための内周リードを設けたことを
特徴とする半導体パッケージ。In a semiconductor package having an outer peripheral lead provided on an outer peripheral portion on a package bottom surface side for electrical connection with a substrate, a peripheral portion of a stage for supporting a semiconductor chip is electrically connected to the substrate. A semiconductor package provided with an inner peripheral lead for use.
とを特徴とする請求項１記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein all of the inner leads are at the same potential.
設け、半導体チップを支持するステージの周辺部に内周
リードを設けた半導体パッケージの製造方法であって、 該内周リード下面での樹脂バリ発生を防止して封止する
工程を有することを特徴とする半導体パッケージの製造
方法。3. A method of manufacturing a semiconductor package, comprising providing an outer peripheral lead on an outer peripheral portion on a package bottom side and an inner peripheral lead on a peripheral portion of a stage for supporting a semiconductor chip, wherein a resin burr on a lower surface of the inner peripheral lead is provided. A method for manufacturing a semiconductor package, comprising a step of preventing occurrence and sealing.
程は、前記内周リードの位置を前記外周リードの位置よ
りも下方に設定してモールド金型でクランプし封止する
工程であることを特徴とする請求項３記載の半導体パッ
ケージの製造方法。4. The step of sealing by preventing occurrence of resin burrs is a step of setting the position of the inner peripheral lead below the position of the outer peripheral lead and clamping and sealing with a mold. 4. The method for manufacturing a semiconductor package according to claim 3, wherein:
程は、前記内周リードの下面に封止テープを接触させて
封止する工程であることを特徴とする請求項３記載の半
導体パッケージの製造方法。5. The semiconductor according to claim 3, wherein the step of sealing by preventing the occurrence of resin burrs is a step of sealing by bringing a sealing tape into contact with a lower surface of the inner peripheral lead. Package manufacturing method.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001115381A JP3953746B2 (en) | 2001-04-13 | 2001-04-13 | Semiconductor package and semiconductor package manufacturing method |
| TW091107454A TW543172B (en) | 2001-04-13 | 2002-04-12 | Semiconductor device and package, and method of manufacture therefor |
| US10/120,391 US7170149B2 (en) | 2001-04-13 | 2002-04-12 | Semiconductor device and package, and method of manufacture therefor |
| CNB021055211A CN1321455C (en) | 2001-04-13 | 2002-04-12 | Semiconductor device and packaging and its manufacturing method |
| KR1020020020076A KR100677651B1 (en) | 2001-04-13 | 2002-04-12 | Semiconductor device and package, and method of manufacture therefor |
| HK03101103A HK1048890A1 (en) | 2001-04-13 | 2003-02-15 | Semiconductor device and package, and method of manufacture therefor |
| US11/516,705 US7554182B2 (en) | 2001-04-13 | 2006-09-07 | Semiconductor device and package, and method of manufacturer therefor |
| KR1020060095868A KR100836303B1 (en) | 2001-04-13 | 2006-09-29 | Semiconductor device and package, and method of manufacture therefor |
| KR1020080005353A KR100831818B1 (en) | 2001-04-13 | 2008-01-17 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001115381A JP3953746B2 (en) | 2001-04-13 | 2001-04-13 | Semiconductor package and semiconductor package manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005294652A Division JP4055175B2 (en) | 2005-10-07 | 2005-10-07 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002314024A true JP2002314024A (en) | 2002-10-25 |
| JP3953746B2 JP3953746B2 (en) | 2007-08-08 |
Family
ID=18966289
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001115381A Expired - Fee Related JP3953746B2 (en) | 2001-04-13 | 2001-04-13 | Semiconductor package and semiconductor package manufacturing method |
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| Country | Link |
|---|---|
| JP (1) | JP3953746B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008091956A (en) * | 2007-12-26 | 2008-04-17 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
| US7397112B2 (en) | 2004-12-24 | 2008-07-08 | Yamaha Corporation | Semiconductor package and lead frame therefor |
| JP2009252778A (en) * | 2008-04-01 | 2009-10-29 | Sharp Corp | Manufacturing method of semiconductor package |
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|---|---|---|---|---|
| JPH10275887A (en) * | 1997-03-31 | 1998-10-13 | Nec Corp | Semiconductor device |
| JPH11233683A (en) * | 1998-02-10 | 1999-08-27 | Dainippon Printing Co Ltd | Resin-encapsulated type semiconductor device, circuit member used for the device, and manufacture thereof |
| JP2000196006A (en) * | 1998-12-24 | 2000-07-14 | Matsushita Electronics Industry Corp | Semiconductor device and method of manufacturing the same |
| JP2001077285A (en) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | Lead frame and manufacture of resin-sealed semiconductor device using the same |
| JP2001313363A (en) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | Resin-encapsulated semiconductor device |
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2001
- 2001-04-13 JP JP2001115381A patent/JP3953746B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10275887A (en) * | 1997-03-31 | 1998-10-13 | Nec Corp | Semiconductor device |
| JPH11233683A (en) * | 1998-02-10 | 1999-08-27 | Dainippon Printing Co Ltd | Resin-encapsulated type semiconductor device, circuit member used for the device, and manufacture thereof |
| JP2000196006A (en) * | 1998-12-24 | 2000-07-14 | Matsushita Electronics Industry Corp | Semiconductor device and method of manufacturing the same |
| JP2001077285A (en) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | Lead frame and manufacture of resin-sealed semiconductor device using the same |
| JP2001313363A (en) * | 2000-05-01 | 2001-11-09 | Rohm Co Ltd | Resin-encapsulated semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7397112B2 (en) | 2004-12-24 | 2008-07-08 | Yamaha Corporation | Semiconductor package and lead frame therefor |
| JP2008091956A (en) * | 2007-12-26 | 2008-04-17 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
| JP2009252778A (en) * | 2008-04-01 | 2009-10-29 | Sharp Corp | Manufacturing method of semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3953746B2 (en) | 2007-08-08 |
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