JP3036339B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3036339B2 JP3036339B2 JP31696493A JP31696493A JP3036339B2 JP 3036339 B2 JP3036339 B2 JP 3036339B2 JP 31696493 A JP31696493 A JP 31696493A JP 31696493 A JP31696493 A JP 31696493A JP 3036339 B2 JP3036339 B2 JP 3036339B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- insulating adhesive
- resin
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はCOL半導体装置とその
リードフレーム及びその製造方法に係わり更に詳しくは
リードフレームインナーリード部の上面に絶縁接着テー
プ或いは絶縁接着剤等の絶縁性接合手段を用いてIC素
子を搭載固定する部分をフォーミングする事により樹脂
封止後のプラスチックパッケージ厚の薄型化が可能とな
る又樹脂封止時のモールド金型に対してリードフレーム
インナーリード、IC素子、ワイヤ、の配置バランスが
良くなる為に封止樹脂注入時のリードフレームインナー
リード,IC素子、ワイヤ、への悪影響が取り除かれ封
止樹脂でインナー部を保護すると言う本来の目的を充分
に達成できる。以上のとうりLOC半導体装置の薄型
化、高信頼性化に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a COL semiconductor device, a lead frame thereof, and a method of manufacturing the same. More particularly, the present invention relates to a method for manufacturing a COL semiconductor device using an insulating adhesive tape or an insulating adhesive on the upper surface of a lead frame inner lead portion. Forming the part where the IC element is mounted and fixed makes it possible to reduce the thickness of the plastic package after resin encapsulation. In order to improve the arrangement balance, an adverse effect on the lead frame inner lead, the IC element, and the wire when the sealing resin is injected is removed, and the original purpose of protecting the inner portion with the sealing resin can be sufficiently achieved. The above relates to thinning and high reliability of the LOC semiconductor device.
【0002】[0002]
【従来の技術】図4は従来のCOL(チップオンリー
ド)構造の半導体装置の一般的ワイヤ高の断面図であ
る。図4において、リードフレームインナーリード2部
の上面に絶縁接着テープ或いは絶縁接着剤等4の絶縁性
接合手段を用いてIC素子3を固着する。次にIC素子
3のワイヤボンディングパットとリードフレームインナ
ーリード2とをワイヤ5で配線する。次にモールド工程
にてプラスチック樹脂1を注入成形し半導体装置のリー
ドフレームインナーリード2の全体を樹脂封止保護す
る。最後にプレス工程でリードフレームアウターリード
6を折り曲げ加工し半導体装置の外部端子とする。2. Description of the Related Art FIG. 4 is a sectional view of a conventional semiconductor device having a COL (chip-on-lead) structure at a general wire height. In FIG. 4, the IC element 3 is fixed to the upper surface of the inner lead 2 of the lead frame using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive 4. Next, the wire bonding pad of the IC element 3 and the lead frame inner lead 2 are wired with the wire 5. Next, in a molding process, the plastic resin 1 is injection-molded to entirely seal and protect the lead frame inner leads 2 of the semiconductor device. Finally, the outer lead 6 of the lead frame is bent in a pressing step to form an external terminal of the semiconductor device.
【0003】図5は従来のCOL(チップオンリード)
構造の半導体装置を薄型化する為にワイヤ高を低くして
配線した断面図である。図5においてリードフレームイ
ンナーリード2部の上面に絶縁接着テープ或いは絶縁接
着剤等4の絶縁性接合手段を用いてIC素子3を固着す
る。次にIC素子3のワイヤボンディングパットとリー
ドフレームインナーリード2とをワイヤ5で配線する。
この時IC素子3の上面ギリギリにワイヤ5の高さを設
定する。次にモールド行程にてプラスチック樹脂1を注
入成形し半導体装置のリードフレームインナーリード2
の全体を樹脂封止保護する。最後にプレス行程でリード
フレームアウターリード6を折り曲げ加工し半導体装置
の外部端子とする。FIG. 5 shows a conventional COL (chip-on-lead).
FIG. 3 is a cross-sectional view in which wiring is performed with a reduced wire height in order to reduce the thickness of a semiconductor device having a structure. In FIG. 5, the IC element 3 is fixed to the upper surface of the inner lead 2 of the lead frame by using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive 4. Next, the wire bonding pad of the IC element 3 and the lead frame inner lead 2 are wired with the wire 5.
At this time, the height of the wire 5 is set almost at the top of the IC element 3. Next, in a molding process, a plastic resin 1 is injection-molded to form a lead frame inner lead 2 of a semiconductor device.
Is resin-sealed and protected. Finally, the outer lead 6 of the lead frame is bent in the pressing step to form an external terminal of the semiconductor device.
【0004】[0004]
【発明が解決しようとする課題】上記のようにリードフ
レームインナーリード部の上面に絶縁接着テープ或いは
絶縁接着剤等の絶縁性接合手段を用いてIC素子を固定
する構造を有する半導体装置は図4においてリードフレ
ームインナーリード2部の上面に絶縁接着テープ或いは
絶縁接着剤等4、を施し更にIC素子3を貼り重ねた上
にIC素子3のワイヤボンディングパットとリードフレ
ームインナーリード2とをワイヤ5で配線するワイヤ5
の垂れ下がりを加味しIC素子3の上面から300μm
以上上げて配線しなければならない、更にはモールド樹
脂1封止後のワイヤ5を保護する為の樹脂厚8が少なく
ても200〜500μm以上が必要であり、更にはモー
ルド工程での樹脂封止時の樹脂1の流動によるワイヤ5
の移動をある程度見込まねばならない等薄型化したいが
できないと言う課題があった。図5において薄型化する
為に無理をしてIC素子3の上面ギリギリにワイヤ5を
配線しても前述と同様にワイヤ5が垂れ下がったりモー
ルド工程での樹脂1注入時にワイヤ移動が発生してIC
素子3の端面とワイヤ5とのショートが発生し薄型化し
たいができないと言う課題があった。又図4、図5にお
いて半導体装置の水平方向上半分と下半分の配置バラン
スが崩れているためにモールド工程で樹脂封止する際に
も樹脂注入圧力バランスが崩れてリードフレームインナ
ーリード2部の移動IC素子3の移動ワイヤ5の移動と
言う数々の課題がある。FIG. 4 shows a semiconductor device having a structure in which an IC element is fixed to the upper surface of a lead frame inner lead portion by using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive as described above. Then, an insulating adhesive tape or an insulating adhesive 4 is applied to the upper surface of the lead frame inner lead 2 and the IC element 3 is pasted thereon, and the wire bonding pad of the IC element 3 and the lead frame inner lead 2 are connected with the wire 5. Wire to be wired 5
300 μm from the top surface of IC element 3
The wiring must be raised above, and the resin thickness 8 for protecting the wire 5 after sealing the molding resin 1 must be at least 200 to 500 μm or more. Wire 5 due to the flow of resin 1 at the time
However, there is a problem that it is not possible to make the device thinner, for example, it is necessary to allow some movement. In FIG. 5, even if the wire 5 is laid barely on the upper surface of the IC element 3 to make it thinner, the wire 5 hangs down or the wire moves during the injection of the resin 1 in the molding process as described above.
There is a problem that a short circuit between the end face of the element 3 and the wire 5 occurs and it is desired to reduce the thickness. Also, in FIGS. 4 and 5, since the arrangement balance between the upper half and the lower half of the semiconductor device in the horizontal direction is disturbed, the resin injection pressure balance is disturbed even when the resin is sealed in the molding process, and the lead frame inner leads 2 There are a number of problems of moving the moving wire 5 of the moving IC element 3.
【0005】本発明は上記の課題を解決する為になされ
たものでリードフレームインナーリード部上面に絶縁接
着テープ或いは絶縁接着剤等の絶縁性接合手段を用いて
IC素子を固定する箇所を下方向にフォーミングするこ
とにより半導体装置の薄型化が可能となるばかりでなく
モールド工程での樹脂封止時の注入バランスが良い為に
リードフレームインナーリード、IC素子、ワイヤの移
動と言う悪影響が及ばず安定した信頼性が得られしかも
高歩留りの製造方法が得られることを目的とするもので
ある。The present invention has been made in order to solve the above-mentioned problem, and the place where an IC element is fixed on an upper surface of a lead frame inner lead portion by using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive is directed downward. In addition to making the semiconductor device thinner by forming into the mold, the injection balance at the time of resin encapsulation in the molding process is good, so that there is no adverse effect such as the movement of the lead frame inner lead, IC element, and wire, which is stable. It is an object of the present invention to obtain a highly reliable manufacturing method with a high yield.
【0006】[0006]
【課題を解決するための手段】本発明のリードフレーム
インナーリード部の上面に絶縁接着テープ或いは絶縁接
着剤等の絶縁性接合手段を用いてIC素子を固定する構
造のプラスチック樹脂封止の半導体装置はリードフレー
ムインナーリード部の上面に接着テープ或いは接着剤等
の絶縁性接合手段を用いてIC素子を固定する部分を下
方向にフォーミングする。このリードフレームインナー
リード部上面の下方向へのフォーミング量は使用リード
フレームインナーリード厚、使用絶縁接着テープ厚、使
用絶縁接着剤厚、使用IC素子厚、ワイヤボンデング時
のワイヤループ高さを考慮して設定するが概ねリードフ
レームインナーリード厚の1/2+IC素子厚の1/2
+絶縁接着テープ或いは絶縁接着剤等の厚みの1/2を
目処に設定すれば良くこうする事によって樹脂封止した
半導体装置のセンターにIC素子が配置される。このよ
うな手段をとることにより半導体装置の薄型化が可能と
なるばかりでなくモールド加工工程での樹脂封止する際
の樹脂注入バランスが良くなり高品質でしかも安定した
プラスチック樹脂封止の半導体装置が得られる。SUMMARY OF THE INVENTION A plastic resin-sealed semiconductor device having a structure in which an IC element is fixed to the upper surface of an inner lead portion of a lead frame of the present invention by using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive. Forms downward the portion for fixing the IC element on the upper surface of the inner lead portion of the lead frame by using an insulating bonding means such as an adhesive tape or an adhesive. The amount of downward forming of the upper surface of the lead frame inner lead part is based on the thickness of the used lead frame inner lead, the used insulating adhesive tape, the used insulating adhesive, the used IC element, and the wire loop height during wire bonding. Approximately 1/2 of the lead frame inner lead thickness + 1/2 of the IC element thickness
It is sufficient to set about 1/2 of the thickness of the insulating adhesive tape or the insulating adhesive or the like, so that the IC element is arranged at the center of the semiconductor device sealed with resin. By taking such measures, not only can the thickness of the semiconductor device be reduced, but also the resin injection balance at the time of resin sealing in the molding process is improved, and a high quality and stable plastic resin sealed semiconductor device. Is obtained.
【0007】[0007]
【実施例】図1は本発明の第1の実施例を示す断面図で
ある。図1においてリードフレームインナーリード2部
の上面に絶縁接着テープ或いは絶縁接着剤等4の絶縁性
接合手段を用いてIC素子3を固定する箇所を下方向に
フォーミング7する、下方向にフォーミングする量は使
用するリードフレームインナーリード厚、使用するリー
ドフレームインナーリードとIC素子とを絶縁性接合す
る為の絶縁接着テープ或いは絶縁接着剤等の厚み、使用
するIC素子厚、ワイヤボンデング時のワイヤループ高
さを考慮して設定するがプラスチック樹脂で封止した完
成品の半導体装置の総厚の中心にIC素子厚の中心が配
置される様設定するのが望ましい。次にIC素子3を絶
縁接着テープ或いは絶縁接着剤等4の絶縁性接合手段を
用いて下方向にフォーミング7されているリードフレー
ムインナーリード2部のIC素子搭載部へ固着する。I
C素子3のワイヤボンデングパットとリードフレームイ
ンナーリード2をワイヤで結線する。一般的にワイヤの
高さはIC素子表面から300μmぐらいである。更に
モールド工程での樹脂封止後のワイヤ5からの保護樹脂
厚8を概ね200〜500μm位に設計する。次にリー
ドフレームを樹脂封止のモールド工程の金型にセット後
樹脂を注入し封止する、樹脂封止する際にパッケージ水
平方向上半分と下半分の体積バランスが良い為にワイヤ
5、及びIC素子3、リードフレームインナーリード2
部のIC素子搭載部、リードフレームインナーリードフ
ォーミング箇所7、は樹脂流入時の移動等の悪影響を受
けないで樹脂封止することが可能となる、最後にリード
フレームアウターリード6をプレス工程で折り曲げ切断
し半導体装置の端子とする。FIG. 1 is a sectional view showing a first embodiment of the present invention. In FIG. 1, the portion where the IC element 3 is fixed is formed 7 on the upper surface of the lead frame inner lead 2 using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive 4, and the amount of the downward forming is formed. Is the thickness of the lead frame inner lead to be used, the thickness of the insulating adhesive tape or insulating adhesive for insulatingly connecting the used lead frame inner lead to the IC element, the thickness of the IC element to be used, the wire loop at the time of wire bonding. The height is set in consideration of the height, but it is desirable to set the center of the IC element thickness at the center of the total thickness of the completed semiconductor device sealed with plastic resin. Next, the IC element 3 is fixed to the IC element mounting portion of the lead frame inner lead 2 portion formed downward 7 by using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive 4. I
The wire bonding pad of the C element 3 and the lead frame inner lead 2 are connected by a wire. Generally, the height of the wire is about 300 μm from the surface of the IC element. Further, the thickness 8 of the protective resin from the wire 5 after resin sealing in the molding process is designed to be approximately 200 to 500 μm. Next, the lead frame is set in a mold in a resin-sealing molding step, and then resin is injected and sealed. When the resin is sealed, the wire 5 is used because the upper half and the lower half of the package have a good volume balance. IC element 3, lead frame inner lead 2
The IC chip mounting portion and the lead frame inner lead forming portion 7 can be resin-sealed without being adversely affected by movement or the like when the resin flows in. Finally, the lead frame outer lead 6 is bent in a pressing step Cut to make terminals of the semiconductor device.
【0008】図2は本発明の第2の実施例を示すIC素
子を搭載固定する部分のリードフレームインナーリード
部にディンプル加工を施したリードフレームの平面図で
ある。 図2においてリードフレームインナーリード2
部のIC素子搭載固定部9にディンプル加工をしIC素
子搭載固定部ディンプル10とする。ディンプル加工を
した事により絶縁接着テープ或いは絶縁接着剤等の絶縁
性接合手段を用いてIC素子をリードフレームインナー
リードのIC搭載固定部9に絶縁性接合した際の接着力
が増加し安定した品質が得られる。FIG. 2 is a plan view of a lead frame according to a second embodiment of the present invention, in which an inner lead portion of a lead frame at which an IC element is mounted and fixed is subjected to dimple processing. In FIG. 2, the lead frame inner lead 2
Dimple processing is performed on the IC element mounting and fixing portion 9 of the portion to obtain an IC element mounting and fixing portion dimple 10. Due to the dimple processing, the adhesive strength when the IC element is insulatively joined to the IC mounting and fixing portion 9 of the lead frame inner lead by using an insulative joining means such as an insulative adhesive tape or an insulative adhesive increases the stable quality. Is obtained.
【0009】図3は本発明の第3の実施例を示すIC素
子を搭載固定する部分のインナーリードを下方向にフォ
ーミング加工する為の金型断面図である。図3において
プレス機械にセットされているフォーミングダイ12に
リードフレームをセットしフォーミングパンチ11を下
ろす、リードフレームインナーリード9のIC素子搭載
固定部にフォーミングパンチ、ダイの形状が移りリード
フレームインナーリード部フォーミング箇所7から下方
向にIC素子搭載固定部9の加工ができると同時に絶縁
接着テープ或いは絶縁接着剤等の絶縁性接合手段を用い
た時の接着力を増す為のディンプル加工もフォーミング
パンチ11にディンプル模様がありこのディンプル模様
がリードフレームインナーリードのIC素子搭載固定部
9に移りフォーミング加工と同時加工が可能である。プ
レス加工が可能な為に安価にスピーディーにしかも精度
の良いリードフレームの提供ができる。FIG. 3 is a sectional view showing a third embodiment of the present invention, which is a die for forming an inner lead in a portion for mounting and fixing an IC element in a downward direction. In FIG. 3, the lead frame is set on the forming die 12 set on the press machine, and the forming punch 11 is lowered. The shape of the forming punch and die is transferred to the IC element mounting fixing portion of the lead frame inner lead 9, and the lead frame inner lead portion is moved. It is possible to process the IC element mounting and fixing portion 9 downward from the forming portion 7 and, at the same time, to form a dimple on the forming punch 11 to increase the adhesive force when using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive. There is a dimple pattern, and the dimple pattern is transferred to the IC element mounting fixing portion 9 of the inner lead of the lead frame, and can be formed simultaneously with the forming process. Since press working is possible, it is possible to provide an inexpensive, speedy and accurate lead frame.
【0010】[0010]
【発明の効果】以上述べたとうり本発明によればリード
フレームインナーリード部上面に絶縁接着テープ或いは
絶縁接着剤等の絶縁性接合手段を用いてIC素子を搭載
固定する構造の(C,O,Lチップオンリード)半導体
装置用のリードフレームのインナーリードのIC素子搭
載固定部を下方向にフォーミングする事により樹脂封止
された半導体装置のセンターにIC素子のセンターが配
置され、配置バランスが良い為にモールド加工工程で樹
脂封止する際の樹脂注入バランス良くなり高品質で安定
したプラスチック樹脂封止の半導体装置が得られる。又
本発明の最大効果であるリードフレームインナーリード
IC素子搭載固定部を下方向へフォーミングする量がパ
ッケージ厚を薄型化可能量となる。又インナーリードを
下方向ヘフォーミングする事により搭載されたIC素子
上面のパットとリードフレームインナーボンディング部
との段差が減少する為にワイヤがIC素子コーナー部と
ショートし難くなりこの分ワイヤの高さを低くする事が
可能となりワイヤを低くした分パッケージ厚を薄型化で
きる。又IC素子を搭載固定する部分のインナーリード
にディンプル加工を施した事により絶縁接着テープ或い
は絶縁接着剤等の接着力が上がり品質の安定した半導体
装置の製造が可能となる。As described above, according to the present invention, there is provided a structure (C, O, O) in which an IC element is mounted and fixed on an upper surface of a lead frame inner lead portion using an insulating bonding means such as an insulating adhesive tape or an insulating adhesive. L-chip-on-lead) The IC element center is arranged at the center of the resin-sealed semiconductor device by forming the IC element mounting fixing portion of the inner lead of the lead frame for the semiconductor device downward, and the arrangement balance is good. The resin injection balance at the time of resin encapsulation in the molding process is improved, and a high quality and stable semiconductor device with plastic resin encapsulation can be obtained. In addition, the amount of downward forming of the fixing portion for mounting the lead frame inner lead IC element, which is the greatest effect of the present invention, is the amount by which the package thickness can be reduced. Also, since the step between the pad on the upper surface of the mounted IC element and the lead frame inner bonding portion is reduced by forming the inner lead downward, the wire is less likely to short-circuit with the corner of the IC element, and the height of the wire is reduced accordingly. And the thickness of the package can be reduced by the reduction in the wire. In addition, by performing dimple processing on the inner lead at the portion where the IC element is mounted and fixed, the adhesive force of an insulating adhesive tape or an insulating adhesive is increased, and a semiconductor device with stable quality can be manufactured.
【図1】本発明の第1の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図2】本発明の第2の実施例を示す平面図。FIG. 2 is a plan view showing a second embodiment of the present invention.
【図3】本発明の第3の実施例を示す断面図。FIG. 3 is a sectional view showing a third embodiment of the present invention.
【図4】従来のCOL構造の半導体装置の一般的ワイヤ
高さの断面図。FIG. 4 is a sectional view of a general wire height of a conventional semiconductor device having a COL structure.
【図5】従来のCOL構造の半導体装置の薄型化の為の
低ワイヤ高さの断面図。FIG. 5 is a cross-sectional view of a low wire height for thinning a conventional COL structure semiconductor device.
1…モールド封止樹脂 2…リードフレームインナーリード 3…IC素子 4…絶縁接着テープ或いは絶縁接着剤 5…ワイヤ 6…リードフレームアウターリード 7…リードフレームインナーリード部フォーミング箇所 8…保護樹脂厚 9…IC素子搭載固定部 10…IC素子搭載固定部ディンプル 11…フォーミングパンチ 12…フォーミングダイ 13…ディンプル模様付け部 DESCRIPTION OF SYMBOLS 1 ... Mold sealing resin 2 ... Lead frame inner lead 3 ... IC element 4 ... Insulating adhesive tape or insulating adhesive 5 ... Wire 6 ... Lead frame outer lead 7 ... Lead frame inner lead forming part 8 ... Protective resin thickness 9 ... IC element mounting fixed part 10: IC element mounting fixed part dimple 11: forming punch 12: forming die 13: dimple patterning part
Claims (3)
と、 一方が前記IC素子の他方の面と相重なる位置にまで延
出され、他方が外部との接続用の端子として用いられる
複数のリードと、 前記リード上の前記IC素子の前記他方の面と相重なる
位置に設けられ前記IC素子と前記リードとの間に介在
し、前記IC素子と前記リードとを固定する絶縁接着部
材と、 前記IC素子の前記電極と前記リードとを電気的に接続
した接続部材と、 前記IC素子及び前記接着部材並びに前記リードの一部
を封止する樹脂と、 を有し、 前記リードにおける前記IC素子の他方の面に相重なる
領域と、前記リードにおける前記接続部材の接続された
領域との間の位置において段差が形成されてなることを
特徴とする半導体装置。An IC element having an electrode formed on one surface, and a plurality of IC elements each extending to a position overlapping with the other surface of the IC element and the other being used as a terminal for connection to the outside. And an insulating adhesive member provided at a position overlapping with the other surface of the IC element on the lead, interposed between the IC element and the lead, and fixing the IC element and the lead. A connection member that electrically connects the electrode of the IC element and the lead; and a resin that seals a part of the IC element, the adhesive member, and the lead. A semiconductor device, wherein a step is formed at a position between a region overlapping with the other surface of the element and a region of the lead to which the connection member is connected.
の面と相重なる位置で且つ前記絶縁接着部材が設けられ
る位置にはディンプルが形成されてなることを特徴とす
る請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein a dimple is formed at a position of the lead overlapping with the other surface of the IC element and at a position where the insulating adhesive member is provided.
C素子厚の中心が配置されるように設定されてなること
を特徴とする請求項1記載の半導体装置。3. The step is formed at the center of the thickness of the resin.
2. The semiconductor device according to claim 1, wherein a center of the C element thickness is set.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31696493A JP3036339B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31696493A JP3036339B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07169780A JPH07169780A (en) | 1995-07-04 |
JP3036339B2 true JP3036339B2 (en) | 2000-04-24 |
Family
ID=18082905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31696493A Expired - Fee Related JP3036339B2 (en) | 1993-12-16 | 1993-12-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3036339B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102106918B1 (en) | 2016-04-22 | 2020-05-06 | 후루카와 덴키 고교 가부시키가이샤 | Winding, coil and transformer |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3275787B2 (en) * | 1997-08-04 | 2002-04-22 | 松下電器産業株式会社 | Resin-sealed semiconductor device and method of manufacturing the same |
KR20120081459A (en) | 2011-01-11 | 2012-07-19 | 삼성전자주식회사 | Semiconductor packages having lead frames |
CN113270514B (en) * | 2021-04-19 | 2023-01-06 | 中国电子科技集团公司第十一研究所 | Non-vacuum refrigeration type infrared detector and packaging method thereof |
-
1993
- 1993-12-16 JP JP31696493A patent/JP3036339B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102106918B1 (en) | 2016-04-22 | 2020-05-06 | 후루카와 덴키 고교 가부시키가이샤 | Winding, coil and transformer |
Also Published As
Publication number | Publication date |
---|---|
JPH07169780A (en) | 1995-07-04 |
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