JP2001185567A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which can ensure sufficient margin of stand off enough, and can prevent the turning of sealing material into a lead terminal part. SOLUTION: This QFN structure of surface-mounting-type package is composed of a semiconductor chip mounted on a tub, and a plurality of leads electrically connected to the pad on this semiconductor chip through a wire, a sealing material to seal the tube, a semiconductor chip, a wire, and a lead such that is exposes the downside of these leads, and others, and out of the molds used for sealing elements with this sealing material, especially a lower mold 11 has a structure with the section that the lead being engage with is recessed, and that the section to come under the tub is projected, within the range of being sealed with a sealing material, excluding the section that the lead is to engage with, and also the height of the section of the projection under the tab is set, based on the thickness of the lead.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device assembling technique, and more particularly to a semiconductor device suitable for securing a stand-off between a lower surface of the package and a mounting substrate in a surface mount type package such as a QFN structure. The present invention relates to a technology that is effective when applied to a manufacturing method.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a surface mount type package having a QFN structure, a distance within a predetermined range between a package lower surface and a mounting board, a so-called stand, is taken into consideration in consideration of board mountability. A method for securing the off state is conceivable. That is, by ensuring the stand-off of the surface mount package, the yield of the substrate mountability can be improved.

[0003] Techniques related to such a surface mount type package having a QFN structure include, for example, 199
The techniques described in “Nikkei Electronics no. 587”, pp. 104 to 118, issued by Nikkei BP on Aug. 2, 1993, may be mentioned.

[0004]

By the way, regarding the technology of the surface mount type package having the QFN structure as described above,
As a result of the study by the present inventors, the following has become clear. For example, a package having a QFN structure includes a semiconductor chip 2 mounted on a tab 1 as shown in FIG.
A plurality of leads 4 electrically connected to the pads on the semiconductor chip 2 via the wires 3, and a tab 1, the semiconductor chip 2, the wires 3, and Sealing material 5 for sealing the lead 4
It is composed of

When the package having the QFN structure is sealed with a sealing material, for example, as shown in FIG. 6 (corresponding to FIG. Lower mold 1 having a lower surface portion formed in a concave shape
By sealing using a mold composed of the upper mold 1 and the upper mold 12 formed in an inverted concave shape, the lower surface of the tab 1 is covered and the lower surface of the lead 4 is exposed. The exposed lower surface of the lead 4 is plated with solder plating 6, and a stand-off can be secured by the thickness of the solder plating 6.

However, in a sealing process using a mold having a structure as shown in FIG. 6, the sealing material 5 goes around the lower surface side of the lead 4 and the lead terminal portion is covered by the sealing material 5 and hidden. There is a risk that it will. When the lead terminal portion is covered with the sealing material 5 as described above, it is conceivable that a problem occurs in the bonding property with the mounting substrate.

Accordingly, an object of the present invention is to improve the structure of a sealing mold in a surface mount type package such as a QFN structure so that a stand-off margin can be sufficiently secured and a lead terminal portion can be provided. The present invention provides a semiconductor device and a method for manufacturing the same, which can prevent the encapsulant from wrapping around.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor device according to the present invention, the tab, the semiconductor, and the semiconductor chip mounted on the tab are exposed so that the lower surfaces of a plurality of leads electrically connected via wires are exposed. In a surface mounting type semiconductor device including a chip, a wire, and a sealing material for sealing a lead, a thickness direction of each lead exposed from the sealing material is exposed with a predetermined dimension.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described surface-mount type semiconductor device, when sealing with a sealing material, a portion where a lead is fitted is formed in a concave shape, The tab on the lower surface side is sealed with a mold including a lower mold having a convex structure. Thus, a sufficient stand-off margin between the lower surface of the package and the mounting substrate can be secured.

In this manufacturing method, the convex portion on the lower surface side of the tab is formed in a convex shape within a range sealed by the sealing material except for a portion where the lead is fitted, so that the lower surface of the lead is formed. The sealing material can be prevented from wrapping around to the side, and the height of the convex portion on the lower surface side of the tab is set based on the thickness of the lead, so that the height in the thickness direction of the tab and the lead can be reduced. It is designed to be able to cope with processing.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a flowchart showing an assembling method in the semiconductor device according to the present embodiment, and FIG.
4 and FIG. 4 are a plan view and a sectional view showing a sealing mold.

First, an example of the configuration of the semiconductor device of the present embodiment will be described with reference to FIG. The semiconductor device of the present embodiment is, for example, a surface mount package having a QFN structure, and is electrically connected to a semiconductor chip 2 mounted on a tab 1 and a pad on the semiconductor chip 2 via a wire 3. A plurality of leads 4 and a sealing material 5 for sealing the tabs 1, the semiconductor chip 2, the wires 3, and the leads 4 so as to expose the lower surfaces of the leads 4.
The thickness direction of each lead 4 that is exposed from is exposed at a predetermined dimension.

The tab 1 and the lead 4 are formed of a strip-shaped lead frame made of, for example, Cu or the like, and the tab 1 supported by four tab suspension leads is provided at the center of each portion corresponding to one semiconductor chip 2. Is provided, and this tab 1
A plurality of leads 4 are provided so as to surround the tab 1 in the vicinity of the periphery of the lead, and solder plating 6 is applied to the exposed lower surfaces of these leads 4 to become external terminals. The lower surface of the tab 1 is subjected to, for example, a half-etching process so that a lead 4 is formed.
About half the thickness of the part.

The semiconductor chip 2 includes, for example, a microcomputer,
A predetermined integrated circuit such as an ASIC, a gate array, a system LSI, and a memory is formed, and a plurality of pads 7 serving as external terminals of the integrated circuit are provided on a main surface. The semiconductor chip 2 is fixed on the tab 1 by an adhesive such as a non-conductive paste.

The wire 3 is made of a metal wire such as Au, for example, and the pad 7 on the semiconductor chip 2 and one end of the lead 4 are electrically connected via the wire 3.

The sealing material 5 is made of a resin material such as an epoxy resin. The tab 1, the semiconductor chip 2, the wires 3 and the leads 4 are protected by the sealing material 5 so that the lower surfaces of the leads 4 are exposed. , And sealed to improve moisture resistance.

Next, an example of a method of assembling the semiconductor device according to the present embodiment will be briefly described with reference to FIG. In FIG. 2, the figure on the right side is a cross-sectional view of the semiconductor device corresponding to each flow. Prior to this assembling, a semiconductor chip 2 formed by dicing from a wafer, a lead frame formed in a plurality of units such as ten strips, wires 3, a sealing material 5, and the like are prepared.

First, a die bonding step (step S)
In 1), a plurality of semiconductor chips 2 are respectively fixed to a plurality of tabs 1 of a lead frame formed in a strip shape with an adhesive. Further, in a wire bonding step (Step S2), each pad 7 on each of the plurality of semiconductor chips 2 is connected to one end of each of the plurality of leads 4 of the lead frame by a wire 3.

Subsequently, in a sealing step (step S3), the strip-shaped lead frame to which the plurality of semiconductor chips 2 are fixed is connected to the tab 1, the semiconductor chip 2, and the semiconductor chip 2 so that the lower surfaces of the leads 4 are exposed. The wires 3 and the leads 4 are sealed with a sealing material 5. In this sealing step, a mold as shown in FIGS. 3 and 4 is particularly used, which will be described in detail below. FIG. 3 is a plan view of the lower mold, and FIGS. 4 (a) and 4 (b).
3 is a cross-sectional view (including an upper mold) taken along a cutting line aa ′ and a cutting line bb ′ in FIG. 3, respectively. In addition, this mold
For simplicity, a 20-pin package is shown as an example.

That is, among the molds composed of the lower mold 11 and the upper mold 12, the lower mold 11 has a concave portion at the portion where the lead 4 is fitted, and the lower portion of the tab 1 has the lead 4 Except for a portion where the tab 1 is fitted, the tab 1 has a structure formed in a convex shape in a range sealed by the sealing material 5.
The height of the convex portion on the lower surface side is set based on the thickness of the lead 4. For example, when the thickness dimension of the lead 4 is 150
μm, the height L of the concave portion of the lower mold 11
1 is about 150 μm, and the height L2 of the convex portion is 50
It is formed to a thickness of about μm.

In this sealing step, first, the lead frame is mounted at a predetermined position on the lower mold 11 of the transfer molding apparatus, and the upper mold 12 and the lower mold 11 are clamped. A cavity 13 in which the tab 1, the semiconductor chip 2, the wires 3 and the leads 4 are sealed by the sealing material 5 is formed on the mating surface of the two clamped molds. Fill. The filled sealing material 5 goes around the lower surface of the half-etched tub 1 and reliably hermetically seals the tub 1, the semiconductor chip 2, the wires 3 and the leads 4. At the same time, the lead 4
Is sufficiently exposed, and the sealing material 5 does not go around the lower surface of the lead 4.

Subsequently, in an exterior processing step (step S4), a plating process is performed to apply the solder plating 6 to the portions of the leads 4 exposed from the sealing material 5. Thereby, for example, when the thickness of the solder plating 6 is about 25 μm, the height of about 50 μm of the height L2 of the convex portion on the lower surface side of the tab 1 due to the shape of the lower mold 11 is added by about 75 μm. Only, a stand-off margin between the lower surface of the package and the mounting substrate can be secured.

Finally, in a cutting step (step S5), the lead frame is cut at a position outside the lead 4,
Separate them one by one from the lead frame as a package. As a result, a surface mount type package having a QFN structure is completed. After this completion, a test is performed to select non-defective / defective packages, and non-defective packages are used as products.

Therefore, according to the semiconductor device of the present embodiment, by using the lower mold 11 having a structure in which the lower surface side of the tab 1 is formed in a convex shape, the thickness of the solder plating 6 becomes convex. In addition to the height dimension, the stand-off margin can be sufficiently secured, and the lead 4 and the lower mold 1 can be secured.
Since the distance and gap between the first die 1 and the upper die 12 can be reduced, it is possible to prevent the sealing material 5 from wrapping around the lower surface of the lead 4. Further, since the distance between the tab 1 and the lower mold 11 is reduced, it is possible to prevent the tab 1 from vertically moving when the sealing material 5 is injected.

As a result, it is expected that the yield of the semiconductor device can be improved by reducing the leakage of the sealing material 5. This leads to an improvement in the reliability of the semiconductor device. That is, since the sealing material 5 adheres to the lead 4 joined to the mounting substrate, there is a problem in that the joint area of the solder plating 6 is reduced, and it becomes difficult to secure the shear strength. Can solve this problem.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, the package structure in which the sealing material goes around the lower surface of the tab has been described. However, a structure in which the tab is exposed may be employed. In this case, by forming the height of the convex portion of the lower mold so as to be in contact with the lower surface of the tab, the lower surface of the tab is in contact with the convex portion of the mold in the sealing step. The vertical deformation of the tab can be eliminated and the deformation of the tab can be prevented. Further, heat can be directly radiated from the tab to the outside to improve the heat radiation of the package.

Although the surface mount type package having the QFN structure has been described, the present invention is not limited to this.
The present invention can also be applied to a package having a similar structure in which tabs, semiconductor chips, wires, and leads are sealed so that the lower surfaces of the leads are exposed.

[0031]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) When encapsulating with a sealing material, the portion into which the lead is fitted is formed in a concave shape, and the portion on the lower surface side of the tab includes a lower mold having a convex shape. By sealing with a mold, the thickness direction of each lead can be exposed with a predetermined dimension, so that a sufficient stand-off margin between the lower surface of the package and the mounting board can be secured. Becomes

(2) The convex portion on the lower surface side of the tab, except for the portion where the lead is fitted, is formed in a convex shape within the range sealed with the sealing material, so that the lower surface side of the lead is formed. Of the sealing material can be prevented.

(3) By setting the height of the convex portion on the lower surface side of the tab based on the thickness of the lead, it is possible to cope with the processing in the thickness direction of the tab and the lead.

(4) According to the above (1), the distance between the tab and the lower mold can be reduced, so that it is possible to prevent the tab from moving up and down when the sealing material is injected.

(5) According to the above (1) to (4), it is possible to secure the stand-off, reduce the leakage of the sealing material to the lead terminal portion, etc., and improve the yield of the substrate mountability by preventing the tab from changing. As a result, the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 shows a semiconductor device according to an embodiment of the present invention;
It is a flowchart which shows an assembling method.

FIG. 3 illustrates a semiconductor device according to an embodiment of the present invention;
It is a top view which shows a sealing mold (lower mold).

FIGS. 4A and 4B are cross-sectional views showing a sealing mold in a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a sectional view showing a semiconductor device which is a premise of the present invention.

FIG. 6 is a cross-sectional view showing a sealing mold in a semiconductor device which is a premise of the present invention.

[Explanation of symbols]

 Reference Signs List 1 tab 2 semiconductor chip 3 wire 4 lead 5 sealing material 6 solder plating 7 pad 11 lower mold 12 upper mold 13 cavity

Claims (4)

[Claims] A semiconductor chip mounted on a tab, a plurality of leads electrically connected to pads on the semiconductor chip via wires, and a lower surface of the plurality of leads being exposed. A surface mounting type semiconductor device comprising a tab, the semiconductor chip, the wires, and a sealing material for sealing the plurality of leads, wherein the plurality of leads exposed from the sealing material are each of the leads. A thickness direction of the semiconductor device is exposed at a predetermined dimension. 2. A semiconductor chip mounted on a tab, a plurality of leads electrically connected to pads on the semiconductor chip via wires, and a lower surface of the plurality of leads is exposed. A method for manufacturing a surface-mount type semiconductor device, comprising: a tab, the semiconductor chip, the wire, and a sealing material for sealing the plurality of leads, wherein the sealing is performed by the sealing material. The portion to be fitted is formed in a concave shape, and the portion on the lower surface side of the tab is sealed with a mold including a lower mold having a structure formed in a convex shape. A method for manufacturing a semiconductor device, comprising securing a standoff margin. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a convex portion on a lower surface side of the tab is sealed with the sealing material except for a portion where the lead is fitted. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed in a convex shape within a range, and prevents the encapsulant from flowing to the lower surface side of the lead. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a height of a convex portion on a lower surface side of said tab is set based on a thickness of said lead, and said tab and said lead are formed. A method of manufacturing a semiconductor device, the method being adapted for processing in a thickness direction of a semiconductor device.