KR100370480B1 - Lead frame for semiconductor package - Google Patents
Lead frame for semiconductor package Download PDFInfo
- Publication number
- KR100370480B1 KR100370480B1 KR10-2000-0045486A KR20000045486A KR100370480B1 KR 100370480 B1 KR100370480 B1 KR 100370480B1 KR 20000045486 A KR20000045486 A KR 20000045486A KR 100370480 B1 KR100370480 B1 KR 100370480B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead frame
- paddle
- semiconductor chip
- lead
- tie
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 반도체 패키지용 리드 프레임을 개시한다. 개시된 본 발명은, 리드 프레임은 밑면에 반도체 칩이 접착되는 중앙의 패들과, 패들의 모서리로부터 하부를 향해 경사지게 연장된 타이-바, 및 타이-바에 연결되어 패들과 수평을 이루면서 반도체 칩의 본드 패드와 전기적으로 연결되는 리드를 포함한다. 리드는 패들보다 하부에 배치되어서, 타이-바는 경사지게 배치된다. 또한, 리드의 밑면이 절반 정도의 두께가 부분 식각되어 돌출부가 형성된다.The present invention discloses a lead frame for a semiconductor package. According to the present invention, a lead frame includes a center paddle to which a semiconductor chip is adhered to a bottom surface, a tie-bar extending obliquely downward from an edge of the paddle, and a bond pad of the semiconductor chip connected to the tie-bar and being horizontal with the paddle. And a lead electrically connected with the lead. The leads are placed below the paddles so that the tie-bars are inclined. In addition, the bottom surface of the lid is about half the thickness is partially etched to form a protrusion.
Description
본 발명은 반도체 패키지의 리드 프레임에 관한 것으로서, 보다 구체적으로는 패키지가 실장되는 보드와 반도체 칩간의 전기적 연결 매개체인 리드 프레임에 관한 것이다.The present invention relates to a lead frame of a semiconductor package, and more particularly, to a lead frame which is an electrical connection medium between a board on which a package is mounted and a semiconductor chip.
웨이퍼에 각종 공정에 의해 복수개의 반도체 칩이 구성되면, 스크라이브 라인을 따라 웨이퍼를 절단하여 개개의 반도체 칩으로 분리하게 된다. 분리된 개개의 반도체 칩에 대해서 보드 실장을 위한 패키징 공정이 실시된다. 패키징 공정중 최종적으로 실시되는 단계는 보드에 전기적으로 접속되는 외부 접속 단자를 형성하는 것인데, 현재에는 주로 외부 접속 단자로서 솔더 볼이 이용되고 있고, 이러한 솔더 볼을 갖는 패키지를 볼 그리드 어레이 패키지라 한다.When a plurality of semiconductor chips are formed on the wafer by various processes, the wafer is cut along the scribe line and separated into individual semiconductor chips. The packaging process for board-mounting is performed for each separated semiconductor chip. The final step in the packaging process is to form external connection terminals that are electrically connected to the board. Currently, solder balls are mainly used as external connection terminals, and a package having such solder balls is called a ball grid array package. .
도 1에 종래의 볼 그리드 어레이 패키지가 단면도로 도시되어 있다. 도시된 바와 같이, 리드 프레임(2) 표면에 반도체 칩(1)이 접착제(6)를 매개로 접착되어 있다. 반도체 칩(1)의 표면에 배치된 본드 패드가 금속 와이어(3)를 매개로 리드 프레임(2)의 양측 표면과 전기적으로 연결되어 있다. 한편, 리드 프레임(2)의 양측 밑면에는 돌출부(2a)가 형성되어 있는데, 이 돌출부(2a)는 리드 프레임(2)의 밑면을 절반 정도 부분 식각하는 것에 의해 형성된다. 돌출부(2a)의 밑면만이 노출되도록, 전체 결과물이 봉지제(4)로 봉지되어 있다. 노출된 돌출부(2a)의 밑면, 즉 볼 랜드에 솔더 볼(5)이 마운트되어 있다.A conventional ball grid array package is shown in cross section in FIG. As shown, the semiconductor chip 1 is adhere | attached on the surface of the lead frame 2 via the adhesive agent 6. Bond pads disposed on the surface of the semiconductor chip 1 are electrically connected to both surfaces of the lead frame 2 via metal wires 3. On the other hand, protrusions 2a are formed on both bottom surfaces of the lead frame 2, which are formed by partially etching the bottom surface of the lead frame 2 about halfway. The entire resultant is sealed with the encapsulant 4 so that only the underside of the projection 2a is exposed. The solder ball 5 is mounted on the bottom surface of the exposed protrusion 2a, that is, the ball land.
그러나, 종래의 볼 그리드 어레이 패키지는 리드 프레임의 중앙부와 양측부가 동일 평면상에 위치하고 있고, 반도체 칩은 리드 프레임의 중앙부에 배치되기 때문에, 와이어 본딩시 금속 와이어가 반도체 칩의 표면보다 돌출될 수 밖에 없다. 이런 이유로 인해서, 와이어 본딩 영역을 봉지하는 봉지제도 반도체 칩의 표면보다 돌출된 금속 와이어 부분보다 더 돌출되어야 하므로, 패키지의 전체 두께를 1㎜ 이하로 줄이는데 한계가 있었다.However, in the conventional ball grid array package, since the center portion and both sides of the lead frame are located on the same plane, and the semiconductor chip is disposed at the center portion of the lead frame, the metal wires may protrude more than the surface of the semiconductor chip during wire bonding. none. For this reason, since the encapsulation that encapsulates the wire bonding area must also protrude more than the protruding metal wire portion than the surface of the semiconductor chip, there is a limit to reducing the overall thickness of the package to 1 mm or less.
따라서, 본 발명은 종래의 리드 프레임이 안고 있는 한계를 극복하기 위해 안출된 것으로서, 금속 와이어가 리드 프레임이나 반도체 칩의 면보다 돌출되지 않도록 하므로써, 패키지의 두께를 리드 프레임과 반도체 칩의 각 두께를 합산한 두께 이내로 줄일 수 있는 반도체 패키지용 리드 프레임을 제공하는데 목적이 있다.Accordingly, the present invention is devised to overcome the limitations of the conventional lead frame, and the thickness of the package is added to the thickness of the lead frame and the semiconductor chip by preventing the metal wire from protruding from the surface of the lead frame or the semiconductor chip. An object of the present invention is to provide a lead frame for a semiconductor package that can be reduced to less than one thickness.
도 1은 종래 기술에 따른 리드 프레임을 갖는 볼 그리드 어레이 패키지를 나타낸 단면도.1 is a cross-sectional view of a ball grid array package having a lead frame according to the prior art.
도 2 내지 도 6은 본 발명에 따른 리드 프레임을 갖는 볼 그리드 어레이 패키지를 제조 공정 순서대로 나타낸 도면.2 to 6 show a ball grid array package having a lead frame according to the present invention in the order of manufacturing process.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 ; 반도체 칩 20 ; 리드 프레임10; Semiconductor chip 20; Lead frame
21 ; 패들 22 ; 리드21; Paddle 22; lead
23 ; 돌출부 24 ; 타이-바23; Protrusion 24; Tie-Bar
40 ; 금속 와이어 50 ; 봉지제40; Metal wire 50; Encapsulant
60 ; 솔더 볼60; Solder ball
상기와 같은 목적을 달성하기 위해, 본 발명에 따른 리드 프레임은 다음과 같은 구성으로 이루어진다.In order to achieve the above object, the lead frame according to the present invention has the following configuration.
리드 프레임은 밑면에 반도체 칩이 접착되는 중앙의 패들과, 패들의 모서리로부터 하부를 향해 경사지게 연장된 타이-바(tie-bar), 및 타이-바에 연결되어 패들과 수평을 이루면서 반도체 칩의 본드 패드와 전기적으로 연결되는 리드를 포함한다. 리드는 패들보다 하부에 배치되어서, 타이-바는 경사지게 배치된다. 또한, 리드의 밑면이 절반 정도의 두께가 부분 식각되어 돌출부가 형성된다.The lead frame has a center paddle to which the semiconductor chip is attached to the bottom surface, a tie-bar extending obliquely downward from the edge of the paddle, and a bond pad of the semiconductor chip connected to the tie-bar to be parallel to the paddle. And a lead electrically connected with the lead. The leads are placed below the paddles so that the tie-bars are inclined. In addition, the bottom surface of the lid is about half the thickness is partially etched to form a protrusion.
상기된 본 발명의 구성에 의하면, 리드 프레임의 패들보다 그의 리드가 하부에 배치되므로써, 금속 와이어가 리드 프레임의 패들 표면보다 돌출되지 않게 된다. 따라서, 와이어 본딩 영역을 봉지하는 봉지제도 패들의 표면보다 돌출되지 않게 되어, 패키지의 전체 두께가 줄어들게 된다.According to the configuration of the present invention described above, since the lead thereof is disposed below the paddle of the lead frame, the metal wire does not protrude beyond the paddle surface of the lead frame. Thus, the encapsulation sealing the wire bonding area also does not protrude beyond the surface of the paddle, reducing the overall thickness of the package.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
도 2 내지 도 6은 본 발명에 따른 리드 프레임을 이용해서 볼 그리드 어레이 패키지를 제조하는 공정을 나타낸 도면이다.2 to 6 is a view showing a process for manufacturing a ball grid array package using a lead frame according to the present invention.
먼저, 단면도인 도 2와 평면도인 도 3에 도시된 리드 프레임(20)을 준비한다. 리드 프레임(20)은 중앙의 패들(21)과, 이 패들(21)의 네 모서리로부터 연장된 타이-바(24), 및 각 타이-바(24)의 단부에 연결된 리드(22)를 포함한다. 리드(22)의 밑면은 그의 절반 두께가 부분 식각되어 돌출부(23)가 형성된다. 후술되겠지만, 돌출부(23)의 밑면이 솔더 볼이 마운트되는 볼 랜드가 된다. 특히, 평행을 이루는 패들(21)과 리드(22)는 동일 평면상에 위치하는 것이 아니라, 타이-바(24)가 다운셋(downset)되어 패들(21)보다 하부에 위치하게 된다.First, the lead frame 20 shown in FIG. 2 which is sectional drawing and FIG. 3 which is a top view is prepared. The lead frame 20 includes a central paddle 21, tie-bars 24 extending from the four corners of the paddles 21, and leads 22 connected to the ends of each tie-bar 24. do. The bottom surface of the lid 22 is partially etched to form a protrusion 23. As will be described later, the bottom surface of the protrusion 23 is a ball land on which solder balls are mounted. In particular, the parallel paddle 21 and the lid 22 are not located on the same plane, but the tie-bar 24 is downset and positioned below the paddle 21.
이어서, 단면도인 도 4와 평면도인 도 5와 같이, 본드 패드가 외곽을 따라 배치된 반도체 칩(10)의 표면을 패들(21)의 밑면에 접착제(30)를 매개로 접착한다. 그러면, 각 본드 패드가 패들(21)의 외곽을 통해서 위로 노출된다. 이때, 반도체 칩(10)은 네 방향에 위치한 리드(22)가 이루는 내부 공간내에 수용되어서, 그의 밑면은 리드(22)의 밑면, 즉 돌출부(23)의 밑면과 동일 평면을 이루거나 적어도 하부로는 돌출되지 않는다.Subsequently, as shown in FIG. 4 and a plan view of FIG. 5, the surface of the semiconductor chip 10, in which the bond pads are disposed along the periphery, is adhered to the bottom surface of the paddle 21 via an adhesive 30. Each bond pad is then exposed upward through the periphery of the paddle 21. At this time, the semiconductor chip 10 is accommodated in the internal space formed by the leads 22 located in four directions, so that the bottom thereof is coplanar with or at least downwardly formed from the bottom of the lead 22, that is, the bottom of the protrusion 23. Does not protrude.
그런 다음, 노출된 본드 패드와 리드(22)의 표면을 금속 와이어(40)를 매개로 전기적으로 연결한다. 이때, 금속 와이어(40)는 패들(21)과 리드(22)간의 단차진 영역내에 위치하게 되므로, 금속 와이어(40)가 패들(21)의 표면보다 적어도 위로 노출되지 않게 된다.Then, the exposed bond pad and the surface of the lead 22 is electrically connected through the metal wire 40. At this time, since the metal wire 40 is located in the stepped region between the paddle 21 and the lead 22, the metal wire 40 is not exposed at least above the surface of the paddle 21.
이어서, 트랜스퍼 몰딩 공정을 실시하여, 돌출부(23)의 밑면만이 노출되도록 전체 결과물을 봉지제(50)로 봉지한다. 이때, 도 5에서는 돌출부(23)의 밑면 뿐만이 아니라 패들(21)의 표면과 반도체 칩(10)의 밑면도 봉지제(50)로부터 노출된 구조를 도시하고 있다. 그 이유는, 반도체 칩(10)과 리드 프레임(20)으로부터 발생되는 고열이 외부로 신속하게 발산되도록 하기 위함이다.Subsequently, the transfer molding process is performed to encapsulate the entire resultant with the encapsulant 50 so that only the underside of the protrusion 23 is exposed. 5 illustrates a structure in which not only the bottom of the protrusion 23, but also the surface of the paddle 21 and the bottom of the semiconductor chip 10 are exposed from the encapsulant 50. The reason is that the high heat generated from the semiconductor chip 10 and the lead frame 20 is quickly dissipated to the outside.
그런 다음, 봉지제(50)로부터 노출된 돌출부(23)의 밑면, 즉 볼 랜드에 솔더 볼(60)을 마운트한 후, 마지막으로 스크라이브 라인을 따라 웨이퍼를 절단하여 개개의 반도체 칩(10)으로 분리하면, 도 6에 도시된 본 실시예에 따른 리드 프레임(20)을 갖는 볼 그리드 어레이 패키지가 완성된다.Then, the solder ball 60 is mounted on the bottom surface of the protrusion 23 exposed from the encapsulant 50, that is, the ball land, and finally, the wafer is cut along the scribe line to the individual semiconductor chips 10. When separated, the ball grid array package having the lead frame 20 according to the present embodiment shown in FIG. 6 is completed.
한편, 리드 프레임(20)의 표면 전체에는 은, 니켈/팔라듐, 금, 또는 구리 산화막이 도금되는 것이 바람직하다.On the other hand, it is preferable that silver, nickel / palladium, gold, or a copper oxide film is plated on the entire surface of the lead frame 20.
이상에서 설명한 바와 같이 본 발명에 의하면, 리드 프레임의 패들보다 리드가 하부에 배치되므로써, 금속 와이어가 패들의 표면보다 돌출되지 않게 된다. 그러므로, 와이어 본딩 영역을 봉지하는 봉지제의 표면이 패들의 표면보다는 돌출되지 않게 되어, 패키지의 전체 두께를 0.8㎜ 이하로 줄일 수가 있게 된다.As described above, according to the present invention, since the lead is disposed below the paddle of the lead frame, the metal wire does not protrude beyond the surface of the paddle. Therefore, the surface of the encapsulant encapsulating the wire bonding area does not protrude more than the surface of the paddle, so that the overall thickness of the package can be reduced to 0.8 mm or less.
이상에서는 본 발명에 의한 리드 프레임을 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.In the above, although the preferred embodiment for implementing the lead frame according to the present invention has been illustrated and described, the present invention is not limited to the above-described embodiment, and the present invention is not limited to the scope of the present invention as claimed in the following claims. Anyone of ordinary skill in the art to which the invention pertains may make various changes.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0045486A KR100370480B1 (en) | 2000-08-05 | 2000-08-05 | Lead frame for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0045486A KR100370480B1 (en) | 2000-08-05 | 2000-08-05 | Lead frame for semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020012059A KR20020012059A (en) | 2002-02-15 |
| KR100370480B1 true KR100370480B1 (en) | 2003-01-29 |
Family
ID=19681926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0045486A KR100370480B1 (en) | 2000-08-05 | 2000-08-05 | Lead frame for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100370480B1 (en) |
-
2000
- 2000-08-05 KR KR10-2000-0045486A patent/KR100370480B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020012059A (en) | 2002-02-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7274088B2 (en) | Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof | |
| KR100260997B1 (en) | Semiconductor package | |
| US6590281B2 (en) | Crack-preventive semiconductor package | |
| US7728414B2 (en) | Lead frame and resin-encapsulated semiconductor device | |
| JP3420057B2 (en) | Resin-sealed semiconductor device | |
| US8093694B2 (en) | Method of manufacturing non-leaded integrated circuit package system having etched differential height lead structures | |
| US7115441B2 (en) | Semiconductor package with semiconductor chips stacked therein and method of making the package | |
| US7436049B2 (en) | Lead frame, semiconductor chip package using the lead frame, and method of manufacturing the semiconductor chip package | |
| KR100369907B1 (en) | Semiconductor Package And Mounting Structure On Substrate Thereof And Stack Structure Thereof | |
| KR19990024255U (en) | Stacked Ball Grid Array Package | |
| KR100370480B1 (en) | Lead frame for semiconductor package | |
| KR100345163B1 (en) | Ball grid array package | |
| KR100258607B1 (en) | Chip scale semiconductor package of lead on chip type and method for manufacturing the same | |
| KR100247641B1 (en) | Package and method of manufacturing the same | |
| KR100379092B1 (en) | semiconductor package and its manufacturing method | |
| KR100575859B1 (en) | ball grid array package | |
| KR20030055834A (en) | Ball grid array type semiconductor chip package using leadframe and stack package | |
| JP3082562U (en) | Multi-chip package | |
| KR20000006787U (en) | Multi-chip package | |
| KR100290783B1 (en) | Semiconductor package | |
| KR100557976B1 (en) | Land grid array package and manufacturing method thereof | |
| KR100876876B1 (en) | Chip stack package | |
| KR20060005717A (en) | Multi chip package | |
| US20030037947A1 (en) | Chip scale package with a small surface mounting area | |
| KR20020044988A (en) | chip scale package and method for fabricating the same in wafer level |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130117 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20140116 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20150121 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20160108 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20170111 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20180105 Year of fee payment: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20190108 Year of fee payment: 17 |
|
| FPAY | Annual fee payment |
Payment date: 20200108 Year of fee payment: 18 |