KR20020044988A - chip scale package and method for fabricating the same in wafer level - Google Patents
chip scale package and method for fabricating the same in wafer level Download PDFInfo
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- KR20020044988A KR20020044988A KR1020000074259A KR20000074259A KR20020044988A KR 20020044988 A KR20020044988 A KR 20020044988A KR 1020000074259 A KR1020000074259 A KR 1020000074259A KR 20000074259 A KR20000074259 A KR 20000074259A KR 20020044988 A KR20020044988 A KR 20020044988A
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- scale package
- center pad
- heat sink
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
본 발명은 칩스케일 패키지 및 웨이퍼 레벨에서의 칩 스케일 패키지 제조방법에 관한 것으로서, 더욱 상세하게는 칩스케일의 패키지 제조에 신뢰성이 높은 와이어 본딩 방식을 이용하는 한편, 열방출이 용이하게 이루어지도록 하며 웨이퍼 레벨에서의 제조가 가능한 새로운 구조의 칩스케일 패키지를 제공하기 위한 것이다.The present invention relates to a chip scale package and a method of manufacturing a chip scale package at a wafer level, and more particularly, to use a highly reliable wire bonding method for manufacturing a chip scale package, and to facilitate heat dissipation and wafer level. To provide a chip-scale package of a new structure that can be manufactured in.
일반적으로, 칩스케일 패키지의 일종인 마이크로 비·지·에이(μ-BGA)는 도 1에 나타낸 바와 같이, 서키트 필름(4)과, 상기 서키트 필름(4)에 부착되는 칩(1)과, 칩(1)과 서키트 필름(4)사이에 개재되어 칩(1)이 서키트 필름(4)에 부착되도록 하는 접착테이프(3)와, 상기 칩(1)의 외부접속단자인 본딩패드(2)와 서키트 필름(4)의 회로패턴을 전기적으로 연결하는 리드(5)와, 상기 칩(1)의 측면 및 리드(5)를 감싸는 몰드바디(7)와, 상기 서키트 필름(4)의 칩 부착면 반대쪽에 부착되는 솔더볼(8)을 포함하여 구성된다.In general, as shown in FIG. 1, a micro B-GA (micro-BGA), which is a type of chip scale package, includes a circuit film 4, a chip 1 attached to the circuit film 4, and An adhesive tape 3 interposed between the chip 1 and the circuit film 4 to attach the chip 1 to the circuit film 4, and a bonding pad 2, which is an external connection terminal of the chip 1. And a lead 5 electrically connecting the circuit pattern of the circuit film 4, a mold body 7 surrounding the side of the chip 1 and the lead 5, and a chip of the circuit film 4. It comprises a solder ball (8) attached to the opposite side of the face.
한편, 이와 같이 구성된 마이크로 비·지·에이의 제조 과정은 다음과 같다.In addition, the manufacturing process of the micro BG comprised in this way is as follows.
먼저, 칩(1)에 접착테이프(3)를 붙이고, 상기 접착테이프(3) 위로 서키트 필름(4)을 올린 뒤, 리드 본드 툴(도시는 생략함)을 이용하여 칩(1)의 본딩패드(2)와 서키트 필름(4)의 회로패턴이 전기적으로 연결되도록 리드 본딩을 실시한다.First, the adhesive tape 3 is attached to the chip 1, the circuit film 4 is placed on the adhesive tape 3, and then a bonding pad of the chip 1 is formed using a lead bond tool (not shown). Lead bonding is performed so that the circuit pattern of (2) and the circuit film 4 is electrically connected.
그 다음, 봉지제로 리드(5) 및 칩(1) 측면을 봉지하여 몰드바디(7)를 형성하므로써 칩(1)의 회로형성면이 보호되도록 한다.Then, the lead body 5 and the side of the chip 1 are sealed with an encapsulant to form the mold body 7 so that the circuit formation surface of the chip 1 is protected.
그러나, 이와 같은 종래의 마이크로 비·지·에이는 히트싱크등 방열구조를 갖추고 있지 않아 열방출 성능이 미약한 단점이 있었다.However, such a conventional micro B, G, A does not have a heat dissipation structure such as a heat sink, and thus has a weak heat dissipation performance.
따라서, 미약한 열방출 성능으로 인해 고전압에서의 구동시 칩이 오동작(fail)을 일으키게 되는 등의 문제점이 있었다.Therefore, there is a problem that the chip malfunctions when driving at high voltage due to the weak heat dissipation performance.
또한, 리드본딩을 하므로 인해 공정이 까다롭고, 웨이퍼 레벨에서의 제조가 곤란한등 많은 문제점이 있었다.In addition, due to the lead bonding, the process is difficult, there are many problems such as difficult to manufacture at the wafer level.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 신뢰성이 높은 와이어 본딩 방식을 이용하여 제조하는 한편, 열방출이 용이하게 이루어지도록 한 새로운 구조의 칩스케일 패키지 및, 상기 칩스케일 패키지를 웨이퍼 레벨에서 제조하는 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention is to solve the above-mentioned problems, and is manufactured using a highly reliable wire bonding method, and a chip scale package having a new structure to facilitate heat dissipation, and the chip scale package at a wafer level. Its purpose is to provide a method of preparation.
도 1은 종래의 마이크로 비·지·에이 구조를 나타낸 종단면도1 is a longitudinal cross-sectional view showing a conventional micro BG-A structure
도 2는 본 발명에 따른 칩스케일 패키지 구조를 나타낸 종단면도로서, 기판에 실장된 상태를 나타낸 종단면도Figure 2 is a longitudinal sectional view showing a chip scale package structure according to the present invention, a longitudinal sectional view showing a state mounted on a substrate
도 3a 내지 도 3f는 본 발명에 따른 칩스케일 패키지 제조 과정을 나타낸 것으로서,3A to 3F illustrate a process of manufacturing a chip scale package according to the present invention.
도 3a는 웨이퍼 평면도3A is a wafer top view
도 3b는 웨이퍼와 동일한 패턴을 가진 히트싱크 평면도3b is a heatsink top view with the same pattern as the wafer
도 3c는 웨이퍼 뒷면에 히트싱크가 부착된 상태를 나타낸 종단면도Figure 3c is a longitudinal sectional view showing a state in which a heat sink is attached to the back of the wafer
도 3d는 리드 어태치 및 와이어 본딩 완료후의 상태를 나타낸 종단면도3D is a longitudinal cross-sectional view illustrating a state after completion of lead attach and wire bonding;
도 3e는 엔캡슐레이션 완료 후의 상태를 나타낸 종단면도3E is a longitudinal sectional view showing a state after completion of encapsulation;
도 3f는 소잉 완료후의 상태를 나타낸 종단면도3F is a longitudinal sectional view showing a state after completion of sawing;
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:칩 1a:센터패드1: Chip 1a: Center Pad
2:본딩패드 3:접착테이프2: Bonding pad 3: Adhesive tape
4:서키트 필름 5:리드4: Circuit film 5: Lead
6:LOC 테이프 7:몰드바디6: LOC tape 7: Molded body
8:솔더볼 10:히트싱크8: Solder Ball 10: Heatsink
9:와이어 11:비전도성 열접착 테이프9: wire 11: non-conductive thermal adhesive tape
12:기판 W:웨이퍼12: Board W: Wafer
상기한 목적을 달성하기 위해, 본 발명은 히트싱크와, 상기 히트싱크 일면에 부착되는 센터패드 타입의 칩과, 상기 칩 상면의 본딩패드 양측에 부착되는 LOC 테이프와, 상기 LOC 테이프 상에 부착되는 다운-셋 구조의 리드와, 상기 칩의 본딩패드와 리드를 전기적으로 연결하는 와이어와, 상기 리드의 선단면만이 노출되도록하면서 리드와 와이어 및 칩의 상면을 봉지하는 몰드바디를 포함하여서 됨을 특징으로 하는 칩스케일 패키지가 제공된다.In order to achieve the above object, the present invention provides a heat sink, a center pad type chip attached to one surface of the heat sink, a LOC tape attached to both sides of a bonding pad of the chip upper surface, and attached to the LOC tape. A lead having a down-set structure, a wire electrically connecting the bonding pad and the lead of the chip, and a mold body encapsulating the lead, the wire, and the top surface of the chip while exposing only the front end surface of the lead. A chip scale package is provided.
한편, 상기한 목적을 달성하기 위한 본 발명의 다른 형태는, 웨이퍼 뒷면에 상기 웨이퍼 전면의 칩패턴과 동일한 패턴을 갖는 히트싱크를 부착하는 단계와, 상기 웨이퍼상에 구비되는 단위칩의 센터패드 양측에 LOC 테이프를 부착하는 단계와, 상기 LOC 테이프 상에 다운-셋된 리드를 부착하는 단계와, 칩의 센터패드와 상기 리드를 와이어 본딩하여 전기적으로 연결하는 단계와, 상기 리드의 선단부만이 노출되도록 하면서 리드와 와이어 및 칩의 상면을 봉지하는 단계와, 소잉하여 단위 유니트별로 분리하는 단계를 포함하여서 됨을 특징으로 하는 웨이퍼 레벨에서의 칩스케일 패키지 제조방법이 제공된다.On the other hand, another aspect of the present invention for achieving the above object, the step of attaching a heat sink having the same pattern as the chip pattern on the front surface of the wafer on the back of the wafer, both sides of the center pad of the unit chip provided on the wafer Attaching a LOC tape to the substrate, attaching a down-set lead on the LOC tape, electrically bonding a center pad of the chip and the lead by wire bonding, and exposing only the tip of the lead While encapsulating the upper surface of the lead, the wire and the chip, and sawing and separating the unit by unit unit is provided a chip scale package manufacturing method at a wafer level.
이하, 본 발명의 일실시예를 첨부도면 도 2와, 도 3a 내지 도 3g를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3A to 3G.
도 2는 본 발명에 따른 칩 스케일 패키지 구조를 나타낸 종단면도로서, 히트싱크(10)와, 상기 히트싱크(10) 일면에 부착되는 센터패드(1a) 타입의 칩(1)과, 상기 칩(1) 상면의 센터패드(1a) 양측에 부착되는 LOC 테이프(Lead On Chip tape)(6)와, 상기 LOC 테이프(6) 상에 부착되는 다운-셋(down-set) 구조의 리드(5)와, 상기 칩(1)의 센터패드(1a)와 리드(5)를 전기적으로 연결하는 와이어(9)와, 상기 리드(5)의 선단면만이 노출되도록 하면서 리드(5)와 와이어(9) 및 칩(1)의 상면을 봉지하는 몰드바디(7)를 포함하여서 구성된다.2 is a longitudinal cross-sectional view showing a chip scale package structure according to the present invention, a heat sink 10, a chip 1 of a center pad type 1a attached to one surface of the heat sink 10, and the chip ( 1) a lead on chip tape (6) attached to both sides of the center pad (1a) on the upper surface, and a lead (5) having a down-set structure attached to the LOC tape (6). And a wire 9 electrically connecting the center pad 1a and the lead 5 of the chip 1 to the lead 5 and the wire 9 while only the front end surface of the lead 5 is exposed. And a mold body 7 for sealing the upper surface of the chip 1.
이 때, 상기 히트싱크(10)와 칩(1)의 뒷면 사이에는 비전도성 열접착테이프(11)가 개재된다.At this time, a non-conductive thermal adhesive tape 11 is interposed between the heat sink 10 and the back surface of the chip 1.
한편, 상기 히트싱크(10)는 열전도성이 우수한 구리등의 메탈 재질로서, 웨이퍼(W)의 형상을 따라 원판형으로 제작되거나, 이와는 달리 사각판형으로 제작되어도 무방하다.On the other hand, the heat sink 10 is a metal material such as copper having excellent thermal conductivity, and may be manufactured in a disk shape along the shape of the wafer W, or alternatively, may be manufactured in a square plate shape.
또한, 상기 히트싱크(10)의 칩부착면 반대쪽에는 방열 면적의 증대를 위해 요철이 형성될 수 있음은 물론이다.In addition, irregularities may be formed on the opposite side of the chip attaching surface of the heat sink 10 to increase the heat dissipation area.
이와 같이 구성된 본 발명의 웨이퍼 레벨 칩스케일 패키지 제조 과정은 다음과 같다.The wafer level chip scale package manufacturing process of the present invention configured as described above is as follows.
먼저, 일괄 제조 공정(FAB 공정)이 완료된 웨이퍼(W)(도 3a 참조) 뒷면에 열전도도가 우수한 구리 재질의 히트싱크(10)(도 3b 참조)를 도 3c에서와 같이 접착시킨다.First, a copper heat sink 10 (see FIG. 3B) having excellent thermal conductivity is bonded to the back side of the wafer W (see FIG. 3A) where the batch fabrication process (FAB process) is completed, as shown in FIG. 3C.
이때, 히트싱크(10) 윗면에는 웨이퍼(W)와의 접착이 용이하도록 비전도성 열압착 테이프(11)가 부착되어 있으며, 상기 히트싱크(10)는 원판형 또는 사각판형을 이룬다.At this time, the non-conductive thermocompression tape 11 is attached to the top surface of the heat sink 10 to facilitate adhesion with the wafer W, and the heat sink 10 has a disc shape or a square plate shape.
한편, 웨이퍼(W)와 히트싱크(10)의 접착 후에는, LOC 테이프(6)를 웨이퍼(W) 상에 형성된 단위 칩(1)의 센터패드(1a) 양측에 부착한다.On the other hand, after bonding the wafer W and the heat sink 10, the LOC tape 6 is attached to both sides of the center pad 1a of the unit chip 1 formed on the wafer W. As shown in FIG.
이어, 상기 LOC 테이프(6)에는 다운-셋된 리드(5)를 부착한다.(도 3d 참조)Subsequently, the LOC tape 6 is attached with a down-set lead 5 (see FIG. 3D).
이 때, 상기 LOC 테이프(6)는 리드(5)에 미리 부착되어 있을 수도 있음은 물론이며, 리드(5)의 수 및 디자인은 디바이스에 따라 결정된다.At this time, the LOC tape 6 may be attached to the lead 5 in advance, as well as the number and design of the leads 5 are determined by the device.
한편, 단위 칩(1) 상면에 리드(5)를 부착한 후에는 센터패드(1a)와 리드(5)의 다운-셋된 영역을 와이어(9)로 본딩하여 칩(1)과 리드(5)를 전기적으로 연결한다.(도 3d 참조)On the other hand, after the lead 5 is attached to the upper surface of the unit chip 1, the center pad 1a and the down-set areas of the lead 5 are bonded with the wire 9 to bond the chip 1 and the lead 5 to each other. Is electrically connected (see FIG. 3D).
이어, 외부충격으로부터 와이어(9)를 보호하기 위해 봉지제로 봉지하여 몰드바디(7)를 형성하게 된다.(도 3e참조)Subsequently, in order to protect the wire 9 from external impact, the encapsulant is encapsulated to form a mold body 7 (see FIG. 3E).
상기 몰드바디(7) 형성 방법으로는 디스펜싱 방식 또는 프린팅 방식이 모두 적용 가능하다.As the method of forming the mold body 7, both a dispensing method or a printing method may be applied.
한편, 몰드바디(7) 형성 후에는 히트싱크(10)가 부착된 웨이퍼(W)를 호일(foil) 마운팅한 다음, 소잉 휠(도시는 생략함)을 이용하여 분리선을 따라 소잉하여 개개의 유니트로 분리하게 된다.(도 3f참조)On the other hand, after the mold body 7 is formed, the wafer W to which the heat sink 10 is attached is foil-mounted, and then sawed along a separation line using a sawing wheel (not shown) to separate units. (See Fig. 3f).
이와 같이 완성된 본 발명의 패키지는 도 2에 나타낸 바와 같이, 솔더를 매개로 기판(12)상에 실장된다.The package of the present invention thus completed is mounted on the substrate 12 via solder, as shown in FIG.
이상에서와 같이, 본 발명은 와이어 본딩 방식을 이용하는 한편, 열방출이 용이하게 이루어지도록 한 새로운 구조의 신뢰성 높은 칩스케일 패키지를 제공하는 한편, 이러한 새로운 구조의 칩스케일의 패키지를 웨이퍼 레벨에서 제조 가능하도록 한 것이다.As described above, the present invention provides a reliable chip-scale package with a new structure that facilitates heat dissipation while using a wire bonding method, and can manufacture a chip-scale package with this new structure at the wafer level. I did it.
즉, 본 발명은 웨이퍼 스케일에서 제조되므로 실제적인 칩 사이즈로의 제조가 가능하고, 마이크로 비·지·에이에서 행하던 리드본딩 공정 대신 신뢰성 높은 와이어 본딩 공정을 사용하므로 인해 제조공정의 신뢰성을 향상시킬 수 있으며, 히트싱크가 구비됨으로 인해 열방출 성능을 극대화 할 수 있게 된다.That is, since the present invention is manufactured at the wafer scale, it is possible to manufacture the actual chip size, and the reliability of the manufacturing process can be improved by using a highly reliable wire bonding process instead of the lead bonding process performed at micro B, G, and A. In addition, the heat sink is provided to maximize the heat dissipation performance.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000074259A KR20020044988A (en) | 2000-12-07 | 2000-12-07 | chip scale package and method for fabricating the same in wafer level |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000074259A KR20020044988A (en) | 2000-12-07 | 2000-12-07 | chip scale package and method for fabricating the same in wafer level |
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| Publication Number | Publication Date |
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| KR20020044988A true KR20020044988A (en) | 2002-06-19 |
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100598426B1 (en) * | 2004-07-27 | 2006-07-10 | 실버레이 주식회사 | An automatic manufacturing apparatus of nano silver water |
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2000
- 2000-12-07 KR KR1020000074259A patent/KR20020044988A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100598426B1 (en) * | 2004-07-27 | 2006-07-10 | 실버레이 주식회사 | An automatic manufacturing apparatus of nano silver water |
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