JPH10229097A - Manufacture of chip type semiconductor - Google Patents
Manufacture of chip type semiconductorInfo
- Publication number
- JPH10229097A JPH10229097A JP3192497A JP3192497A JPH10229097A JP H10229097 A JPH10229097 A JP H10229097A JP 3192497 A JP3192497 A JP 3192497A JP 3192497 A JP3192497 A JP 3192497A JP H10229097 A JPH10229097 A JP H10229097A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- semiconductor
- die
- dicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01067—Holmium [Ho]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、チップ型半導体の
製造方法に係り、特に発光ダイオード素子、フォトダイ
オード素子、フォトトランジスタ素子などの光半導体素
子、及び集積回路を基板の上に直接ダイボンドするタイ
プのチップ型半導体の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a chip type semiconductor, and more particularly to a method of directly bonding an optical semiconductor device such as a light emitting diode device, a photodiode device and a phototransistor device, and an integrated circuit onto a substrate. And a method for manufacturing a chip-type semiconductor.
【０００２】[0002]
【従来の技術】従来、この種のチップ型半導体は、例え
ば図４及び図５に示したような工程で製造されていた。
この製造方法では先ず半導体ウエハ１をダイシングシー
ト２に接着し（イ）、次いでダイシングシート２上の半
導体ウエハ１を枡目状にダイシングして各半導体チップ
３毎に分離する（ロ）。その後、半導体チップ３を１個
ずつ吸着し易いように、エキスパンド工程においてダイ
シングシート２を引っ張り、隣接する半導体チップ３同
士の間隔を空ける（ハ）。2. Description of the Related Art Heretofore, this type of chip type semiconductor has been manufactured by the steps shown in FIGS. 4 and 5, for example.
In this manufacturing method, first, the semiconductor wafer 1 is bonded to the dicing sheet 2 (A), and then the semiconductor wafer 1 on the dicing sheet 2 is diced into meshes and separated into individual semiconductor chips 3 (B). Thereafter, the dicing sheet 2 is pulled in the expanding step so as to easily adsorb the semiconductor chips 3 one by one, and a space is provided between adjacent semiconductor chips 3 (c).
【０００３】次の工程では、図５に示したように、吸着
ノズルによって半導体チップ３を１個ずつ基板４上に移
動し、所定の電極上に導電性接着剤５を介してダイボン
ドする（ニ）。ダイボンドしたのち、基板４をキュア炉
に通し、導電性接着剤５を溶融して基板４に半導体チッ
プ３を接合する。キュア炉から出した後に、半導体チッ
プ３の上面と基板４上の電極とを金属細線６でボンディ
ングする（ホ）。そして、半導体チップ３及び金属細線
６を保護するために透光性樹脂７で基板４の全面を樹脂
封止する（ヘ）。最後に、ダイシングマシーンによって
封止樹脂７及び基板４を半導体チップ３毎に枡目状に切
断し、１個ずつのチップ型半導体（チップ型発光ダイオ
ード）８を得る（ト）。In the next step, as shown in FIG. 5, the semiconductor chips 3 are moved one by one onto the substrate 4 by the suction nozzle and die-bonded onto predetermined electrodes via the conductive adhesive 5 (d). ). After die bonding, the substrate 4 is passed through a curing furnace, the conductive adhesive 5 is melted, and the semiconductor chip 3 is bonded to the substrate 4. After the substrate is taken out of the curing furnace, the upper surface of the semiconductor chip 3 and the electrode on the substrate 4 are bonded with the thin metal wires 6 (e). Then, the entire surface of the substrate 4 is resin-sealed with a translucent resin 7 to protect the semiconductor chip 3 and the thin metal wires 6 (f). Finally, the sealing resin 7 and the substrate 4 are cut into squares for each semiconductor chip 3 by a dicing machine to obtain chip semiconductors (chip light emitting diodes) 8 one by one (g).
【０００４】図６は、上記製造方法によって形成された
チップ型発光ダイオード８の拡大斜視図である。このチ
ップ型発光ダイオード８は、基板４の表面に形成された
電極４ａ，４ｂ間に電流を流すことにより半導体チップ
３が発光する。FIG. 6 is an enlarged perspective view of a chip type light emitting diode 8 formed by the above manufacturing method. In the chip type light emitting diode 8, the semiconductor chip 3 emits light by passing a current between the electrodes 4a and 4b formed on the surface of the substrate 4.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来のチップ型半導体の製造方法にあっては、ダイシング
した半導体チップ３を１個ずつ基板４上に移し替え、各
々位置合わせしてからダイボンドする工程と、ダイボン
ドした半導体チップ３と基板４上の電極とを金属細線６
を用いてワイヤボンディングする工程とが必要となって
いたために、作業工程が面倒であると共に作業時間がか
かってしまうという問題があった。However, in the above-mentioned conventional method of manufacturing a chip-type semiconductor, the steps of transferring the diced semiconductor chips 3 one by one onto the substrate 4 and aligning them each other before die bonding are performed. And a metal wire 6 between the die-bonded semiconductor chip 3 and the electrode on the substrate 4.
Therefore, there is a problem that the work process is troublesome and requires a long working time, since a wire bonding process using the method is required.
【０００６】そこで、本発明は半導体チップを基板上に
ダイボンドする工程を容易にすると共に、ダイボンドし
た半導体チップのワイヤボンディング工程を省略するこ
とを目的としている。Accordingly, it is an object of the present invention to facilitate the step of die bonding a semiconductor chip on a substrate and to omit the step of wire bonding the die bonded semiconductor chip.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明に係るチップ型半導体の製造方法は、第１の
基板の上面に半導体ウエハを導電性接着剤を介してダイ
ボンドする工程と、第１の基板は残した状態で半導体ウ
エハを半導体チップ毎にダイシングする工程と、ダイシ
ングした半導体ウエハの上面に第２の基板を導電性接着
剤を介してダイボンドする工程と、前記ダイシングによ
って生じた各半導体チップ間の隙間に樹脂を充填して封
止する工程と、樹脂封止した第１の基板、半導体ウエハ
及び第２の基板を前記ダイシングした半導体チップ毎に
再度ダイシングしてチップ型半導体を得る工程とを備え
たことを特徴とする。In order to solve the above-mentioned problems, a method of manufacturing a chip-type semiconductor according to the present invention includes a step of die-bonding a semiconductor wafer to an upper surface of a first substrate via a conductive adhesive. Dicing the semiconductor wafer into individual semiconductor chips while leaving the first substrate, a step of die-bonding the second substrate to the upper surface of the diced semiconductor wafer via a conductive adhesive, Filling the gap between the semiconductor chips with a resin and sealing, and dicing the resin-sealed first substrate, semiconductor wafer and second substrate again for each of the diced semiconductor chips to form a chip-type semiconductor. And a step of obtaining
【０００８】また、上記第１の基板及び第２の基板は、
導電性の基板もしくは絶縁性の基板のいずれでも対象と
なる。導電性の基板としては、銅板やアルミニウム板の
ような金属基板が主であり、また絶縁性の基板として
は、ガラスエポキシ板のような樹脂基板やポリエステル
フィルム、ホリイミドフィルムのようなフレキシブル基
板が主に利用される。[0008] The first substrate and the second substrate may include:
Either a conductive substrate or an insulating substrate is a target. As the conductive substrate, a metal substrate such as a copper plate or an aluminum plate is mainly used, and as the insulating substrate, a resin substrate such as a glass epoxy plate or a flexible substrate such as a polyester film or a polyimide film is used. Mainly used.
【０００９】[0009]
【発明の実施の形態】以下、添付図面に基づいて本発明
に係るチップ型半導体の製造方法を詳細に説明する。図
１は本発明に係るチップ型半導体の製造工程を示したも
のである。この製造工程では、先ず第１に、全面に電極
が形成された第１の基板９の上面全体に導電性接着剤１
０を均一に塗布し、その上に半導体ウエハ１１を位置決
めして載せる（イ）。次に、これをキュア炉に通して導
電性接着剤１０を硬化し、半導体ウエハ１１と第１の基
板９とを接着する。この時、導電性接着剤１０は、半導
体ウエハの全面に接着して全面電極を構成する。次のダ
イシング工程ではダイシングマシーンによって半導体ウ
エハ１１を枡目状に切断して半導体チップ１２毎に分割
する（ロ）。この時、半導体ウエハ１１と導電性接着剤
１０及び第１の基板９まで切れ目を入れる。この時、第
１の基板９は完全には切断しないように、ダイシングマ
シーンのブレードの深さを調整する。次いで、上記第１
の基板９と同様に、全面に電極が形成された第２の基板
１３の全面に導電性接着剤１０を塗布してから、半導体
チップ１２の上に位置決めして載せ、再びキュア炉に通
して導電性接着剤１０を硬化し、半導体チップ１２と第
２の基板１３とを接着する（ハ）。そして、ダイシング
によって半導体チップ１２同士の間に発生した隙間に透
光性樹脂１４を充填して半導体チップ１２の周囲を樹脂
封止する（ニ）。透光性樹脂１４はキュア炉に通すこと
で硬化する。なお、上記第１の基板９及び第２の基板１
３に、銅板やアルミニウム板のような金属板を用いた場
合には基板の全面がそのまま電極となるが、ガラスエポ
キシ板やフレキシブルフィルムを基板とする場合には表
面に銅箔などのパターンを形成することで電極とするこ
とができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a chip type semiconductor according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a manufacturing process of a chip type semiconductor according to the present invention. In this manufacturing process, first, the conductive adhesive 1 is applied to the entire upper surface of the first substrate 9 having the electrodes formed on the entire surface.
0 is uniformly applied, and the semiconductor wafer 11 is positioned and mounted thereon (a). Next, this is passed through a curing furnace to cure the conductive adhesive 10, and the semiconductor wafer 11 and the first substrate 9 are bonded. At this time, the conductive adhesive 10 adheres to the entire surface of the semiconductor wafer to form a full-surface electrode. In the next dicing step, the semiconductor wafer 11 is cut into meshes by a dicing machine and divided into semiconductor chips 12 (b). At this time, a cut is made to the semiconductor wafer 11, the conductive adhesive 10, and the first substrate 9. At this time, the depth of the blade of the dicing machine is adjusted so that the first substrate 9 is not completely cut. Then, the first
As in the case of the substrate 9, the conductive adhesive 10 is applied to the entire surface of the second substrate 13 having the electrodes formed on the entire surface, and then positioned and mounted on the semiconductor chip 12, and again passed through a curing furnace. The conductive adhesive 10 is cured, and the semiconductor chip 12 and the second substrate 13 are bonded (C). Then, the gap formed between the semiconductor chips 12 by dicing is filled with the translucent resin 14 to seal the periphery of the semiconductor chip 12 with the resin (d). The translucent resin 14 is cured by passing it through a cure furnace. The first substrate 9 and the second substrate 1
(3) When a metal plate such as a copper plate or an aluminum plate is used, the entire surface of the substrate becomes an electrode as it is, but when a glass epoxy plate or a flexible film is used as the substrate, a pattern such as a copper foil is formed on the surface. By doing so, an electrode can be obtained.
【００１０】次のダイシング工程では、上述のようにサ
ンドイッチ構造となった第１の基板９、半導体チップ１
２及び第２の基板１３を、ダイシングマシーンによって
半導体チップ１２毎に一緒に切断する（ホ）。このダイ
シングマシーンに使用されるブレードは、最初のダイシ
ングの時よりも幅の薄いものが使用される。従って、半
導体チップ１２の側面に樹脂封止した透光性樹脂１４を
残すことができ、半導体チップ１２の周囲を透光性樹脂
１４が取り囲んだチップ型半導体（チップ型発光ダイオ
ード）１５が完成する。In the next dicing step, the first substrate 9 and the semiconductor chip 1 having the sandwich structure as described above are formed.
The second substrate 13 and the second substrate 13 are cut together for each semiconductor chip 12 by a dicing machine (e). The blade used in the dicing machine has a smaller width than that of the first dicing. Therefore, the light-transmitting resin 14 sealed with resin can be left on the side surface of the semiconductor chip 12, and a chip-type semiconductor (chip-type light-emitting diode) 15 in which the light-transmitting resin 14 surrounds the periphery of the semiconductor chip 12 is completed. .
【００１１】図２は、上記製造方法によって形成された
チップ型発光ダイオード１５の拡大斜視図である。この
チップ型発光ダイオード１５は、第１の基板９の電極と
半導体チップ１２の一方側の電極、及び第２の基板１３
の電極と半導体チップ１２の他方側の電極が、いずれも
導電性接着剤１０を介して電気的に接続されている。従
って、第１の基板９と第２の基板１３との間に電流を流
すことにより半導体チップ１２が発光する。FIG. 2 is an enlarged perspective view of the chip type light emitting diode 15 formed by the above-described manufacturing method. The chip-type light emitting diode 15 includes an electrode on the first substrate 9, an electrode on one side of the semiconductor chip 12, and the second substrate 13.
Are electrically connected to each other on the other side of the semiconductor chip 12 via the conductive adhesive 10. Therefore, the semiconductor chip 12 emits light when a current flows between the first substrate 9 and the second substrate 13.
【００１２】図３は、上記チップ型発光ダイオード１５
をマザーボード１６上に実装した状態を示す断面図であ
る。この場合、マザーボード１６に対して第１及び第２
の基板９，１３が直交するようにチップ型発光ダイオー
ド１５を載置し、マザーボード１６の表面に形成された
ボード電極１７ａ，１７ｂ上に第１の基板９及び第２の
基板１３の各端面を配置する。そして、両者を半田１８
でそれぞれ接続することにより、第１の基板９と第２の
基板１３との間に電流が流れ、半導体チップ１２が発光
して上方及び基板９，１３によって塞がれていない側方
が光る。FIG. 3 shows the chip type light emitting diode 15.
FIG. 2 is a cross-sectional view showing a state in which is mounted on a motherboard 16. In this case, the first and second
The chip type light emitting diode 15 is mounted so that the substrates 9 and 13 are orthogonal to each other, and the respective end faces of the first substrate 9 and the second substrate 13 are placed on the board electrodes 17 a and 17 b formed on the surface of the motherboard 16. Deploy. Then, the solder 18
Respectively, a current flows between the first substrate 9 and the second substrate 13, the semiconductor chip 12 emits light, and the upper side and the side not blocked by the substrates 9 and 13 glow.
【００１３】このように、上記実施例では半導体ウエハ
１１を第１の基板９上に直接ダイボンドするので、従来
のように半導体チップを１個ずつ移し替えてダイボンド
するのに比べて作業が極めて容易となる。また、上記実
施例では第１の基板９と第２の基板１３との間に電気を
流すだけで半導体チップを発光させることができ、従来
のようなワイヤボンディング作業を省略することができ
た。As described above, in the above embodiment, since the semiconductor wafer 11 is directly die-bonded on the first substrate 9, the operation is extremely easy as compared with the conventional method in which semiconductor chips are transferred one by one and die-bonded. Becomes Further, in the above embodiment, the semiconductor chip can emit light only by passing electricity between the first substrate 9 and the second substrate 13, and the conventional wire bonding operation can be omitted.
【００１４】なお、本発明のチップ型半導体の製造方法
は、上述のようなチップ型発光ダイオードの製法に限定
されるものではなく、例えば集積回路のようなＩＣチッ
プの製造方法にも応用することができる。この場合、Ｉ
Ｃチップは上記実施例のように半導体ウエハの両面を導
電性接着剤によって接着するのではなく、ＩＣの電極パ
ッドと基板のパターンについては、バンプのような部分
的な接続によって基板に接着することができる。The method of manufacturing a chip-type semiconductor according to the present invention is not limited to the method of manufacturing a chip-type light emitting diode as described above, but may be applied to a method of manufacturing an IC chip such as an integrated circuit. Can be. In this case, I
As for the C chip, the electrode pads of the IC and the pattern of the substrate should be bonded to the substrate by partial connection such as bumps instead of bonding both surfaces of the semiconductor wafer with a conductive adhesive as in the above embodiment. Can be.
【００１５】[0015]
【発明の効果】以上説明したように、本発明に係るチッ
プ型半導体の製造方法によれば、半導体ウエハの状態で
基板上にダイボンドされた半導体ウエハを直接ダイシン
グしたので、従来のように１個ずつにダイシングされた
半導体チップを基板上にダイボンドする工程に比べて作
業が極めて容易になる。また、第１の基板と第２の基板
とのサンドイッチ構造としたことで、従来のような半導
体チップと基板上の電極とを金属細線を用いてワイヤボ
ンディングするという面倒な作業工程を省略することが
できた。As described above, according to the method of manufacturing a chip-type semiconductor according to the present invention, the semiconductor wafer die-bonded directly to the substrate in the state of the semiconductor wafer is directly diced. The operation becomes extremely easy as compared with the step of die-bonding the semiconductor chips diced at a time on a substrate. Further, the sandwich structure of the first substrate and the second substrate eliminates the troublesome work process of wire bonding the semiconductor chip and the electrodes on the substrate using a thin metal wire as in the related art. Was completed.
【図１】本発明に係るチップ型半導体の製造工程図であ
る。FIG. 1 is a manufacturing process diagram of a chip-type semiconductor according to the present invention.
【図２】本発明の製造方法により形成したチップ型発光
ダイオードの斜視図である。FIG. 2 is a perspective view of a chip-type light emitting diode formed by the manufacturing method of the present invention.
【図３】チップ型発光ダイオードのマザーボードへの実
装状態を示す断面図である。FIG. 3 is a cross-sectional view showing a mounted state of a chip type light emitting diode on a motherboard.
【図４】従来のチップ型半導体の製造工程図である。FIG. 4 is a manufacturing process diagram of a conventional chip-type semiconductor.
【図５】従来のチップ型半導体の製造工程図である。FIG. 5 is a manufacturing process diagram of a conventional chip-type semiconductor.
【図６】従来の製造方法により形成したチップ型発光ダ
イオードの斜視図である。FIG. 6 is a perspective view of a chip-type light emitting diode formed by a conventional manufacturing method.
９ 第１の基板 １０ 導電性接着剤 １１ 半導体ウエハ １２ 半導体チップ １３ 第２の基板 １４ 透光性樹脂 １５ チップ型発光ダイオード（チップ型半導体） 9 first substrate 10 conductive adhesive 11 semiconductor wafer 12 semiconductor chip 13 second substrate 14 translucent resin 15 chip type light emitting diode (chip type semiconductor)
Claims (2)
性接着剤を介してダイボンドする工程と、 第１の基板は残した状態で半導体ウエハを半導体チップ
毎にダイシングする工程と、 ダイシングした半導体ウエハの上面に第２の基板を導電
性接着剤を介してダイボンドする工程と、 前記ダイシングによって生じた各半導体チップ間の隙間
に樹脂を充填して封止する工程と、 樹脂封止した第１の基板、半導体ウエハ及び第２の基板
を前記ダイシングした半導体チップ毎に再度ダイシング
してチップ型半導体を得る工程とを備えたことを特徴と
するチップ型半導体の製造方法。A step of die-bonding a semiconductor wafer to an upper surface of a first substrate via a conductive adhesive; a step of dicing the semiconductor wafer for each semiconductor chip while leaving the first substrate; A step of die-bonding the second substrate to the upper surface of the semiconductor wafer via a conductive adhesive, a step of filling and sealing a resin between the semiconductor chips generated by the dicing, and a step of resin sealing. Dicing the first substrate, the semiconductor wafer, and the second substrate again for each of the diced semiconductor chips to obtain a chip-type semiconductor.
性の基板もしくは絶縁性の基板のいずれかであることを
特徴とする請求項１記載のチップ型半導体の製造方法。2. The method according to claim 1, wherein the first substrate and the second substrate are one of a conductive substrate and an insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03192497A JP3604108B2 (en) | 1997-02-17 | 1997-02-17 | Manufacturing method of chip type optical semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03192497A JP3604108B2 (en) | 1997-02-17 | 1997-02-17 | Manufacturing method of chip type optical semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10229097A true JPH10229097A (en) | 1998-08-25 |
| JP3604108B2 JP3604108B2 (en) | 2004-12-22 |
Family
ID=12344531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03192497A Expired - Lifetime JP3604108B2 (en) | 1997-02-17 | 1997-02-17 | Manufacturing method of chip type optical semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3604108B2 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252235A (en) * | 1999-02-25 | 2000-09-14 | Nec Corp | Semiconductor and manufacture thereof |
| KR100401975B1 (en) * | 2001-12-27 | 2003-10-17 | 삼성전기주식회사 | Chip package and the method of fabricating the same |
| KR100420433B1 (en) * | 1999-12-30 | 2004-03-03 | 앰코 테크놀로지 코리아 주식회사 | Film adhesive for semiconductor package |
| KR100444228B1 (en) * | 2001-12-27 | 2004-08-16 | 삼성전기주식회사 | Chip package and method of fabricating the same |
| WO2009103283A1 (en) * | 2008-02-22 | 2009-08-27 | Osram Opto Semiconductors Gmbh | Method for producing a plurality of radiation emitting components and radiation emitting component |
| JP2010133946A (en) * | 2008-10-31 | 2010-06-17 | Asahi Kasei Electronics Co Ltd | Method for manufacturing infrared sensor, infrared sensor and quantum-type infrared gas concentration meter |
| DE102007025950B4 (en) * | 2006-06-05 | 2012-08-30 | Denso Corporation | Semiconductor device and its manufacturing method |
| JP2013178282A (en) * | 2010-05-28 | 2013-09-09 | Olympus Corp | Cell isolation apparatus, cell isolation system and cell isolation method |
| US9274033B2 (en) | 2011-05-20 | 2016-03-01 | Olympus Corporation | Substrate-sheet fabricating method |
| US9291534B2 (en) | 2011-11-24 | 2016-03-22 | Olympus Corporation | Cell collection apparatus and cell collecting method |
| JP2016039324A (en) * | 2014-08-08 | 2016-03-22 | 日亜化学工業株式会社 | Light-emitting device and method for manufacturing light-emitting device |
| JP2016152416A (en) * | 2015-02-17 | 2016-08-22 | 立昌先進科技股▲分▼有限公司 | Multi-function miniaturized surface-mount device and method for producing the same |
| US9530204B2 (en) | 2010-11-19 | 2016-12-27 | Olympus Corporation | Method of preparing biological specimen |
-
1997
- 1997-02-17 JP JP03192497A patent/JP3604108B2/en not_active Expired - Lifetime
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252235A (en) * | 1999-02-25 | 2000-09-14 | Nec Corp | Semiconductor and manufacture thereof |
| KR100420433B1 (en) * | 1999-12-30 | 2004-03-03 | 앰코 테크놀로지 코리아 주식회사 | Film adhesive for semiconductor package |
| KR100401975B1 (en) * | 2001-12-27 | 2003-10-17 | 삼성전기주식회사 | Chip package and the method of fabricating the same |
| KR100444228B1 (en) * | 2001-12-27 | 2004-08-16 | 삼성전기주식회사 | Chip package and method of fabricating the same |
| DE102007025950B4 (en) * | 2006-06-05 | 2012-08-30 | Denso Corporation | Semiconductor device and its manufacturing method |
| US8309434B2 (en) | 2006-06-05 | 2012-11-13 | Denso Corporation | Method for manufacturing semiconductor device including semiconductor elements with electrode formed thereon |
| US8790939B2 (en) | 2008-02-22 | 2014-07-29 | Osram Opto Semiconductors Gmbh | Method for producing a plurality of radiation-emitting components and radiation-emitting component |
| WO2009103283A1 (en) * | 2008-02-22 | 2009-08-27 | Osram Opto Semiconductors Gmbh | Method for producing a plurality of radiation emitting components and radiation emitting component |
| JP2010133946A (en) * | 2008-10-31 | 2010-06-17 | Asahi Kasei Electronics Co Ltd | Method for manufacturing infrared sensor, infrared sensor and quantum-type infrared gas concentration meter |
| JP2013178282A (en) * | 2010-05-28 | 2013-09-09 | Olympus Corp | Cell isolation apparatus, cell isolation system and cell isolation method |
| US9304068B2 (en) | 2010-05-28 | 2016-04-05 | Olympus Corporation | Cell collection apparatus, cell collecting system, and cell collecting method |
| US9530204B2 (en) | 2010-11-19 | 2016-12-27 | Olympus Corporation | Method of preparing biological specimen |
| US9274033B2 (en) | 2011-05-20 | 2016-03-01 | Olympus Corporation | Substrate-sheet fabricating method |
| US9291534B2 (en) | 2011-11-24 | 2016-03-22 | Olympus Corporation | Cell collection apparatus and cell collecting method |
| JP2016039324A (en) * | 2014-08-08 | 2016-03-22 | 日亜化学工業株式会社 | Light-emitting device and method for manufacturing light-emitting device |
| JP2016152416A (en) * | 2015-02-17 | 2016-08-22 | 立昌先進科技股▲分▼有限公司 | Multi-function miniaturized surface-mount device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3604108B2 (en) | 2004-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6060729A (en) | Light-emitting device | |
| JP3337405B2 (en) | Light-emitting display element, method for connecting to light-emitting substrate, and method for manufacturing | |
| JP3342322B2 (en) | Method for manufacturing LED element display device | |
| JP2002208656A (en) | Semiconductor device | |
| JP2007207921A (en) | Method for manufacturing surface-mounting optical semiconductor device | |
| JPH11168235A (en) | Light emitting diode | |
| KR20050084598A (en) | Taped lead frames and methods of making and using the same in semiconductor packaging | |
| JPWO2016021476A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2002094123A (en) | Surface-mounted light emitting diode and its manufacturing method | |
| JPH10229097A (en) | Manufacture of chip type semiconductor | |
| JP2005327820A (en) | Package for light emitting diode, light emitting device employing same and manufacturing method of the light emitting device | |
| JP2002009347A (en) | Led light source and its manufacturing method | |
| US20060209514A1 (en) | Semiconductor device and manufacturing method therefor | |
| US5789820A (en) | Method for manufacturing heat radiating resin-molded semiconductor device | |
| JP2002110718A (en) | Manufacturing method of semiconductor device | |
| JP2002222992A (en) | Led light emitting element and device thereof | |
| JPH10335577A (en) | Semiconductor device and its manufacture | |
| KR100523803B1 (en) | Package of semiconductor device and fabrication method thereof | |
| JP2015185685A (en) | Light emitting device manufacturing method and light device | |
| CN110473865B (en) | Energy-saving LED lighting equipment and manufacturing method thereof | |
| JP3203228B2 (en) | Semiconductor device and manufacturing method thereof | |
| US10847689B2 (en) | Semiconductor light emitting device and method of manufacturing the same | |
| JPH10150069A (en) | Semiconductor package and its manufacture | |
| JP2002124627A (en) | Semiconductor device and its manufacturing method | |
| JPH09293905A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040622 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040625 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040824 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20040924 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040927 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071008 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101008 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131008 Year of fee payment: 9 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |