JP3203228B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3203228B2 JP3203228B2 JP06733098A JP6733098A JP3203228B2 JP 3203228 B2 JP3203228 B2 JP 3203228B2 JP 06733098 A JP06733098 A JP 06733098A JP 6733098 A JP6733098 A JP 6733098A JP 3203228 B2 JP3203228 B2 JP 3203228B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- resin
- semiconductor chip
- semiconductor device
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特にパッケージ外形を縮小し、実装面積を低減できる半
導体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of reducing a package outer shape and a mounting area.
【０００２】[0002]
【従来の技術】半導体装置の製造におけるパッケージン
グの技術には、金型と樹脂注入によるトランスファーモ
ールドが多用されている。このトランスファーモールド
技術にはリードフレームが用いられており、１本のリー
ドフレームで複数の半導体装置を同時に製造することに
なる。2. Description of the Related Art As a packaging technique in the manufacture of semiconductor devices, a transfer mold using a mold and resin injection is frequently used. A lead frame is used in this transfer molding technique, and a plurality of semiconductor devices are manufactured simultaneously with one lead frame.
【０００３】図５（Ａ）はトランスファーモールド工程
を示す図である。ダイボンド、ワイヤボンドにより半導
体チップ１をリードフレーム２に固着し、上下金型３
Ａ、３Ｂで形成したキャビティ４の内部にリードフレー
ム２を設置し、キャビティ４内にエポキシ樹脂を注入す
ることにより、半導体チップ１の封止が行われる。この
ようなトランスファーモールド工程の後、リードフレー
ム２を各半導体チップ１毎に切断して、個別の半導体装
置が製造される。FIG. 5A is a view showing a transfer molding process. The semiconductor chip 1 is fixed to the lead frame 2 by die bonding and wire bonding.
The semiconductor chip 1 is sealed by placing the lead frame 2 inside the cavity 4 formed by A and 3B and injecting the epoxy resin into the cavity 4. After such a transfer molding step, the lead frame 2 is cut for each semiconductor chip 1 to manufacture an individual semiconductor device.
【０００４】図５（Ｂ）は、トランスファーモールドに
よって製造した半導体装置を示す図である。トランジス
タ等の素子が形成された半導体チップ１がアイランド５
上に半田等のろう材６によって固着実装され、半導体チ
ップ１の電極パッドとリード７とがワイヤ８で接続さ
れ、半導体チップ１の周辺部分が上記キャビティの形状
に合致した樹脂９で被覆され、樹脂９の外部にリード７
の先端部分が導出されたものである。FIG. 5B is a diagram showing a semiconductor device manufactured by transfer molding. The semiconductor chip 1 on which elements such as transistors are formed is an island 5
The semiconductor chip 1 is fixedly mounted thereon with a brazing material 6 such as solder, the electrode pads of the semiconductor chip 1 are connected to the leads 7 by wires 8, and the peripheral portion of the semiconductor chip 1 is covered with a resin 9 conforming to the shape of the cavity. Lead 7 outside resin 9
Are derived.
【０００５】[0005]
【発明が解決しようとする課題】従来のリードフレーム
とトランスファーモールドを用いたパッケージでは、外
部接続用のリード端子を樹脂から突出させるので、リー
ド端子の先端部までの距離を実装面積として考慮しなく
てはならず、樹脂の外形寸法より実装面積の方が遙かに
大きくなるという欠点がある。In a conventional package using a lead frame and transfer mold, a lead terminal for external connection is made to protrude from the resin, so that the distance to the tip of the lead terminal is not considered as a mounting area. However, there is a disadvantage that the mounting area is much larger than the external dimensions of the resin.
【０００６】そのため、外部接続リードに半田バンプな
どを用いることで外形寸法と実装面積とをほぼ等しくす
るような手法や、実装基板上にベアチップを直接ダイボ
ンドする方法等が提案されている。このような命題に対
し、本願出願人は、絶縁基板とダイシング技術を用いる
ことにより、実装面積を大幅に低減した半導体装置を特
願平９−２６２１６０号に提案した。For this reason, there have been proposed methods of using solder bumps or the like for external connection leads to make the external dimensions substantially equal to the mounting area, and a method of directly die-bonding a bare chip onto a mounting substrate. In response to such a proposition, the present applicant proposed in Japanese Patent Application No. 9-262160 a semiconductor device in which the mounting area was significantly reduced by using an insulating substrate and dicing technology.
【０００７】斯かる装置は、図６を参照して、第１の絶
縁基板５１に導電パターンによりアイランド部５２とリ
ード部５３を設け、半導体チップ５４をダイボンド、ワ
イヤボンドし、第２の絶縁基板５５の裏面に外部電極５
６を設け、更に第２の絶縁基板５５の４隅に導電メッキ
を施した切り欠き５７を設けて外部電極５６と接続し、
該外部電極５６とアイランド部５２及びリード部５３と
を中間の導電体パターン５８とスルーホール５９とによ
り電気的に接続したものである。パッケージの外形寸法
は金型のキャビティで決めるのではなく、半導体チップ
５４の周囲で樹脂６０と共にダイシングで切断すること
により形成している。これを実装するときは、切り欠き
５７内面に露出する導電メッキ層と共に第２の絶縁基板
５５裏面に形成した外部電極５６を電極として、実装基
板に半田で接着するものである。この構造は、リード端
子が突出しないので、実装面積を大幅に低減する事がで
きる。尚、図６（Ｂ）は図６（Ａ）のＢＢ線断面図であ
る。Referring to FIG. 6, an island 52 and a lead 53 are provided on a first insulating substrate 51 by a conductive pattern, and a semiconductor chip 54 is die-bonded and wire-bonded. External electrodes 5 on the back of 55
6, and further provided with cutouts 57 provided with conductive plating at four corners of the second insulating substrate 55 and connected to the external electrodes 56,
The external electrode 56 is electrically connected to the island portion 52 and the lead portion 53 by an intermediate conductor pattern 58 and a through hole 59. The external dimensions of the package are not determined by the cavity of the mold, but are formed by dicing the semiconductor chip 54 with the resin 60 around the semiconductor chip 54. When this is mounted, the external electrode 56 formed on the back surface of the second insulating substrate 55 is used as an electrode together with the conductive plating layer exposed on the inner surface of the notch 57, and is bonded to the mounting substrate by soldering. In this structure, since the lead terminals do not protrude, the mounting area can be significantly reduced. FIG. 6B is a sectional view taken along the line BB of FIG. 6A.
【０００８】しかしながら、斯かる構造では樹脂６０と
第１の絶縁基板５１の境界部分にアイランド部５２とリ
ード部５３の導電パターンの端面が露出した構造とな
る。導電パターンに用いる金（Au）は半田との塗れ性が
極めて高いため、実装用の半田が前記導電パターンの端
面に達すると半田を吸着してしまい、第１の絶縁基板５
１と樹脂６０との境界に半田が侵入して剥がれ不良を生
じることが明らかになった。However, such a structure has a structure in which the end surfaces of the conductive patterns of the island portion 52 and the lead portion 53 are exposed at the boundary between the resin 60 and the first insulating substrate 51. Since gold (Au) used for the conductive pattern has extremely high wettability with the solder, when the mounting solder reaches the end face of the conductive pattern, the solder is attracted to the first insulating substrate 5.
It has been clarified that the solder penetrates into the boundary between the resin 1 and the resin 60 to cause peeling failure.
【０００９】[0009]
【課題を解決するための手段】本発明は、上述した各事
情に鑑みて成されたものであり、第１に、共通の絶縁基
板上に複数の半導体チップを搭載し、半導体チップを樹
脂で封止し、半導体チップを囲むように樹脂と絶縁基板
とをダイシング・切断することにより、装置の外形寸法
及び実装面積を大幅に低減できる半導体装置を提供する
ものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances. First, a plurality of semiconductor chips are mounted on a common insulating substrate, and the semiconductor chips are made of resin. An object of the present invention is to provide a semiconductor device capable of greatly reducing the external dimensions and mounting area of the device by sealing and dicing and cutting the resin and the insulating substrate so as to surround the semiconductor chip.
【００１０】第２に、絶縁基板の表面に形成した導電体
パターンを、絶縁基板の外周端面から内側に後退させる
ことにより、導電体パターンが露出することを防止し、
もって実装時の半田が樹脂と絶縁基板との界面に吸着さ
れる現象を防止するものである。Second, the conductor pattern formed on the surface of the insulating substrate is retreated inward from the outer peripheral end surface of the insulating substrate to prevent the conductor pattern from being exposed,
This prevents a phenomenon that the solder at the time of mounting is adsorbed on the interface between the resin and the insulating substrate.
【００１１】[0011]
【発明の実施の形態】以下に本発明の実施の形態を詳細
に説明する。図１は本発明の半導体装置を示す（Ａ）平
面図、（Ｂ）ＡＡ線断面図である。この半導体装置は、
板厚が各々２５０〜３５０μのセラミックやガラスエポ
キシ等からなる絶縁基板１１と、基板１１の上に搭載さ
れ、トランジスタ素子などを形成した半導体チップ１２
とを有する。Embodiments of the present invention will be described below in detail. FIG. 1A is a plan view showing a semiconductor device of the present invention, and FIG. This semiconductor device
An insulating substrate 11 made of ceramic, glass epoxy, or the like, each having a thickness of 250 to 350 μm, and a semiconductor chip 12 mounted on the substrate 11 and forming a transistor element and the like.
And
【００１２】絶縁基板１１の表面には、金メッキ層によ
ってアイランド部１３とリード部１４とが形成されてお
り、絶縁基板１１の裏面にも金メッキ層により外部電極
１５、１６が形成されている、アイランド部１３とリー
ド部１４には絶縁基板１１を貫通するスルーホール１
７、１８が設けられ、この内壁にも金メッキ層等が設け
られて、表面のアイランド部１３、リード部１４と外部
電極１５、１６とを電気的に接続している。これによ
り、外部電極１５がトランジスタのコレクタ電極とな
り、外部電極１６が各々トランジスタのベース、エミッ
タに対応する。An island portion 13 and a lead portion 14 are formed on the surface of the insulating substrate 11 by a gold plating layer, and external electrodes 15 and 16 are formed on the back surface of the insulating substrate 11 by the gold plating layer. The through hole 1 penetrating the insulating substrate 11 is provided in the portion 13 and the lead portion 14.
7 and 18 are provided, and a gold plating layer or the like is also provided on the inner wall to electrically connect the island portions 13 and the lead portions 14 on the surface to the external electrodes 15 and 16. Thus, the external electrode 15 becomes a collector electrode of the transistor, and the external electrode 16 corresponds to the base and the emitter of the transistor, respectively.
【００１３】そして、半導体チップ１２はアイランド部
１３に銀ペーストや金シリコン共晶等の接着剤１９によ
って固着されており、半導体チップ１２表面に形成した
ボンディングパッドとリード部１４とが、ワイヤ２０で
ワイヤボンディングされている。これらの半導体チップ
１２とワイヤ２０を被覆するように、絶縁基板１１の上
にエポキシ系の絶縁樹脂２１を形成してこれを封止し、
略直方体のパッケージを形成している。The semiconductor chip 12 is fixed to the island portion 13 by an adhesive 19 such as silver paste or gold silicon eutectic, and the bonding pad formed on the surface of the semiconductor chip 12 and the lead portion 14 are connected by wires 20. Wire bonded. An epoxy-based insulating resin 21 is formed on the insulating substrate 11 so as to cover the semiconductor chip 12 and the wires 20 and is sealed.
A substantially rectangular parallelepiped package is formed.
【００１４】パッケージの外形は、上面が樹脂２１によ
り、下面が絶縁基板１１の裏面により、そして４つの側
面が樹脂２１と絶縁基板１１の外周端面１１ａ、２１ａ
によって各々構成される。樹脂２１の外周端面２１ａと
絶縁基板１１の外周端面１１ａとは連続する同一水平面
を成している。そして、絶縁基板１１の表面に形成した
アイランド部１３とリード部１４の金メッキ層は、絶縁
基板１１の外周端部１１ａには達せず、基板１１の全周
にわたって、その端部から３０〜７０μの距離だけ後退
されている。後退された箇所には、絶縁基板１１の外周
端面１１ａに沿って半導体チップ１２の周囲を囲むよう
に幅が３０〜７０μ、深さ１００μ程度の溝２２が形成
されている。The outer shape of the package is such that the upper surface is made of the resin 21, the lower surface is made of the back surface of the insulating substrate 11, and the four side surfaces are made of the resin 21 and the outer peripheral end surfaces 11a
Respectively. The outer peripheral end surface 21a of the resin 21 and the outer peripheral end surface 11a of the insulating substrate 11 form the same continuous horizontal plane. Then, the gold plating layers of the island portions 13 and the lead portions 14 formed on the surface of the insulating substrate 11 do not reach the outer peripheral end 11 a of the insulating substrate 11, and extend 30 to 70 μm from the end over the entire periphery of the substrate 11. Have been retreated by a distance. In the recessed portion, a groove 22 having a width of about 30 to 70 μ and a depth of about 100 μ is formed along the outer peripheral end face 11 a of the insulating substrate 11 so as to surround the periphery of the semiconductor chip 12.
【００１５】図１（Ｃ）は、斯かる装置を実装した状態
を示す断面図である。実装基板２３上に形成された回路
網形成用のプリント配線２４に、装置の外部電極１５、
１６を位置あわせして、半田により装置が固着される。
半田２５は表面張力によって端部に盛り上がって半田フ
ィレット２５を形成する。本発明の半導体装置であれ
ば、アイランド部１３とリード部１４を後退させたこと
により、樹脂２１と絶縁基板１１との境界部分の側面に
金メッキ層が露出しないので、半田フィレット２５の半
田を吸収することもなく、樹脂２１が剥離する事故を回
避できる。また、溝２２を設けたことにより絶縁基板１
１と樹脂２１との密着面積が増大するので、両者の接着
強度を増大できる。FIG. 1C is a sectional view showing a state where such a device is mounted. External electrodes 15 of the device are connected to printed wirings 24 for forming a circuit network formed on a mounting substrate 23.
16 is aligned, and the device is fixed by soldering.
The solder 25 rises to the end due to surface tension to form a solder fillet 25. According to the semiconductor device of the present invention, since the island portion 13 and the lead portion 14 are retracted, the gold plating layer is not exposed on the side surface at the boundary between the resin 21 and the insulating substrate 11, so that the solder of the solder fillet 25 is absorbed. An accident in which the resin 21 peels off can be avoided without doing so. Also, the provision of the groove 22 allows the insulating substrate 1
Since the contact area between the resin 1 and the resin 21 increases, the adhesive strength between the two can be increased.
【００１６】以上に説明した半導体装置は、以下の方法
によって得ることができる。 第１工程：図２（Ａ）参照 まずは装置複数個分に対応する大判の絶縁基板１１を準
備する。絶縁基板１１の表面には金メッキ層によりアイ
ランド１３とリード部１４に対応するパターンが櫛歯状
の連続パターンで描画されている。絶縁基板１１の裏面
にも同様の連続パターンで外部電極１５、１６に対応す
る金メッキ層が形成される。アイランド１３とリード部
１４の絶縁基板１１には外部電極１５、１６と電気的接
続を取るためのスルーホール１６、１７が設けられてい
る。この段階では、アイランド部１３とリード部１４と
は分離していない連続したパターンである。The semiconductor device described above can be obtained by the following method. First step: See FIG. 2A First, a large-sized insulating substrate 11 corresponding to a plurality of devices is prepared. On the surface of the insulating substrate 11, a pattern corresponding to the island 13 and the lead portion 14 is drawn by a gold-plated layer in a comb-like continuous pattern. Gold plated layers corresponding to the external electrodes 15 and 16 are formed on the back surface of the insulating substrate 11 in a similar continuous pattern. On the insulating substrate 11 of the island 13 and the lead portion 14, through holes 16 and 17 for electrically connecting to the external electrodes 15 and 16 are provided. At this stage, the island portions 13 and the lead portions 14 are continuous patterns that are not separated.
【００１７】絶縁基板１１に対して、多数の半導体チッ
プ１２をダイボンドし、チップ上に形成したボンディン
グパッドとリード部１４とをボンディングワイヤ２０で
接続する。同図において、ダイシングライン２６で囲ま
れた領域が１つの半導体装置として後に切り出されるこ
とになる。 第２工程：図２（Ｂ） ダイシングライン２６を中心線として、これに沿うよう
幅５０〜８０μ、深さ約１００μの溝２２を形成する。
溝２２はダイシングブレードを用いて金メッキ層と共に
絶縁基板１１表面をダイシングすることによって形成す
る。これにより、溝２２を形成すると同時にアイランド
部１３とリード部１４をダイシングライン２６から後退
させることができる。A large number of semiconductor chips 12 are die-bonded to the insulating substrate 11, and the bonding pads formed on the chips and the leads 14 are connected by bonding wires 20. In the figure, a region surrounded by the dicing line 26 is cut out later as one semiconductor device. Second step: FIG. 2B With the dicing line 26 as a center line, a groove 22 having a width of 50 to 80 μ and a depth of about 100 μ is formed along the dicing line 26.
The groove 22 is formed by dicing the surface of the insulating substrate 11 with a gold plating layer using a dicing blade. Thereby, the island portion 13 and the lead portion 14 can be retracted from the dicing line 26 at the same time when the groove 22 is formed.
【００１８】第３工程：図３（Ａ） 絶縁基板１１の上にポッティングなどの手法により樹脂
２１を形成する。樹脂２１は半導体チップ１２を個別に
被覆するものではなく、複数の半導体チップ１２を連続
した樹脂層で一括して被覆する。例えば一枚の絶縁基板
１１に５０個の半導体チップ１２を搭載した場合は、５
０個全てのチップを一括して被覆する。Third step: FIG. 3A A resin 21 is formed on the insulating substrate 11 by a method such as potting. The resin 21 does not individually cover the semiconductor chips 12, but collectively covers the plurality of semiconductor chips 12 with a continuous resin layer. For example, when 50 semiconductor chips 12 are mounted on one insulating substrate 11, 5
All zero chips are covered at once.
【００１９】第４工程：図３（Ｂ） ダイシングブレード２７により、ダイシングライン２６
に沿って樹脂１２と絶縁基板１１を同時に切断し、個々
の半導体装置に分離する。この工程では溝２２の幅より
も板厚が狭いダイシングブレードを用いており、これに
よって絶縁基板１１の外周端面１１ａに溝２２を残し、
アイランド部１３とリード部１４との金メッキ層が樹脂
２１の外周端面２１ａに露出しない構造を得ることがで
きる。更に、ダイシングによってパッケージの４つの側
面を構成することにより、それらの切断面（外周端面２
５、２６、２７）が同一平面で構成される。Fourth step: FIG. 3B A dicing line 26 is formed by a dicing blade 27.
The resin 12 and the insulating substrate 11 are cut at the same time to separate the semiconductor devices into individual semiconductor devices. In this step, a dicing blade having a smaller plate thickness than the width of the groove 22 is used, thereby leaving the groove 22 on the outer peripheral end surface 11a of the insulating substrate 11,
A structure in which the gold plating layer of the island portion 13 and the lead portion 14 is not exposed on the outer peripheral end surface 21a of the resin 21 can be obtained. Further, by forming the four side surfaces of the package by dicing, their cut surfaces (the outer peripheral end surface 2) are formed.
5, 26, 27) on the same plane.
【００２０】以上の方法によって製造された半導体装置
は、以下のメリットを有する。多数個の素子をまとめて
樹脂でパッケージングするので、個々にパッケージング
する場合に比べて、無駄にする樹脂材料を少なくでき。
材料費の低減につながる。モールド金型とリードフレー
ムとの位置合わせ精度がプラス・マイナス５０μ程度で
あるのに対して、ダイシング装置の位置あわせ精度はプ
ラス・マイナス１０μ程度と精度が高い。従って樹脂外
形をダイシングで形成すれば、アイランド部１３から樹
脂２１の切断面までの肉厚を薄くして、より外形寸法の
小さなパッケージを得ることができるほか、同じ外形寸
法で比較すればアイランド部１３の面積を増大して、搭
載可能な半導体チップ１２を大型化できる。The semiconductor device manufactured by the above method has the following advantages. Since a large number of elements are packaged together with a resin, the amount of wasted resin material can be reduced as compared with the case of individually packaging.
This leads to a reduction in material costs. While the positioning accuracy between the mold and the lead frame is approximately ± 50 μ, the positioning accuracy of the dicing device is as high as ± 10 μ. Therefore, if the resin outer shape is formed by dicing, the thickness from the island portion 13 to the cut surface of the resin 21 can be reduced, and a package having a smaller outer size can be obtained. The area of the semiconductor chip 12 can be increased by increasing the area of the semiconductor chip 12.
【００２１】尚、ダイシングで溝２２を形成する手段に
代えて、アイランド部１３とリード部１４のパターンを
形成する際に、あらかじめダイシングライン２６から後
退させたパターンで形成することでも同様の構造を得る
ことができる。更に図４に示したように、溝２２の形成
と同時的にアイランド部１３とリード部１４との間の空
白部分にも溝２２ａを形成することにより、樹脂との密
着強度を更に向上することも可能である。Incidentally, instead of the means for forming the groove 22 by dicing, a similar structure can be obtained by forming the pattern of the island portion 13 and the lead portion 14 with a pattern which is set back from the dicing line 26 in advance. Obtainable. Further, as shown in FIG. 4, by simultaneously forming the groove 22, a groove 22 a is also formed in a blank portion between the island portion 13 and the lead portion 14, thereby further improving the adhesive strength with the resin. Is also possible.
【００２２】本実施形態では、半導体チップ１２にトラ
ンジスタを形成したが、縦型或いは比較的発熱量の少な
い横型のデバイスであればこれに限らず、例えば、パワ
ーＭＯＳＦＥＴ、ＩＧＢＴ、ＨＢＴ等のデバイスを形成
した半導体チップであっても、本発明に応用ができるこ
とは説明するまでもない。In this embodiment, the transistors are formed on the semiconductor chip 12. However, the present invention is not limited to the vertical type or a horizontal type device that generates a relatively small amount of heat. For example, a device such as a power MOSFET, IGBT, or HBT may be used. It is needless to say that the formed semiconductor chip can be applied to the present invention.
【００２３】[0023]
【発明の効果】以上に説明したように、本発明によれ
ば、リードフレームを用いた半導体装置よりも更に小型
化できるパッケージ構造を提供できる利点を有する。こ
のとき、リード端子が突出しない構造であるので、実装
したときの占有面積を低減し、高密度実装を実現でき
る。As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size than a semiconductor device using a lead frame. At this time, since the lead terminals do not protrude, the area occupied by mounting is reduced, and high-density mounting can be realized.
【００２４】更に、絶縁基板１１と樹脂２１との境界部
分に金メッキ層が露出しない構成としたので、実装時の
半田が境界部分に吸いこまれて樹脂２１が剥離する事故
を回避することができる。加えて、絶縁基板１１の外周
部分に溝２２を形成することにより、絶縁基板１１と樹
脂２１との密着力を増大でき、溝２２をダイシングで形
成することにより、金メッキ層の後退と溝２２の形成を
同時的に実施することができる。Further, since the gold plating layer is not exposed at the boundary between the insulating substrate 11 and the resin 21, it is possible to avoid an accident that the solder 21 is sucked into the boundary at the time of mounting and the resin 21 peels off. In addition, by forming the groove 22 on the outer peripheral portion of the insulating substrate 11, the adhesive force between the insulating substrate 11 and the resin 21 can be increased. By forming the groove 22 by dicing, the gold plating layer recedes and the groove 22 is formed. The formation can be performed simultaneously.
【図１】本発明の半導体装置を示す（Ａ）平面図、
（Ｂ）断面図、（Ｃ）断面図である。FIG. 1A is a plan view showing a semiconductor device of the present invention,
(B) is a sectional view, (C) is a sectional view.
【図２】製造方法を説明するための平面図である。FIG. 2 is a plan view for explaining a manufacturing method.
【図３】製造方法を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a manufacturing method.
【図４】他の実施の形態を示す（Ａ）平面図、（Ｂ）断
面図である。FIG. 4A is a plan view and FIG. 4B is a sectional view showing another embodiment.
【図５】従来例を説明する断面図。FIG. 5 is a cross-sectional view illustrating a conventional example.
【図６】半導体装置を示す（Ａ）平面図（Ｂ）断面図で
ある。6A is a plan view and FIG. 6B is a cross-sectional view illustrating a semiconductor device.
フロントページの続き (56)参考文献 特開 平９−181359（ＪＰ，Ａ) 特開 昭64−54749（ＪＰ，Ａ) 特開 平９−330997（ＪＰ，Ａ) 特開 平５−55278（ＪＰ，Ａ) 特開 平11−102924（ＪＰ，Ａ) 特開 平10−284525（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28 - 23/31 Continuation of front page (56) References JP-A-9-181359 (JP, A) JP-A-64-54749 (JP, A) JP-A-9-330997 (JP, A) JP-A-5-55278 (JP) JP-A-11-102924 (JP, A) JP-A-10-284525 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/28-23/31
Claims (4)
ランド部とリード部とを形成した絶縁性の基板と、 前記アイランド部に搭載した半導体チップと、 前記半導体チップの電極と前記リード部とを電気的に接
続する手段と、 前記絶縁性の基板の上に設けられて前記半導体チップ及
び前記アイランド部と前記リード部とを被覆する絶縁樹
脂層と、 前記絶縁基板の裏面側に形成され、前記アイランド部ま
たはリード部と電気的に接続された外部電極と、前記絶縁基板の外周端面と前記絶縁樹脂の外周端面と
が、同一平面をなすように切断された切断面で構成さ
れ、 前記アイランド部と前記リード部の導電体パターンが前
記外周端面より内側に後退され、 前記外周端面付近では前記絶縁性の基板の素材と前記絶
縁樹脂とが密着していることを特徴とする半導体装置。1. An insulating substrate having an island portion and a lead portion formed on a surface thereof by a conductor pattern, a semiconductor chip mounted on the island portion, and an electrode of the semiconductor chip and the lead portion electrically connected to each other. An insulating resin layer provided on the insulating substrate to cover the semiconductor chip, the island portion, and the lead portion; and an island portion formed on the back surface side of the insulating substrate. Or, an external electrode electrically connected to the lead portion, an outer peripheral end surface of the insulating substrate and an outer peripheral end surface of the insulating resin.
Are composed of cut surfaces that are cut so as to be flush with each other.
Is, the conductor pattern of said island portion and the lead portion is recessed inward from the outer peripheral end surface, said near the outer peripheral end face, characterized in that the material of the substrate of the insulation and the insulation resin is in close contact Semiconductor device.
徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein:
るための導電体パターンを形成した、絶縁性の基板を準Prepare an insulated substrate with a conductor pattern for
備する工程と、Process to prepare, 前記導電体パターンを前記絶縁性の基板の端から後退さThe conductor pattern is set back from the edge of the insulating substrate.
せる工程と、And the process of 前記導電体パターンに半導体チップを固着する工程と、Fixing a semiconductor chip to the conductor pattern; 前記半導体チップを被覆するように前記絶縁基板の上部Upper part of the insulating substrate so as to cover the semiconductor chip
を樹脂で被覆する工程と、Coating with a resin, 前記半導体チップの周囲で、前記樹脂と前記絶縁基板とAround the semiconductor chip, the resin and the insulating substrate
を同時的に切断して前記半導体素子を個々に分離する工To simultaneously separate the semiconductor elements by simultaneously cutting
程と、を具備することを特徴とする半導体装置の製造方And a method of manufacturing a semiconductor device, comprising:
法。Law.
端から後退させる工程が、前記導電パターンと共に前記
絶縁性の基板の途中までをダイシングすることを特徴と
する 、請求項３記載の半導体装置の製造方法 。 4. The method according to claim 1, wherein the conductive pattern is formed on the insulating substrate.
The step of retracting from the end, together with the conductive pattern,
Dicing up to the middle of the insulating substrate
The method for manufacturing a semiconductor device according to claim 3, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06733098A JP3203228B2 (en) | 1998-03-17 | 1998-03-17 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06733098A JP3203228B2 (en) | 1998-03-17 | 1998-03-17 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11265964A JPH11265964A (en) | 1999-09-28 |
| JP3203228B2 true JP3203228B2 (en) | 2001-08-27 |
Family
ID=13341912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06733098A Expired - Fee Related JP3203228B2 (en) | 1998-03-17 | 1998-03-17 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3203228B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102485176B1 (en) * | 2017-09-27 | 2023-01-05 | 엘지이노텍 주식회사 | Lamp module and head lamp comprising the same |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3901427B2 (en) | 1999-05-27 | 2007-04-04 | 松下電器産業株式会社 | Electronic device, manufacturing method thereof, and manufacturing device thereof |
| JP4711483B2 (en) * | 2000-01-11 | 2011-06-29 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP3560585B2 (en) | 2001-12-14 | 2004-09-02 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| JP2004087882A (en) * | 2002-08-28 | 2004-03-18 | Sanyo Electric Co Ltd | Semiconductor device |
| CN100411155C (en) * | 2004-01-27 | 2008-08-13 | 株式会社村田制作所 | Laminated electronic part and its manufacturing method |
-
1998
- 1998-03-17 JP JP06733098A patent/JP3203228B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102485176B1 (en) * | 2017-09-27 | 2023-01-05 | 엘지이노텍 주식회사 | Lamp module and head lamp comprising the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11265964A (en) | 1999-09-28 |
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