JP4162303B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can reduce the package area by reducing the package outer shape and further reduce the waste of materials associated with the manufacturing.
[0002]
[Prior art]
In the manufacture of a semiconductor device, a semiconductor chip diced and separated from a wafer is fixed to a lead frame, and the semiconductor chip fixed on the lead frame is sealed by a transfer mold using a mold and resin injection. A process of separating a semiconductor chip for each individual semiconductor device is performed. A strip-like or hoop-like frame is used for the lead frame, and in any case, a plurality of semiconductor devices are simultaneously sealed in one sealing step.
[0003]
FIG. 8 is a diagram showing the situation of the transfer molding process. In the transfer molding process, the lead frame 2 to which the semiconductor chip 1 is fixed by die bonding or wire bonding is placed inside the cavity 4 formed by the upper and lower molds 3A and 3B, and epoxy resin is injected into the cavity 4 The semiconductor chip 1 is sealed. After such a transfer molding process, the lead frame 2 is cut for each semiconductor chip 1 to manufacture individual semiconductor devices (for example, Japanese Patent Laid-Open No. 05-129473).
[0004]
At this time, as shown in FIG. 9, a large number of cavities 4a to 4d, a resin source 5 for injecting resin, the runner 6, and the runner 6 to the cavities 4a to 4d on the surface of the mold 3. A gate 7 for pouring resin is provided. These are all grooves provided on the surface of the mold 3. In the case of a strip-like lead frame, for example, ten semiconductor chips 1 are mounted on one lead frame, and corresponding to one lead frame, ten cavities 4 and ten gates 7, And one runner 6 is provided. For example, a cavity 4 for 20 lead frames is provided on the surface of the mold 3.
[0005]
FIG. 10 is a view showing a semiconductor device manufactured by the transfer mold described above. The semiconductor chip 1 on which elements such as transistors are formed is fixedly mounted on the island 8 of the lead frame by a soldering material 9 such as solder, and the electrode pads of the semiconductor chip 1 and the leads 10 are connected by wires 11. The peripheral portion of the lead terminal 10 is covered with the resin 12 matching the shape of the cavity, and the leading end portion of the lead terminal 10 is led out of the resin 12.
[0006]
[Problems to be solved by the invention]
In the conventional package, since the lead terminal 10 for external connection protrudes from the resin 12, the distance to the tip of the lead terminal 10 must be taken into consideration as the mounting area. The disadvantage is that it is much larger.
[0007]
In the transfer mold technique, the resin is cured at the runner 6 and the gate 7 because the resin is cured while pressure is continuously applied, and the resin remaining on the runner 6 and the like is disposed of. For this reason, the above-described method using the lead frame has the disadvantage that the use efficiency of the resin is poor and the number of semiconductor devices that can be manufactured is small with respect to the amount of resin because the gate 7 is provided for each semiconductor device to be manufactured. It was.
[0008]
[Means for Solving the Problems]
The present invention has been made in view of the above-mentioned conventional drawbacks, and a step of preparing an insulating substrate having a locally thin plate thickness at a location where a semiconductor chip is mounted and a thick plate thickness at other portions;
Mounting a plurality of semiconductor chips on the locally thin portion;
Coating the plurality of semiconductor chips with a common resin layer;
A method of manufacturing a semiconductor device that separates individual semiconductor devices by cutting the resin layer and the insulating substrate so as to surround the semiconductor chip,
The locally thin portion has a size capable of mounting a plurality of the semiconductor chips,
The insulating substrate is characterized in that a plurality of locally thin portions are arranged vertically and horizontally.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
[0010]
First Step: See FIGS. 1 and 2 First, for example, a large substrate 32 corresponding to 100 devices is prepared. The large-sized substrate 32 is obtained by adhering two sheets of first and second insulating substrates 21a and 21b, for example. The first insulating substrate 21a is a substrate made of ceramic or glass epoxy having a plate thickness (FIG. 2: t1) of 50 to 200 μm, and the second insulating substrate 11b has a plate thickness (FIG. 2: t2) of 100 to 250 μm. A substrate made of ceramic, glass epoxy or the like.
[0011]
The second insulating substrate 21 b is provided with a through hole 33 having a size sufficient to mount 2 to 10 semiconductor chips, for example, 4 semiconductor chips. The substrate 21a is exposed. Therefore, the plate thickness is locally thin (t1) in the portion of the through hole 33, whereas the other regions have a thick plate thickness (t1 + t2 = t3). A plurality of through holes 33 are regularly arranged vertically and horizontally, and the second insulating substrate 21b extends in a lattice pattern.
[0012]
In addition, you may use the board | substrate which provided the bottomed hole in the location corresponded to the through-hole 33 in one board | substrate, and formed the difference in plate | board thickness.
[0013]
FIG. 2 shows an enlarged plan view (A) and a sectional view (B) of the large-sized substrate 32. An island portion 24a is formed by a gold plating layer on the surface of the first insulating substrate 21a exposed in the through hole 33 of the second insulating substrate 21b, and an external electrode 25a is also formed by a gold plating layer on the back surface. Yes. The first insulating substrate 21a is provided with a through hole penetrating the first insulating substrate 21a, and the inside of the through hole is buried with a conductive material such as tungsten, Ag-Pd, Au, etc., so that the island portion 24 and the external electrode 25a are formed. Electrically connected. Internal electrodes 24b and 24c are drawn on the surface of the second insulating substrate 21b by a gold plating layer, and a gold plating pattern is drawn on the corresponding back surface of the first insulating substrate 21a to form the external electrodes 25. ing. The first insulating substrate 21a and the second insulating substrate 21b below the internal electrodes 24b and 24c are provided with through holes penetrating them, and the inside of the through holes is made of a conductive material such as tungsten, Ag-Pd, or Au. The internal electrodes 24b and 24c are electrically connected to the external electrodes 25 and 25, respectively.
[0014]
In the figure, a region 34 surrounded by a line is cut out later as one semiconductor device.
[0015]
Second Step: See FIG. 3 The semiconductor chip 22 is die-bonded to the large substrate 32 in such a state. First, the adhesive 27 is supplied onto the island part 24a inside the through-hole 33, and the semiconductor chip 22 is transported and fixed onto the island part 24a. Then, the bonding pads 28 formed on the semiconductor chip 22 and the internal electrodes 24 b and 24 c are wire-bonded with bonding wires 29.
[0016]
It should be noted that a region surrounded by the dicing line 34 is cut out as one semiconductor device by a dicing process performed after this process.
[0017]
Third step: See FIG. 4 A resin layer 23 is formed on a large substrate 32 and molded so as to cover the entire die-bonded semiconductor chip 22. The mold is supplied with resin by potting and cured, or is molded by an upper and lower mold having one cavity for each large-sized substrate 32. The resin layer 23 does not individually cover the semiconductor chips 22 but covers a plurality of semiconductor chips 22 together with a continuous resin. For example, when 100 semiconductor chips 22 are mounted on one large-sized substrate 32, all 100 chips are covered together. If potting, the amount of resin that is wasted is very small. Further, even in the case of transfer molding using a mold, only one gate needs to be provided for 100 devices, so the amount of waste is small.
[0018]
4th process: With reference to FIG. 5, the resin layer 23 and the 1st and 2nd insulation board | substrates 21a and 21b are cut | disconnected simultaneously along the dicing line 34 with the dicing blade 35 whose width is 100-300 micrometers, and isolate | separates into each semiconductor device To do. The side surfaces of the individual semiconductor devices are formed by dicing in this step, and the outer peripheral end surfaces of the first and second insulating substrates 21a and 21b are exposed on the cut surfaces, and the same plane as the resin layer 23 is formed.
[0019]
The manufacturing method described above has the following merits.
[0020]
Since a large number of elements are packaged together with resin, it is possible to reduce the amount of resin material that is wasted compared to the case of individual packaging. It leads to reduction of material cost.
[0021]
The alignment accuracy between the mold die and the lead frame is about plus / minus 50 μm, whereas the alignment accuracy of the dicing apparatus is as high as about plus / minus 10 μm. Therefore, by forming the resin outer shape by dicing, a package having a smaller outer size than the conventional one can be obtained.
[0022]
Since almost the entire large-sized substrate 32 has a relatively thick plate thickness (t3), the large-sized substrate 32 is prevented from being cracked or chipped in the manufacturing process and easy to handle. Since a general ceramic substrate starts to have insufficient mechanical strength when its thickness is less than 100 μm, in the present invention, only the first insulating substrate 21a has a thickness (t1) that tends to have insufficient strength. By reinforcing with the plate thickness (t2) of the second insulating substrate 21b, the large substrate 32 in which only the portion on which the semiconductor chip 22 is mounted was thin was formed. Specifically, a second insulating substrate 21b having a thickness equal to or greater than the thickness of the first insulating substrate 21a is attached to the first insulating substrate 21a, so that the overall thickness is increased. 150 μm or more, for example, 300 μm. As a result, the large substrate 32 has a thick plate thickness (t3) and has only a thin plate thickness (t1) locally, so that it can have sufficient mechanical strength for manufacturing. It becomes. In addition, after molding with the resin layer 23, the resin layer 23 maintains mechanical strength.
[0023]
In addition, if the first insulating substrate 21a extends beyond an area of about 20 mm × 20 mm, cracks are also likely to occur. Therefore, locally thin portions are scattered, and thick portions are extended in a grid pattern. Strength was maintained by letting.
[0024]
As a result, only the thickness (t1) of the island portion 24a can be reduced, so that the height of the entire semiconductor device can be kept low. The inventor of the present application was able to realize a small package transistor having a length × width × height of 1.0 mm × 0.5 mm × 0.5 mm by the method of the present application.
[0025]
6 and 7 show a semiconductor device formed by the above manufacturing method. 6A is a cross-sectional view showing a semiconductor device of the present invention, FIG. 6B is a plan view thereof, FIG. 7A is a perspective view of the device viewed from above, and FIG. It is a perspective view when seeing from below.
[0026]
Referring to FIGS. 6 and 7, this semiconductor device includes an insulating substrate 21 having first and second insulating substrates 21a and 21b attached thereto, and a transistor element fixed on the first insulating substrate 21a. The formed semiconductor chip 22 and the resin layer 23 that seals the whole including the semiconductor chip 22 are included.
[0027]
The semiconductor chip 22 is die-bonded to the island portion 24a of the first insulating substrate 21a with an adhesive 27 such as an Ag paste, and the electrode pads 28 on the surface of the semiconductor chip 22 and the internal electrodes 24b formed on the surface of the second insulating substrate 21b. , 24c are wire-bonded to each other by a gold wire 29. As a result, the external electrode 25a becomes a collector electrode, and the external electrodes 25b and 25c become base and emitter electrodes. The insulating substrate 21 on which die bonding and wire bonding are formed is covered with an epoxy insulating resin layer 23 to seal the semiconductor chip 22 and form a substantially rectangular parallelepiped package shape.
[0028]
Of the package outer shape, at least four side surfaces 23a to 23d are constituted by cut surfaces regardless of the mold surface. One of the outer peripheral end surface 30 of the first insulating substrate 21a and the outer peripheral end surface 31 of the second insulating substrate 21b is exposed on the surface of the resin layer 23, and is continuous with the side surfaces 23a, 23b, 23c, and 23d of the resin layer 23. They are on the same plane. These are formed by simultaneously cutting the resin layer 23 and the respective insulating substrates 21a and 21b by a cutting process, for example, a dicing blade.
[0029]
The second insulating substrate 21 b extends with a certain width along the side surface 23 d corresponding to one side of the semiconductor chip 22. The end portions are in contact with the side surfaces 23b and 23c adjacent to the side surface 23d, and two sides of the outer peripheral end surface 31 of the second insulating substrate 21b are exposed on the side surfaces 23b and 23c. The remaining one of the outer peripheral end surfaces 31 of the second insulating substrate 21 b is buried in the resin layer 23.
[0030]
Thus, the semiconductor device of the present invention has a structure in which the external electrodes 25a, 25b, and 25c do not protrude from the outer dimensions of the package. It is possible to realize a high-density mounting by reducing the area occupied by the substrate.
[0031]
Furthermore, the gold plating layer of the island portion 24a and the internal electrodes 24b and 24c formed on the surface of the insulating substrate 21 does not reach the side surfaces 23a to 23d of the resin layer 23, and is 30 to 30 mm from the end over the entire circumference of the insulating substrate 21. It is retracted by a distance of 70μ. The external electrodes 25a, 25b, 25c formed on the back surface of the first insulating substrate 21a are also retracted from the outer peripheral end surface 30 of the first insulating substrate 21a. This configuration produces two advantages.
[0032]
One advantage is obtained when the side surfaces 23a, 23b, 23c, 23d are cut with a dicing blade. That is, a gold plating layer having excellent properties as a conductive material is a material having excellent ductility at the same time. For this reason, when the gold plating layer is cut with a dicing blade, the gold plating layer is stretched by the blade to generate burrs, which causes poor appearance. Such an accident can be prevented by not contacting the dicing blade.
[0033]
Two of the advantages are obtained when the semiconductor device is mounted on a printed circuit board. That is, when mounting the semiconductor device described above, the external electrodes 25a, 25b, 25c of the first insulating substrate 21a are aligned and placed on the conductive pattern formed on the printed circuit board, and the two are soldered together. Although it adheres, gold has the property that it is very wettable with solder. Therefore, when the gold plating layer is exposed on the side surfaces 23a to 23d of the package and comes into contact with the solder, the solder enters the interface between the insulating substrate 21 and the resin layer 23, causing an accident such as resin peeling or electrical short circuit. Such an accident can be prevented by not exposing the gold plating layer on the side surface of the package.
[0034]
Thus, by partially thinning the portion where the semiconductor chip 22 is mounted, the overall height of the semiconductor device (t4 in FIG. 6) can be kept low.
[0035]
Furthermore, the height of the electrode pad 28 on the semiconductor chip 22 and the internal electrodes 24b, 24c can be approximated by thickening the location where the internal electrodes 24b, 24c are provided as the location where the plate thickness is increased. As a result, the bondability of the wire can be improved in the wire bonding step, and an accident of contact with the semiconductor chip 23 due to “sag” of the wire 29 can be avoided.
[0036]
【The invention's effect】
As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size as compared with a semiconductor device using a lead frame. At this time, since the lead terminal does not protrude, the occupied area when mounted can be reduced, and high-density mounting can be realized.
[0037]
Furthermore, since a large number of semiconductor chips 22 are collectively molded with the continuous resin layer 23, the amount of resin consumed per device can be saved and waste can be reduced.
[0038]
Furthermore, by making a difference in plate thickness between the first insulating substrate 21a and the second insulating substrate 21b, a small package can be realized while suppressing the height (t3) of the outer shape of the device.
[0039]
Further, the thin plate portions are interspersed and the thick plate portions are arranged in a lattice shape, thereby making it easy to handle the large substrate 32 in manufacturing and preventing the cracks and chips thereof.
[0040]
Furthermore, by arranging the internal electrodes 24b and 24c at a location where the plate thickness is thick, there is an advantage that the bondability of the wire bond can be improved.
[Brief description of the drawings]
FIG. 1 is a perspective view for explaining the present invention;
2A is a plan view and FIG. 2B is a sectional view for explaining the present invention.
3A is a plan view and FIG. 3B is a cross-sectional view for explaining the present invention.
FIG. 4 is a perspective view for explaining the present invention;
FIG. 5 is a perspective view for explaining the present invention;
6A is a sectional view and FIG. 6B is a plan view for explaining the present invention.
FIG. 7 is a perspective view for explaining the present invention.
FIG. 8 is a cross-sectional view illustrating a conventional example.
FIG. 9 is a plan view for explaining a conventional example.
FIG. 10 is a cross-sectional view illustrating a conventional example.

Claims (3)

A first region in which the semiconductor chip is mounted and the plate thickness is locally the first plate thickness; and a second region in the other portion that is thicker than the first plate thickness ; Preparing an insulating substrate having :
Mounting a plurality of semiconductor chips in the first region ;
Coating the plurality of semiconductor chips with a common resin layer;
A method of manufacturing a semiconductor device that separates individual semiconductor devices by cutting the resin layer and the insulating substrate so as to surround the semiconductor chip,
The first region has a size capable of mounting a plurality of the semiconductor chips,
A method of manufacturing a semiconductor device, wherein a plurality of the first regions are arranged vertically and horizontally on the insulating substrate.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the cutting step is a dicing step. The insulating substrate is a laminate of a first insulating substrate having the same thickness as the first region and a second insulating substrate having a through hole for forming the first region. The method of manufacturing a semiconductor device according to claim 1, wherein:

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