JP3710942B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3710942B2
JP3710942B2 JP29844198A JP29844198A JP3710942B2 JP 3710942 B2 JP3710942 B2 JP 3710942B2 JP 29844198 A JP29844198 A JP 29844198A JP 29844198 A JP29844198 A JP 29844198A JP 3710942 B2 JP3710942 B2 JP 3710942B2
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common substrate
semiconductor device
resin
resin layer
manufacturing
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JP2000124236A (en
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孝行 谷
治雄 兵藤
隆生 渋谷
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置の製造方法に関し、特にパッケージ外形を縮小し、実装面積を低減しコストダウンが可能な半導体装置の製造方法に関する。
【０００２】
【従来の技術】
半導体装置の製造においては、ウェハからダイシングして分離した半導体チップをリードフレームに固着し、金型と樹脂注入によるトランスファーモールドによってリードフレーム上に固着された半導体チップを封止し、封止された半導体チップを個々の半導体装置毎に分離するという工程が行われている。このリードフレームには短冊状あるいはフープ状のフレームが用いられており、いずれにしろ１回の封止工程で複数個の半導体装置が同時に封止されている。
【０００３】
図７は、トランスファーモールド工程の状況を示す図である。トランスファーモールド工程では、ダイボンド、ワイヤボンドにより半導体チップ１が固着されたリードフレーム２を、上下金型３Ａ、３Ｂで形成したキャビティ４の内部に設置し、キャビティ４内にエポキシ樹脂を注入することにより、半導体チップ１の封止が行われる。このようなトランスファーモールド工程の後、リードフレーム２を各半導体チップ１毎に切断して、個別の半導体装置が製造される（例えば特開平０５−１２９４７３号）。
【０００４】
この時、図８に示すように、金型３Ｂの表面には多数個のキャビティ４ａ〜４ｆと、樹脂を注入するための樹脂源５と、ランナー６、及びランナー６から各キャビティ４ａ〜４ｆに樹脂を流し込むためのゲート７とが設けられている。これらは全て金型３Ｂ表面に設けた溝である。短冊状のリードフレームであれば、１本のリードフレームに例えば１０個の半導体チップ１が搭載されており、１本のリードフレームに対応して、１０個のキャビティ４と１０本のゲート７、及び１本のランナー６が設けられる。そして、金型３表面には例えばリードフレーム２０本分のキャビティ４が設けられる。
【０００５】
図９は、上記のトランスファーモールドによって製造した半導体装置を示す図である。トランジスタ等の素子が形成された半導体チップ１がリードフレームのアイランド８上に半田等のろう材９によって固着実装され、半導体チップ１の電極パッドとリード１０とがワイヤ１１で接続され、半導体チップ１の周辺部分が上記キャビティの形状に合致した樹脂１２で被覆され、樹脂１２の外部にリード端子１０の先端部分が導出されたものである。
【０００６】
【発明が解決しようとする課題】
従来のパッケージでは、外部接続用のリード端子１０を樹脂１２から突出させるので、リード端子１０の先端部までの距離を実装面積として考慮しなくてはならず、樹脂１２の外形寸法より実装面積の方が遥かに大きくなるという欠点がある。
【０００７】
また、従来のトランスファーモールド技術では、圧力をかけ続けた状態で硬化させることから、ランナー６とゲート７においても樹脂が硬化し、このランナー６等に残った樹脂は廃棄処分となる。そのため、上記のリードフレームを用いた手法では、製造すべき半導体装置個々にゲート７を設けるので、樹脂の利用効率が悪く、樹脂の量に対して製造できる半導体装置の個数が少ないという欠点があった。
【０００８】
【課題を解決するための手段】
本発明は、上述した各事情に鑑みて成されたものであり、半導体チップを固着するための複数の搭載部と、該複数個の搭載部を取り囲むダム部とを有する共通基板を準備する工程と、
前記搭載部の各々に、半導体チップを固着する工程と、
前記共通基板の上に樹脂を供給して、前記複数個の半導体チップを共通の樹脂層で被覆する工程と、
前記樹脂層と前記共通基板とを分割し、前記搭載部を個々に分割する工程とを具備することを具備することを特徴とするものである。
【０００９】
【発明の実施の形態】
以下に本発明の実施の形態を詳細に説明する。
【００１０】
第１工程：図１参照
まず、図１（Ａ）（Ｂ）に示したような、製造すべき半導体装置の複数個分、例えば１００個分に対応する搭載部２０が縦横に配置された大判の共通基板２１を準備する。共通基板２１は、セラミックやガラスエポキシ等からなる絶縁基板であり、それらが１枚あるいは数枚重ね合わされて、合計の板厚が２５０〜３５０μｍと製造工程における機械的強度を維持し得る板厚を有している。
【００１１】
搭載部２０表面の各々には、金メッキ層による導電パターン２２が電解あるいは無電解メッキ工程よって形成されている。導電パターンのパターン形状は、次工程の説明で明らかにされる。そして、金メッキ工程で導電パターンと同時的に、共通基板２１の周辺部分に搭載部２０群を取り囲むダム部２３が設けられている。ダム部２３は、幅が０．２〜０．５ｍｍ、膜厚が５〜２０μｍで形成されている。
【００１２】
第２工程：図２参照
共通基板２１の各搭載部２０毎に、半導体チップ２４をダイボンド、ワイヤボンドする。図２（Ｂ）を参照して、各搭載部２０の表面には、導電パターン２２によって半導体チップ２４を搭載するためのアイランド部２５やボンディングワイヤ２６を接続するためのリード部２７を形成する。この例では、バイポーラトランジスタ、パワーＭＯＳＦＥＴ等の３端子の半導体チップを搭載している。共通基板２１の裏面側にも金メッキ層によって導電パターンが形成されており（図示せず）、該裏面側の導電パターンが外部接続用の端子となる。そして、共通基板２１表面側の導電パターンと裏面側の導電パターンとが、共通基板２１を貫通するスルーホールを介して電気的に接続されている。各搭載部２０間の間隔が、各搭載部２０毎の分割ライン２８となる。
【００１３】
第３工程：図３参照
共通基板２１の上方に移送したディスペンサ２９から所定量のエポキシ系液体樹脂を滴下（ポッティング）し、すべての半導体チップ２４を共通の樹脂層３０で被覆する。例えば一枚の共通基板２１に１００個の半導体チップ２４を搭載した場合は、１００個全ての半導体チップ２４を一括して被覆する。前記液体樹脂として例えばＣＶ５７６ＡＮ（松下電工製）を用いた。滴下した液体樹脂は比較的粘性が高く、表面張力を有しているので、その表面が図３（Ａ）に示すように湾曲面を構成する。このとき、共通基板２１の周辺部に形成したダム部２３は、その膜厚が形成する高さの差によって、樹脂層３０が過剰に流出することを防止する。樹脂に表面張力があるので、金メッキ層のような少しの高さの差でも、その流出を止めることが可能である。
【００１４】
この様にして半導体チップ３９を封止した後に、１００〜２００度、数時間の熱処理（キュア）にて樹脂５２を硬化させる。
【００１５】
第４工程：図４参照
次に、樹脂層３０の湾曲した表面を削って平坦面を形成する。ダイシング装置を用い、ダイシングブレード３１によって樹脂層３０の表面が共通基板２１から一定の高さに揃うように、樹脂層３０表面を削る。この工程では、樹脂層２９の膜厚を０．３〜１．０ｍｍに成形する。平坦面は、少なくとも最も外側に位置する半導体チップ２４を個別半導体装置に分離したときに、規格化したパッケージサイズの樹脂外形を構成できるように、その端部まで拡張する。前記ブレードには様々な板厚のものが準備されており、比較的厚めのブレードを用いて、切削を複数回繰り返すことで全体を平坦面に形成する。
【００１６】
尚、ダイシングブレードの他に砥石による研磨等でも平坦面を形成することが可能である。また、樹脂層３０が硬化する前に、表面が平坦なる成形部材を樹脂層３０表面に押しつけることによっても、平坦面を形成することができる。
【００１７】
第５工程：図５参照
次に、搭載部２０毎に樹脂層３０を切断して各々の半導体装置３３を分離する。切断にはダイシング装置を用い、ダイシングブレード３２によって分割ライン２８に沿って樹脂層３０と共通基板２１とを同時に切断することにより、搭載部２０毎に分割した半導体装置３３を形成する。ダイシング工程においては共通基板２１の裏面側にブルーシート（たとえば、商品名：ＵＶシート、リンテック株式会社製）を貼り付け、前記ダイシングブレードがブルーシートの表面に到達するような切削深さで切断する。この時には、共通基板２１の表面にあらかじめ形成した合わせマークをダイシング装置側で自動認識し、これを位置基準として用いてダイシングする。
【００１８】
図６は、上述の工程によって形成された各半導体装置３３を示す図である。図６（Ａ）が樹脂層３０側から観測した斜視図（但し樹脂層を点線で示した）、図６（Ｂ）が共通基板２１側から観測した斜視図である。パッケージの周囲４辺には樹脂層３０と共通基板２１の切断面が露出する。パッケージの上面は平坦化した樹脂層３０の表面が露出し、パッケージの下面は共通基板２１の裏面側が露出する。裏面側の金メッキ層による導電パターン２５ａ、２７ａは、各々がアイランド部２５、リード部２７に電気的に接続されている。バイポーラトランジスタを封止した場合であれは、導電パターン２５ａがコレクタ端子となり、導電パターン２７ａがベースとエミッタの端子となる。
【００１９】
斯かる手法によって形成した半導体装置は、以下のメリットを有する。
【００２０】
多数個の素子をまとめて樹脂でパッケージングするので、個々にパッケージングする場合に比べて、無駄にする樹脂材料を少なくでき。材料費の低減につながる。
【００２１】
リードフレームを用いないので、従来のトランスファーモールド手法に比べて、パッケージ外形を大幅に小型化することができる。
【００２２】
外部接続用の端子が共通基板２１の裏面に形成され、パッケージの外形から突出しないので、装置の実装面積を大幅に小型化できる。
【００２３】
ポッティングで樹脂封止するので、従来の金型３Ａ、３Ｂを不要にできる。これによって、大幅なコストダウンが可能である
共通基板２１表面にダム部２３を設けることによって、ポッティング樹脂の過大な流出を止めることができるので、製造工程における障害の発生を防止できる。また、過大な流出を止めることによって、供給した樹脂層３０の膜厚が安定化し、膜厚不足による外形不良の発生を抑制できる。さらには、ダム部２３を金メッキ層で形成することにより、ダム部２３を形成するための特別な部材を不要とすることができる。
【００２４】
【発明の効果】
以上に説明したように、本発明によれば、リードフレームを用いた半導体装置よりも更に小型化できるパッケージ構造を提供できる利点を有する。このとき、リード端子が突出しない構造であるので、実装したときの占有面積を低減し、高密度実装を実現できる。
【００２５】
さらに、キャビティを構成するための金型３Ａ、３Ｂが不要であるので、大幅なコストダウンが可能である利点を有する。
【００２６】
そして、共通基板２１周辺部にダム部２３を設けることによって、樹脂層３０の膜厚が安定化し、製造工程における障害発生を防止し且つ膜厚不足による外形不良の発生を防止できる利点を有する。
【図面の簡単な説明】
【図１】本発明の第１工程を示す（Ａ）断面図、（Ｂ）斜視図である。
【図２】本発明の第２工程を示す（Ａ）断面図、（Ｂ）平面図である。
【図３】本発明の第３工程を示す断面図である。
【図４】本発明の第４工程を示す断面図である。
【図５】本発明の第５工程を示す断面図である。
【図６】本発明の半導体装置を示す斜視図である。
【図７】従来例を説明するための断面図である。
【図８】従来例を説明するための平面図である。
【図９】従来例を説明するための断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of reducing the package outer shape, reducing the mounting area, and reducing the cost.
[0002]
[Prior art]
In the manufacture of a semiconductor device, a semiconductor chip diced and separated from a wafer is fixed to a lead frame, and the semiconductor chip fixed on the lead frame is sealed by a transfer mold using a mold and resin injection. A process of separating a semiconductor chip for each individual semiconductor device is performed. A strip-like or hoop-like frame is used for the lead frame, and in any case, a plurality of semiconductor devices are simultaneously sealed in one sealing step.
[0003]
FIG. 7 is a diagram showing the situation of the transfer molding process. In the transfer molding process, the lead frame 2 to which the semiconductor chip 1 is fixed by die bonding or wire bonding is placed inside the cavity 4 formed by the upper and lower molds 3A and 3B, and epoxy resin is injected into the cavity 4 The semiconductor chip 1 is sealed. After such a transfer molding process, the lead frame 2 is cut for each semiconductor chip 1 to manufacture individual semiconductor devices (for example, Japanese Patent Laid-Open No. 05-129473).
[0004]
At this time, as shown in FIG. 8, a large number of cavities 4a to 4f, a resin source 5 for injecting resin, the runner 6, and the runner 6 to the cavities 4a to 4f are formed on the surface of the mold 3B. A gate 7 for pouring resin is provided. These are all grooves provided on the surface of the mold 3B. In the case of a strip-like lead frame, for example, ten semiconductor chips 1 are mounted on one lead frame, and corresponding to one lead frame, ten cavities 4 and ten gates 7, And one runner 6 is provided. For example, a cavity 4 for 20 lead frames is provided on the surface of the mold 3.
[0005]
FIG. 9 is a view showing a semiconductor device manufactured by the transfer mold. The semiconductor chip 1 on which elements such as transistors are formed is fixedly mounted on the island 8 of the lead frame by a soldering material 9 such as solder, and the electrode pads of the semiconductor chip 1 and the leads 10 are connected by wires 11. The peripheral portion of the lead terminal 10 is covered with the resin 12 matching the shape of the cavity, and the leading end portion of the lead terminal 10 is led out of the resin 12.
[0006]
[Problems to be solved by the invention]
In the conventional package, since the lead terminal 10 for external connection protrudes from the resin 12, the distance to the tip of the lead terminal 10 must be taken into consideration as the mounting area. The disadvantage is that it is much larger.
[0007]
Further, in the conventional transfer mold technology, the resin is cured in the runner 6 and the gate 7 because the resin is cured while pressure is continuously applied, and the resin remaining in the runner 6 and the like is disposed of. For this reason, the above-described method using the lead frame has the disadvantage that the use efficiency of the resin is poor and the number of semiconductor devices that can be manufactured is small with respect to the amount of resin because the gate 7 is provided for each semiconductor device to be manufactured. It was.
[0008]
[Means for Solving the Problems]
The present invention has been made in view of the above-described circumstances, and a step of preparing a common substrate having a plurality of mounting portions for fixing a semiconductor chip and a dam portion surrounding the plurality of mounting portions. When,
A step of fixing a semiconductor chip to each of the mounting portions;
Supplying a resin on the common substrate and coating the plurality of semiconductor chips with a common resin layer;
A step of dividing the resin layer and the common substrate and individually dividing the mounting portion.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail.
[0010]
First Step: See FIG. 1 First, as shown in FIGS. 1A and 1B, a large format in which mounting portions 20 corresponding to a plurality of, for example, 100 semiconductor devices to be manufactured are arranged vertically and horizontally. The common substrate 21 is prepared. The common substrate 21 is an insulating substrate made of ceramic, glass epoxy, or the like, and one or several of them are overlapped so that the total plate thickness is 250 to 350 μm, which can maintain the mechanical strength in the manufacturing process. Have.
[0011]
A conductive pattern 22 made of a gold plating layer is formed on each surface of the mounting portion 20 by an electrolytic or electroless plating process. The pattern shape of the conductive pattern will be clarified in the description of the next step. A dam portion 23 surrounding the mounting portion 20 group is provided in the peripheral portion of the common substrate 21 simultaneously with the conductive pattern in the gold plating process. The dam part 23 is formed with a width of 0.2 to 0.5 mm and a film thickness of 5 to 20 μm.
[0012]
Second step: See FIG. 2. For each mounting portion 20 of the common substrate 21, the semiconductor chip 24 is die-bonded and wire-bonded. With reference to FIG. 2B, island portions 25 for mounting semiconductor chips 24 and lead portions 27 for connecting bonding wires 26 are formed on the surface of each mounting portion 20 by a conductive pattern 22. In this example, a three-terminal semiconductor chip such as a bipolar transistor and a power MOSFET is mounted. A conductive pattern is also formed on the back side of the common substrate 21 by a gold plating layer (not shown), and the conductive pattern on the back side serves as a terminal for external connection. The conductive pattern on the front surface side of the common substrate 21 and the conductive pattern on the back surface side are electrically connected through a through hole penetrating the common substrate 21. An interval between the mounting portions 20 is a dividing line 28 for each mounting portion 20.
[0013]
Third Step: See FIG. 3 A predetermined amount of epoxy-based liquid resin is dropped (potted) from the dispenser 29 transferred above the common substrate 21, and all the semiconductor chips 24 are covered with the common resin layer 30. For example, when 100 semiconductor chips 24 are mounted on one common substrate 21, all 100 semiconductor chips 24 are collectively covered. For example, CV576AN (manufactured by Matsushita Electric Works) was used as the liquid resin. Since the dropped liquid resin has a relatively high viscosity and a surface tension, the surface forms a curved surface as shown in FIG. At this time, the dam portion 23 formed in the peripheral portion of the common substrate 21 prevents the resin layer 30 from flowing out excessively due to the difference in height formed by the film thickness. Since the resin has surface tension, it is possible to stop the outflow even with a slight difference in height as in the gold plating layer.
[0014]
After sealing the semiconductor chip 39 in this way, the resin 52 is cured by heat treatment (curing) for several hours at 100 to 200 degrees.
[0015]
Fourth Step: See FIG. 4 Next, the curved surface of the resin layer 30 is shaved to form a flat surface. Using a dicing apparatus, the surface of the resin layer 30 is shaved by the dicing blade 31 so that the surface of the resin layer 30 is aligned at a certain height from the common substrate 21. In this step, the resin layer 29 is formed to a thickness of 0.3 to 1.0 mm. The flat surface extends to its end so that at least the outermost semiconductor chip 24 can be separated into individual semiconductor devices to form a standardized package size resin profile. Various blade thicknesses are prepared for the blade, and the entire blade is formed on a flat surface by repeating cutting a plurality of times using a relatively thick blade.
[0016]
In addition to the dicing blade, a flat surface can be formed by polishing with a grindstone. Moreover, a flat surface can also be formed by pressing a molding member having a flat surface against the surface of the resin layer 30 before the resin layer 30 is cured.
[0017]
5th process: See FIG. 5 Next, the resin layer 30 is cut | disconnected for every mounting part 20, and each semiconductor device 33 is isolate | separated. A dicing apparatus is used for cutting, and the resin layer 30 and the common substrate 21 are simultaneously cut along the dividing line 28 by the dicing blade 32 to form the semiconductor device 33 divided for each mounting portion 20. In the dicing process, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Corporation) is attached to the back side of the common substrate 21 and cut at a cutting depth such that the dicing blade reaches the surface of the blue sheet. . At this time, the alignment mark formed in advance on the surface of the common substrate 21 is automatically recognized on the dicing apparatus side, and dicing is performed using this as a position reference.
[0018]
FIG. 6 is a diagram showing each semiconductor device 33 formed by the above-described steps. 6A is a perspective view observed from the resin layer 30 side (however, the resin layer is indicated by a dotted line), and FIG. 6B is a perspective view observed from the common substrate 21 side. The cut surfaces of the resin layer 30 and the common substrate 21 are exposed on the four sides around the package. The upper surface of the package exposes the planarized surface of the resin layer 30, and the lower surface of the package exposes the back side of the common substrate 21. The conductive patterns 25a and 27a made of the gold plating layer on the back side are electrically connected to the island portion 25 and the lead portion 27, respectively. Even when the bipolar transistor is sealed, the conductive pattern 25a becomes the collector terminal, and the conductive pattern 27a becomes the base and emitter terminals.
[0019]
A semiconductor device formed by such a method has the following merits.
[0020]
Since a large number of elements are packaged together with resin, it is possible to reduce the amount of resin material that is wasted compared to the case of individual packaging. It leads to reduction of material cost.
[0021]
Since no lead frame is used, the package outer shape can be greatly reduced as compared with the conventional transfer molding method.
[0022]
Since terminals for external connection are formed on the back surface of the common substrate 21 and do not protrude from the outer shape of the package, the mounting area of the device can be significantly reduced.
[0023]
Since the resin is sealed by potting, the conventional molds 3A and 3B can be made unnecessary. Accordingly, by providing the dam portion 23 on the surface of the common substrate 21 where the cost can be significantly reduced, it is possible to stop the excessive outflow of the potting resin, and thus it is possible to prevent the occurrence of trouble in the manufacturing process. Moreover, by stopping an excessive outflow, the thickness of the supplied resin layer 30 is stabilized, and the occurrence of an external defect due to insufficient film thickness can be suppressed. Furthermore, the special member for forming the dam part 23 can be made unnecessary by forming the dam part 23 with a gold plating layer.
[0024]
【The invention's effect】
As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size as compared with a semiconductor device using a lead frame. At this time, since the lead terminal does not protrude, the occupied area when mounted can be reduced, and high-density mounting can be realized.
[0025]
Further, since the molds 3A and 3B for forming the cavity are unnecessary, there is an advantage that the cost can be significantly reduced.
[0026]
And providing the dam part 23 in the peripheral part of the common substrate 21 has an advantage that the film thickness of the resin layer 30 is stabilized, the occurrence of troubles in the manufacturing process can be prevented, and the appearance defect due to the insufficient film thickness can be prevented.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view and FIG. 1B is a perspective view showing a first step of the present invention.
FIG. 2A is a cross-sectional view and FIG. 2B is a plan view showing a second step of the present invention.
FIG. 3 is a cross-sectional view showing a third step of the present invention.
FIG. 4 is a cross-sectional view showing a fourth step of the present invention.
FIG. 5 is a cross-sectional view showing a fifth step of the present invention.
FIG. 6 is a perspective view showing a semiconductor device of the present invention.
FIG. 7 is a cross-sectional view for explaining a conventional example.
FIG. 8 is a plan view for explaining a conventional example.
FIG. 9 is a cross-sectional view for explaining a conventional example.

Claims (4)

共通基板を準備し、前記共通基板の複数の搭載部の導電パターン及び前記複数の搭載部が配置された領域を取り囲む一体のダム部に金メッキ層を同一作業で形成する工程と、
前記搭載部の前記導電パターンに、半導体チップを固着する工程と、
前記共通基板の前記ダム部で囲まれた領域に樹脂を供給して、前記複数個の半導体チップを共通の樹脂層で被覆する工程と、
前記樹脂層と前記共通基板とを分割し、前記搭載部を個々に分割する工程とを具備することを特徴とする半導体装置の製造方法。 Preparing a common substrate, and forming a gold plating layer on the integrated dam portion surrounding the conductive pattern of the plurality of mounting portions of the common substrate and the region where the plurality of mounting portions are disposed in the same operation;
A step of fixing a semiconductor chip to the conductive pattern of the mounting portion;
Supplying resin to a region surrounded by the dam portion of the common substrate , and covering the plurality of semiconductor chips with a common resin layer;
A method for manufacturing a semiconductor device, comprising: dividing the resin layer and the common substrate and individually dividing the mounting portion. 前記共通基板がセラミック基板であることを特徴とする請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein the common substrate is a ceramic substrate. 前記共通基板を分割する工程では、前記共通基板の裏面側にシートを貼り付け、前記樹脂層側からダイシングブレードが前記シート表面に到達するように、前記共通基板を分割することを特徴とする請求項１に記載の半導体装置の製造方法。In the step of dividing the common substrate, a sheet is attached to a back surface side of the common substrate, and the common substrate is divided so that a dicing blade reaches the sheet surface from the resin layer side. Item 12. A method for manufacturing a semiconductor device according to Item 1. 前記共通の樹脂層の上面を平坦面に加工する工程をさらに具備することを特徴とする請求項１に記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of processing the upper surface of the common resin layer into a flat surface.
JP29844198A 1998-10-20 1998-10-20 Manufacturing method of semiconductor device Expired - Fee Related JP3710942B2 (en)

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