JP3269025B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3269025B2 JP3269025B2 JP10651998A JP10651998A JP3269025B2 JP 3269025 B2 JP3269025 B2 JP 3269025B2 JP 10651998 A JP10651998 A JP 10651998A JP 10651998 A JP10651998 A JP 10651998A JP 3269025 B2 JP3269025 B2 JP 3269025B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- outer peripheral
- resin layer
- conductor pattern
- peripheral end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特にパッケージ外形を縮小し、実装面積を低減できる半
導体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of reducing a package outer shape and a mounting area.
【０００２】[0002]
【従来の技術】半導体装置の製造におけるパッケージン
グの技術には、金型と樹脂注入によるトランスファーモ
ールドが多用されている。このトランスファーモールド
技術にはリードフレームが用いられており、１本のリー
ドフレームで複数の半導体装置を同時に製造することに
なる。2. Description of the Related Art As a packaging technique in the manufacture of semiconductor devices, a transfer mold using a mold and resin injection is frequently used. A lead frame is used in this transfer molding technique, and a plurality of semiconductor devices are manufactured simultaneously with one lead frame.
【０００３】図６（Ａ）はトランスファーモールド工程
を示す図である。ダイボンド、ワイヤボンドにより半導
体チップ１をリードフレーム２に固着し、上下金型３
Ａ、３Ｂで形成したキャビティ４の内部にリードフレー
ム２を設置し、キャビティ４内にエポキシ樹脂を注入す
ることにより、半導体チップ１の封止が行われる。この
ようなトランスファーモールド工程の後、リードフレー
ム２を各半導体チップ１毎に切断して、個別の半導体装
置が製造される。FIG. 6A is a view showing a transfer molding process. The semiconductor chip 1 is fixed to the lead frame 2 by die bonding and wire bonding.
The semiconductor chip 1 is sealed by placing the lead frame 2 inside the cavity 4 formed by A and 3B and injecting the epoxy resin into the cavity 4. After such a transfer molding step, the lead frame 2 is cut for each semiconductor chip 1 to manufacture an individual semiconductor device.
【０００４】図６（Ｂ）は、トランスファーモールドに
よって製造した半導体装置を示す図である。トランジス
タ等の素子が形成された半導体チップ１がアイランド５
上に半田等のろう材６によって固着実装され、半導体チ
ップ１の電極パッドとリード７とがワイヤ８で接続さ
れ、半導体チップ１の周辺部分が上記キャビティの形状
に合致した樹脂９で被覆され、樹脂９の外部にリード７
の先端部分が導出されたものである。FIG. 6B is a diagram showing a semiconductor device manufactured by transfer molding. The semiconductor chip 1 on which elements such as transistors are formed is an island 5
The semiconductor chip 1 is fixedly mounted thereon with a brazing material 6 such as solder, and the electrode pads of the semiconductor chip 1 and the leads 7 are connected by wires 8. Lead 7 outside resin 9
Are derived.
【０００５】[0005]
【発明が解決しようとする課題】従来のリードフレーム
とトランスファーモールドを用いたパッケージでは、外
部接続用のリード端子を樹脂から突出させるので、リー
ド端子の先端部までの距離を実装面積として考慮しなく
てはならず、樹脂の外形寸法より実装面積の方が遥かに
大きくなるという欠点がある。In a conventional package using a lead frame and transfer mold, a lead terminal for external connection is made to protrude from the resin, so that the distance to the tip of the lead terminal is not considered as a mounting area. However, there is a disadvantage that the mounting area is much larger than the external dimensions of the resin.
【０００６】そのため、外部接続リードに半田バンプな
どを用いることで外形寸法と実装面積とをほぼ等しくす
るような手法や、実装基板上にベアチップを直接ダイボ
ンドする方法等が提案されている。For this reason, there have been proposed methods of using solder bumps or the like for external connection leads to make the external dimensions substantially equal to the mounting area, and a method of directly die-bonding a bare chip onto a mounting substrate.
【０００７】このような命題に対し、本願出願人は、絶
縁基板とダイシング技術を用いることにより、実装面積
を大幅に低減した半導体装置を特願平９−２６２１６０
号に提案した。[0007] In response to such a proposition, the present applicant has proposed a semiconductor device whose mounting area is greatly reduced by using an insulating substrate and dicing technology, as disclosed in Japanese Patent Application No. 9-262160.
No. proposed.
【０００８】斯かる装置は、図７を参照して、第１の絶
縁基板５１に導電パターンによりアイランド部５２とリ
ード部５３を設け、半導体チップ５４をダイボンド、ワ
イヤボンドし、第２の絶縁基板５５の裏面に外部電極５
６を設け、更に第２の絶縁基板５５の４隅に導電メッキ
を施した切り欠き５７を設けて外部電極５６と接続し、
該外部電極５６とアイランド部５２及びリード部５３と
を中間の導電体パターン５８とスルーホール５９とによ
り電気的に接続したものである。パッケージの外形寸法
は金型のキャビティで決めるのではなく、半導体チップ
５４の周囲で樹脂６０と共にダイシングで切断すること
により形成している。これを実装するときは、切り欠き
５７内面に露出する導電メッキ層と共に第２の絶縁基板
５５裏面に形成した外部電極５６を電極として、実装基
板に半田で接着するものである。この構造は、リード端
子が突出しないので、実装面積を大幅に低減する事がで
きる。尚、図７（Ｂ）は図７（Ａ）のＢＢ線断面図であ
る。Referring to FIG. 7, such an apparatus is provided with an island portion 52 and a lead portion 53 by a conductive pattern on a first insulating substrate 51, and a semiconductor chip 54 is die-bonded and wire-bonded to form a second insulating substrate 51. External electrodes 5 on the back of 55
6, and further provided with cutouts 57 provided with conductive plating at four corners of the second insulating substrate 55 and connected to the external electrodes 56,
The external electrode 56 is electrically connected to the island portion 52 and the lead portion 53 by an intermediate conductor pattern 58 and a through hole 59. The external dimensions of the package are not determined by the cavity of the mold, but are formed by dicing the semiconductor chip 54 with the resin 60 around the semiconductor chip 54. When this is mounted, the external electrode 56 formed on the back surface of the second insulating substrate 55 is used as an electrode together with the conductive plating layer exposed on the inner surface of the notch 57, and is bonded to the mounting substrate by soldering. In this structure, since the lead terminals do not protrude, the mounting area can be significantly reduced. FIG. 7B is a sectional view taken along line BB of FIG. 7A.
【０００９】しかしながら、斯かる構造では樹脂６０と
第１の絶縁基板５１の境界部分にアイランド部５２とリ
ード部５３の導電パターンの端面が露出した構造とな
る。導電パターンに用いる金（Au）は半田との塗れ性が
極めて高いため、実装用の半田が前記導電パターンの端
面に達すると半田を吸着してしまい、第１の絶縁基板５
１と樹脂６０との境界に半田が侵入して剥がれ不良を生
じることが明らかになった。However, such a structure has a structure in which the end surfaces of the conductive patterns of the island portion 52 and the lead portion 53 are exposed at the boundary between the resin 60 and the first insulating substrate 51. Since gold (Au) used for the conductive pattern has extremely high wettability with the solder, when the mounting solder reaches the end face of the conductive pattern, the solder is attracted to the first insulating substrate 5.
It has been clarified that the solder penetrates into the boundary between the resin 1 and the resin 60 to cause peeling failure.
【００１０】[0010]
【課題を解決するための手段】本発明は上述した各事情
に鑑みて成されたものであり、第１に、複数の絶縁基板
を貼着して形成した基板上に複数の半導体チップを搭載
し、半導体チップを樹脂層で封止し、半導体チップを囲
むように樹脂と絶縁基板とをダイシング・切断すること
により、装置の外形寸法及び実装面積を大幅に低減でき
る半導体装置を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. First, a plurality of semiconductor chips are mounted on a substrate formed by attaching a plurality of insulating substrates. In addition, the semiconductor chip is sealed with a resin layer, and the resin and the insulating substrate are diced and cut so as to surround the semiconductor chip, thereby providing a semiconductor device capable of greatly reducing the external dimensions and mounting area of the device. is there.
【００１１】第２に、第１の絶縁基板の表面に形成した
導電体パターンを、第１の絶縁基板の外周端面から内側
に後退させることにより、導電体パターンが外周端面に
露出することを防止し、もって実装時のはんだが樹脂層
と第１の絶縁基板との間に吸着される事故を防止するも
のである。Second, the conductor pattern formed on the surface of the first insulating substrate is retreated inward from the outer peripheral end surface of the first insulating substrate, thereby preventing the conductive pattern from being exposed on the outer peripheral end surface. This prevents the solder at the time of mounting from being adsorbed between the resin layer and the first insulating substrate.
【００１２】[0012]
【発明の実施の形態】以下に本発明の実施の形態を詳細
に説明する。Embodiments of the present invention will be described below in detail.
【００１３】図１は本発明の半導体装置を示す（Ａ）平
面図、（Ｂ）ＡＡ線断面図、図２（Ａ）は本発明の半導
体装置を示す斜視図である。この半導体装置は、板厚が
各々１５０〜２５０μのセラミックやガラスエポキシ等
からなる第１と第２の絶縁基板１１ａ、１１ｂと、第１
の絶縁基板１１の上に搭載され、トランジスタ素子など
を形成した半導体チップ１２とを有する。FIG. 1A is a plan view showing a semiconductor device of the present invention, FIG. 1B is a sectional view taken along the line AA, and FIG. 2A is a perspective view showing the semiconductor device of the present invention. This semiconductor device comprises first and second insulating substrates 11a and 11b each made of ceramic or glass epoxy having a thickness of 150 to 250 μm,
And a semiconductor chip 12 on which a transistor element and the like are formed.
【００１４】第１の絶縁基板１１ａの表面には、金メッ
キ層によってアイランド部１３とリード部１４とが形成
されており、第１の絶縁基板１１ａの裏面にも金メッキ
層により中間電極１５、１６が形成されている。中間電
極１５、１６は、アイランド部１３、リード部１４のパ
ターンと同等のパターンを有している。アイランド部１
３とリード部１４の第１の絶縁基板１１ａにはスルーホ
ール１７、１８が設けられており、該スルーホール１
７、１８の内部がタングステン、Ａｇ−Ｐｄ等の導電材
料によって埋設され、これによってアイランド部１３と
中間電極１５、及びリード部１４と中間電極１６とが各
々電気的に接続されている。The island portions 13 and the lead portions 14 are formed on the surface of the first insulating substrate 11a by a gold plating layer, and the intermediate electrodes 15 and 16 are also formed on the back surface of the first insulating substrate 11a by the gold plating layer. Is formed. The intermediate electrodes 15 and 16 have the same pattern as the pattern of the island portion 13 and the lead portion 14. Island part 1
3 and the first insulating substrate 11a of the lead portion 14 are provided with through holes 17 and 18, respectively.
The insides of 7 and 18 are buried with a conductive material such as tungsten or Ag-Pd, so that the island 13 and the intermediate electrode 15 and the lead 14 and the intermediate electrode 16 are electrically connected.
【００１５】第２の絶縁基板１１ｂの裏面には導電パタ
ーンにより外部電極１９、２０が形成されており、この
外部電極１９、２０は第２の絶縁基板１１ｂの終端付近
にまで延在している。第２の絶縁基板１１ｂの４隅に
は、円筒形の４分の１に相当する切り欠き部２１が形成
されており、該切り欠き部２１の内周面にも導電パター
ンが形成されて、外部電極１９、２０と中間電極１５、
１６とが電気的に接続される。結果、トランジスタのベ
ース・コレクタ・エミッタに各々相当する外部電極１
９、２０が形成される。External electrodes 19 and 20 are formed by conductive patterns on the back surface of the second insulating substrate 11b, and these external electrodes 19 and 20 extend to near the end of the second insulating substrate 11b. . At four corners of the second insulating substrate 11b, notches 21 corresponding to a quarter of a cylindrical shape are formed, and a conductive pattern is also formed on the inner peripheral surface of the notches 21. External electrodes 19, 20 and intermediate electrode 15,
16 are electrically connected. As a result, external electrodes 1 corresponding to the base, collector and emitter of the transistor, respectively.
9 and 20 are formed.
【００１６】そして、半導体チップ１２はアイランド部
１３に銀ペーストや金シリコン共晶等の接着剤２２によ
って固着されており、半導体チップ１２表面に形成した
ボンディングパッドとリード部１４とが、ワイヤ２３で
ワイヤボンディングされている。これらの半導体チップ
１２とワイヤ２３を被覆するように、第１の絶縁基板１
１ａの上にエポキシ系の樹脂層２４を形成してこれを封
止し、略直方体のパッケージを形成している。The semiconductor chip 12 is fixed to the island portion 13 by an adhesive 22 such as a silver paste or a gold silicon eutectic, and the bonding pad formed on the surface of the semiconductor chip 12 and the lead portion 14 are connected by wires 23. Wire bonded. The first insulating substrate 1 is formed so as to cover these semiconductor chips 12 and the wires 23.
An epoxy resin layer 24 is formed on 1a and sealed, thereby forming a substantially rectangular parallelepiped package.
【００１７】パッケージの外形は、上面が樹脂層２４に
より、下面が第２の絶縁基板１１ｂの裏面により、そし
て４つの側面が樹脂層２４と第１と第２の絶縁基板１１
ａ、１１ｂの外周端面２５、２６、２７によって各々構
成される。樹脂層２４の外周端面２５と、第１と第２の
絶縁基板１１ａ、１１ｂの外周端面２６、２７とは連続
する同一水平面を成している。The outer shape of the package is such that the upper surface is formed by the resin layer 24, the lower surface is formed by the back surface of the second insulating substrate 11b, and four side surfaces are formed by the resin layer 24 and the first and second insulating substrates 11b.
a and 11b are respectively constituted by outer peripheral end surfaces 25, 26 and 27. The outer peripheral end surface 25 of the resin layer 24 and the outer peripheral end surfaces 26, 27 of the first and second insulating substrates 11a, 11b form a continuous horizontal plane.
【００１８】そして、第１の絶縁基板１１ａの表面に形
成したアイランド部１３とリード部１４の金メッキ層
は、第１の絶縁基板１１ａの外周端面２６には達せず、
第１の絶縁基板１１ａの全周にわたって、その端部から
３０〜７０μの距離だけ後退されている。後退された箇
所には、第１の絶縁基板１１ａの外周端面２６に沿って
半導体チップ１２の周囲を囲むように幅が３０〜７０
μ、深さ１００μ程度の溝２８が形成されている。Then, the gold plating layers of the island portions 13 and the lead portions 14 formed on the surface of the first insulating substrate 11a do not reach the outer peripheral end surface 26 of the first insulating substrate 11a.
The first insulating substrate 11a is set back from the end by a distance of 30 to 70 μ over the entire circumference. The recessed portion has a width of 30 to 70 so as to surround the periphery of the semiconductor chip 12 along the outer peripheral end surface 26 of the first insulating substrate 11a.
A groove 28 having a depth of about μ and a depth of about 100 μ is formed.
【００１９】図２（Ｂ）は、斯かる装置を実装した状態
を示す断面図である。実装基板２９上に形成された回路
網形成用のプリント配線３０に、装置の外部電極１９、
２０を位置あわせして、半田により装置が固着される。
半田は表面張力によって端部に盛り上がって半田フィレ
ット３１を形成する。FIG. 2B is a sectional view showing a state where such a device is mounted. The external electrodes 19 of the device are connected to the printed wiring 30 for forming a circuit network formed on the mounting board 29.
20 is aligned, and the device is fixed with solder.
The solder rises to the end due to surface tension to form a solder fillet 31.
【００２０】本発明の半導体装置であれば、切り欠き部
２１の内面が金メッキ層等の導電パターンで被覆されて
いるので、半田フィレット３１を大きく盛り上げること
ができる。このとき、アイランド部１３とリード部１４
を後退させたことにより、樹脂層２４と第１の絶縁基板
１１ａの境界にこれらの金メッキ層が露出しないので、
半田フィレット３１の半田を吸収することもない。その
ため、樹脂層２４が剥離する事故を回避できる。また、
溝２８を設けたことにより、第１の絶縁基板１１ａと樹
脂層２４との密着面積が増大するので、両者の接着強度
を増大できる。In the semiconductor device of the present invention, since the inner surface of the notch 21 is covered with a conductive pattern such as a gold plating layer, the solder fillet 31 can be greatly raised. At this time, the island 13 and the lead 14
, The gold plated layers are not exposed at the boundary between the resin layer 24 and the first insulating substrate 11a.
The solder of the solder fillet 31 is not absorbed. Therefore, an accident in which the resin layer 24 peels can be avoided. Also,
By providing the groove 28, the contact area between the first insulating substrate 11a and the resin layer 24 increases, so that the bonding strength between the two can be increased.
【００２１】以上に説明した半導体装置は、以下の方法
によって得ることができる。The semiconductor device described above can be obtained by the following method.
【００２２】第１工程：図３（Ａ）参照 まずは装置複数個分に相当する大判の基板３２を準備す
る。この基板３２は、第１と第２の絶縁基板１１ａ、１
１ｂを貼着したものである。第１の絶縁基板１１ａの表
面には金メッキ層によりアイランド１３とリード部１４
に対応するパターンが櫛歯状の連続パターンで描画され
ている。第２の絶縁基板１１ｂの裏面にも同様の連続パ
ターンで外部電極１９、２０に対応する金メッキ層が形
成される。アイランド１３とリード部１４の第１の絶縁
基板１１ａには外部電極１９、２０と電気的接続を取る
ためのスルーホール１７、１８が設けられている。この
段階では、アイランド部１３とリード部１４とは分離し
ていない連続したパターンである。First Step: See FIG. 3A First, a large-sized substrate 32 corresponding to a plurality of devices is prepared. This substrate 32 includes first and second insulating substrates 11a, 11a,
1b. The islands 13 and the lead portions 14 are formed on the surface of the first insulating substrate 11a by a gold plating layer.
Are drawn in a comb-like continuous pattern. A gold plating layer corresponding to the external electrodes 19 and 20 is formed in a similar continuous pattern on the back surface of the second insulating substrate 11b. In the first insulating substrate 11a of the island 13 and the lead portion 14, through holes 17 and 18 for making electrical connection with external electrodes 19 and 20 are provided. At this stage, the island portions 13 and the lead portions 14 are continuous patterns that are not separated.
【００２３】同図において、ダイシングライン３３で囲
まれた領域が１つの半導体装置として後に切り出される
ことになる。そして、ダイシングライン３３の交差する
箇所の第２の絶縁基板１１ｂには、切り欠き２１に相当
するスルーホール３４が設けられている。In the figure, a region surrounded by a dicing line 33 is cut out later as one semiconductor device. Then, a through hole 34 corresponding to the notch 21 is provided in the second insulating substrate 11b at a location where the dicing line 33 intersects.
【００２４】斯かる状態の基板３２にに対して、多数の
半導体チップ１２をダイボンドし、チップ上に形成した
ボンディングパッドとリード部１４とをボンディングワ
イヤ２３で接続する。A large number of semiconductor chips 12 are die-bonded to the substrate 32 in such a state, and the bonding pads formed on the chips and the lead portions 14 are connected by bonding wires 23.
【００２５】第２工程：図３（Ｂ） ダイシングライン３３を中心線として、これに沿うよう
幅５０〜８０μ、深さ約１００μの溝２８を形成する。
溝２８はダイシングブレードを用いて金メッキ層と共に
第１の絶縁基板１１ａ表面をダイシングすることによっ
て形成する。これにより、溝２８を形成すると同時にア
イランド部１３とリード部１４をダイシングライン３３
から後退させることができる。Second step: FIG. 3B With the dicing line 33 as a center line, a groove 28 having a width of 50 to 80 μm and a depth of about 100 μm is formed along the dicing line 33.
The groove 28 is formed by dicing the surface of the first insulating substrate 11a together with the gold plating layer using a dicing blade. As a result, the groove 28 is formed and simultaneously the island portion 13 and the lead portion 14 are connected to the dicing line 33.
Can be retreated.
【００２６】第３工程：図４（Ａ） 第１の絶縁基板１１ａの上にポッティングなどの手法に
より樹脂層２４を形成する。樹脂層２４は半導体チップ
１２を個別に被覆するものではなく、複数の半導体チッ
プ１２を連続した樹脂で一括して被覆する。例えば一枚
の基板３２に５０個の半導体チップ１２を搭載した場合
は、５０個全てのチップを一括して被覆する。Third step: FIG. 4A A resin layer 24 is formed on the first insulating substrate 11a by a technique such as potting. The resin layer 24 does not individually cover the semiconductor chips 12, but collectively covers the plurality of semiconductor chips 12 with a continuous resin. For example, when 50 semiconductor chips 12 are mounted on one substrate 32, all of the 50 chips are collectively covered.
【００２７】第４工程：図４（Ｂ） ダイシングブレード３５により、ダイシングライン３３
に沿って樹脂層２４と第１と第２の絶縁基板１１ａ、１
１ｂを同時に切断し、個々の半導体装置に分離する。こ
の工程では溝２８の幅よりも板厚が狭いダイシングブレ
ードを用いており、これによって第１の絶縁基板１１ａ
の外周端面２６に溝２８を残し、アイランド部１３とリ
ード部１４との金メッキ層が樹脂層２４の外周端面２５
に露出しない構造を得ている。また、ダイシングライン
３３の交差部分に設けたスルーホール３４はダイシング
により４分割されて切り欠き部２１を形成する。更に、
ダイシングによってパッケージの４つの側面を構成する
ことにより、それらの切断面（外周端面２５、２６、２
７）が同一平面で構成される。Fourth step: FIG. 4B A dicing line 33 is formed by a dicing blade 35.
Along the resin layer 24 and the first and second insulating substrates 11a, 11a
1b is simultaneously cut and separated into individual semiconductor devices. In this step, a dicing blade having a plate thickness smaller than the width of the groove 28 is used, so that the first insulating substrate 11a
A groove 28 is left in the outer peripheral end surface 26 of the resin layer 24 and the gold plating layer of the island portion 13 and the lead portion 14
A structure that is not exposed to light is obtained. Further, the through hole 34 provided at the intersection of the dicing lines 33 is divided into four by dicing to form the cutout portions 21. Furthermore,
By forming the four side surfaces of the package by dicing, their cut surfaces (outer peripheral end surfaces 25, 26, 2
7) is configured on the same plane.
【００２８】以上の方法によって製造された半導体装置
は、以下のメリットを有する。The semiconductor device manufactured by the above method has the following advantages.
【００２９】多数個の素子をまとめて樹脂でパッケージ
ングするので、個々にパッケージングする場合に比べ
て、無駄にする樹脂材料を少なくでき。材料費の低減に
つながる。Since a large number of elements are packaged together with a resin, the amount of wasted resin material can be reduced as compared with the case where individual elements are packaged. This leads to a reduction in material costs.
【００３０】モールド金型とリードフレームとの位置合
わせ精度がプラス・マイナス５０μ程度であるのに対し
て、ダイシング装置の位置あわせ精度はプラス・マイナ
ス１０μ程度と精度が高い。従って樹脂外形をダイシン
グで形成すれば、アイランド部１３から樹脂２１の切断
面までの肉厚を薄くして、より外形寸法の小さなパッケ
ージを得ることができるほか、同じ外形寸法で比較すれ
ばアイランド部１３の面積を増大して、搭載可能な半導
体チップ１２を大型化できる。While the positioning accuracy between the mold and the lead frame is about ± 50 μm, the positioning accuracy of the dicing apparatus is as high as ± 10 μm. Therefore, if the resin outer shape is formed by dicing, the thickness from the island portion 13 to the cut surface of the resin 21 can be reduced, and a package having a smaller outer size can be obtained. The area of the semiconductor chip 12 can be increased by increasing the area of the semiconductor chip 12.
【００３１】尚、ダイシングで溝２８を形成する手段に
代えて、アイランド部１３とリード部１４のパターンを
形成する際に、あらかじめダイシングライン２６から後
退させたパターンで形成することでも同様の構造を得る
ことができる。Incidentally, instead of the means for forming the groove 28 by dicing, a similar structure can be obtained by forming the pattern of the island portion 13 and the lead portion 14 with a pattern which has been set back from the dicing line 26 in advance. Obtainable.
【００３２】更に図５に示したように、溝２８の形成と
同時的にアイランド部１３とリード部１４との間の空白
部分にも溝２８ａを形成することにより、樹脂との密着
強度を更に向上することも可能である。Further, as shown in FIG. 5, by simultaneously forming the groove 28, a groove 28a is also formed in a blank portion between the island portion 13 and the lead portion 14, thereby further increasing the adhesive strength with the resin. It can be improved.
【００３３】本実施形態では、半導体チップ１２にトラ
ンジスタを形成したが、縦型或いは比較的発熱量の少な
い横型のデバイスであればこれに限らず、例えば、パワ
ーＭＯＳＦＥＴ、ＩＧＢＴ、ＨＢＴ等のデバイスを形成
した半導体チップであっても、本発明に応用ができるこ
とは説明するまでもない。In this embodiment, the transistor is formed on the semiconductor chip 12. However, the present invention is not limited to a vertical device or a horizontal device that generates a relatively small amount of heat. It is needless to say that the formed semiconductor chip can be applied to the present invention.
【００３４】[0034]
【発明の効果】以上に説明したように、本発明によれ
ば、リードフレームを用いた半導体装置よりも更に小型
化できるパッケージ構造を提供できる利点を有する。こ
のとき、リード端子が突出しない構造であるので、実装
したときの占有面積を低減し、高密度実装を実現でき
る。As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size than a semiconductor device using a lead frame. At this time, since the lead terminals do not protrude, the area occupied by mounting is reduced, and high-density mounting can be realized.
【００３５】更に、切り欠き部２１によって半田フィレ
ット３１が容易に盛り上がる構造にできる。このとき、
第１の絶縁基板１１ａと樹脂層２４との境界部分に金メ
ッキ層が露出しない構成としたので、実装時の半田が境
界部分に接触・吸い込まれて樹脂層２４が剥離する事故
を回避することができる。Further, a structure in which the solder fillet 31 is easily raised by the notch 21 can be provided. At this time,
Since the gold plating layer is not exposed at the boundary between the first insulating substrate 11a and the resin layer 24, it is possible to avoid an accident in which the solder at the time of mounting comes into contact with the boundary and is sucked and the resin layer 24 peels off. it can.
【００３６】加えて、第１の絶縁基板１１ａの外周部分
に溝２８を形成することにより、第１の絶縁基板１１ａ
と樹脂層２４との密着力を増大できる他、溝２８をダイ
シングで形成することにより、金メッキ層の後退と溝２
８の形成を同時的に実施することができる。く寄与する
ことができる。In addition, by forming a groove 28 in the outer peripheral portion of the first insulating substrate 11a, the first insulating substrate 11a
In addition to increasing the adhesive strength between the metal layer and the resin layer 24, the recess 28 is formed by dicing, so that the gold plating layer is recessed and the groove 2 is formed.
8 can be performed simultaneously. Can contribute significantly.
【図１】本発明の半導体装置を示す（Ａ）平面図、
（Ｂ）断面図である。FIG. 1A is a plan view showing a semiconductor device of the present invention,
(B) It is sectional drawing.
【図２】本発明の半導体装置を示す（Ａ）斜視図、
（Ｂ）断面図である。FIG. 2A is a perspective view showing a semiconductor device of the present invention,
(B) It is sectional drawing.
【図３】本発明の半導体装置の製造方法を説明する図で
ある。FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.
【図４】本発明の半導体装置の製造方法を説明する図で
ある。FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to the present invention.
【図５】他の実施の形態を説明する（Ａ）平面図、
（Ｂ）断面図である。FIG. 5A is a plan view illustrating another embodiment,
(B) It is sectional drawing.
【図６】従来の半導体装置を説明する断面図である。FIG. 6 is a cross-sectional view illustrating a conventional semiconductor device.
【図７】半導体装置を示す（Ａ）平面図、（Ｂ）断面図
である。7A is a plan view and FIG. 7B is a cross-sectional view illustrating a semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平８−8354（ＪＰ，Ａ) 特開 平11−163200（ＪＰ，Ａ) 特開 平４−53237（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 23/48 H01L 21/56 H01L 23/28 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-8354 (JP, A) JP-A-11-163200 (JP, A) JP-A-4-53237 (JP, A) (58) Survey Field (Int.Cl. 7 , DB name) H01L 23/12 H01L 23/48 H01L 21/56 H01L 23/28
Claims (5)
の絶縁基板と、 前記第１の絶縁基板の表面に導電体パターンによって形
成したアイランド部、及びリード部と、 前記アイランド部に搭載した半導体チップと、 前記半導体チップの電極と前記リード部とを電気的に接
続する手段と、 前記第１の絶縁基板の上に設けられて前記半導体チップ
及び前記アイランド部と前記リード部とを被覆する樹脂
層と、 前記第１の絶縁基板と第２の絶縁基板の間に設けた中間
電極と、 前記第２の絶縁基板の裏面側に形成され、前記アイラン
ド部またはリード部と前記中間電極を介して電気的に接
続された外部電極と、 前記第２の絶縁基板の角部に設けられ、その表面に前記
外部電極と連続する導電パターンが設けられた切り欠き
部と、 前記第１と第２の絶縁基板の外周端面と、 前記樹脂層の外周端面とを具備し、 前記第１と第２の絶縁基板の外周端面と前記樹脂層の外
周端面とがほぼ一致し、 前記アイランド部と前記リード部の導電体パターンが前
記外周端面より内側に位置し、 前記外周端面付近では前記第１の絶縁基板の素材と前記
樹脂層とが密着していることを特徴とする半導体装置。1. A first and a second means for attaching and forming a support substrate.
An insulating substrate, an island portion formed by a conductor pattern on the surface of the first insulating substrate, and a lead portion; a semiconductor chip mounted on the island portion; and an electrode of the semiconductor chip and the lead portion. Means for electrically connecting; a resin layer provided on the first insulating substrate to cover the semiconductor chip, the island portion, and the lead portion; and the first insulating substrate and the second insulating substrate An intermediate electrode provided between the second insulating substrate and an external electrode formed on the back surface of the second insulating substrate and electrically connected to the island portion or the lead portion via the intermediate electrode; A notch portion provided at a corner of the substrate and provided on its surface with a conductive pattern continuous with the external electrode; an outer peripheral end surface of the first and second insulating substrates; and an outer peripheral end surface of the resin layer. Ingredient An outer peripheral end surface of the first and second insulating substrates substantially coincides with an outer peripheral end surface of the resin layer; the conductor pattern of the island portion and the lead portion is located inside the outer peripheral end surface; A semiconductor device, wherein a material of the first insulating substrate and the resin layer are in close contact with each other near an end face.
第２の絶縁基板とを同時に切断した切断面で構成されて
いることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said outer peripheral end surface is constituted by a cut surface obtained by cutting said resin layer and said first and second insulating substrates at the same time.
を設けたことを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein a groove is provided near an outer peripheral end surface of said first insulating substrate.
るための導電体パターンを形成した第１の絶縁基板と、
外部接続用の外部電極を形成した第２の絶縁基板とを、
前記導電体パターンと前記外部電極とが電気的に接続さ
れるように貼着し、大判の基板を構成する工程と、 前記導電体パターンを前記第１の絶縁基板の端から後退
させる工程と、 前記導電体パターンに半導体チップを固着する工程と、 前記半導体チップを被覆するように前記第１の絶縁基板
の上部を樹脂層で被覆する工程と、 前記半導体チップの周囲で、前記樹脂層と前記第１と第
２の絶縁基板とを切断して前記半導体素子を個々に分離
する工程と、を具備することを特徴とする半導体装置の
製造方法。4. A first insulating substrate having a surface on which a conductor pattern for forming a plurality of semiconductor elements is formed;
A second insulating substrate on which external electrodes for external connection are formed;
Adhering the conductor pattern and the external electrode so as to be electrically connected to each other to form a large-sized substrate; andretreating the conductor pattern from an end of the first insulating substrate; A step of fixing a semiconductor chip to the conductor pattern; a step of coating an upper part of the first insulating substrate with a resin layer so as to cover the semiconductor chip; Cutting the first and second insulating substrates to individually separate the semiconductor elements.
基板の表面をダイシングすることにより、前記導電体パ
ターンをパッケージ外周予定部位より後退させたことを
特徴とする請求項４記載の半導体装置の製造方法。5. The semiconductor device according to claim 4, wherein said conductor pattern is retracted from a predetermined portion of a package outer periphery by dicing a surface of said first insulating substrate together with said conductor pattern. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10651998A JP3269025B2 (en) | 1998-04-16 | 1998-04-16 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10651998A JP3269025B2 (en) | 1998-04-16 | 1998-04-16 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11307673A JPH11307673A (en) | 1999-11-05 |
| JP3269025B2 true JP3269025B2 (en) | 2002-03-25 |
Family
ID=14435663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10651998A Expired - Fee Related JP3269025B2 (en) | 1998-04-16 | 1998-04-16 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3269025B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3871820B2 (en) * | 1998-10-23 | 2007-01-24 | ローム株式会社 | Semiconductor light emitting device |
| JP4711483B2 (en) * | 2000-01-11 | 2011-06-29 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP4651152B2 (en) * | 2000-03-27 | 2011-03-16 | 京セラ株式会社 | Multi-cavity ceramic wiring board |
| JP4149377B2 (en) | 2001-06-07 | 2008-09-10 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| JP4822484B2 (en) * | 2001-06-19 | 2011-11-24 | シチズン電子株式会社 | Surface mount type electronic component and manufacturing method thereof |
| JP4959071B2 (en) * | 2001-07-04 | 2012-06-20 | ローム株式会社 | Surface mount semiconductor device |
| JP2004087882A (en) * | 2002-08-28 | 2004-03-18 | Sanyo Electric Co Ltd | Semiconductor device |
| JP4831958B2 (en) * | 2004-12-06 | 2011-12-07 | スタンレー電気株式会社 | Surface mount type LED |
| US7933128B2 (en) | 2007-10-10 | 2011-04-26 | Epson Toyocom Corporation | Electronic device, electronic module, and methods for manufacturing the same |
| KR101142987B1 (en) | 2011-02-21 | 2012-05-08 | 한성대학교 산학협력단 | Flexible electronic circuits and preparation method thereof |
-
1998
- 1998-04-16 JP JP10651998A patent/JP3269025B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11307673A (en) | 1999-11-05 |
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