JP2000091365A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a compact package, whose mounting area is reduced and to provide a semiconductor substrate for which handling in manufacturing is improved. SOLUTION: First and second insulating substrates 21a and 21b are attached and are made as an insulating substrate 21. An island part 24a is formed on the surface of the first insulating substrate 21. Inner electrodes 24b and 24c are formed on the surface of the second insulating substrate 24b. The upper part is covered with a resin layer 23. Side surfaces 23a-23d of a package are constituted of the cutting surfaces. At the side surfaces 23a-23d, outer-surface end planes 30 and 31 of the first and second insulating substrates 21a and 21b are exposed, and the same plane is formed. At the part where a semiconductor chip 22 is mounted, the insulating substrate 21 has the thin plate thickness t1. On the other part, a thick plate thickness (t1+t2) is provided. The second insulating substrate 21b forming the thick plate thickness is elongated along one side of the semiconductor chip 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, which can reduce a package outer shape to reduce a mounting area, and further reduce waste of materials involved in manufacturing.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor device, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip fixed on the lead frame is sealed by a transfer mold using a mold and resin injection. In addition, a process of separating a sealed semiconductor chip into individual semiconductor devices has been performed. A strip-shaped or hoop-shaped frame is used as the lead frame. In any case, a plurality of semiconductor devices are simultaneously sealed in one sealing step.

FIG. 8 is a diagram showing a state of a transfer molding process. In the transfer molding process,
The lead frame 2 to which the semiconductor chip 1 is fixed by die bonding or wire bonding is placed inside the cavity 4 formed by the upper and lower molds 3A and 3B, and the epoxy resin is injected into the cavity 4 so that the semiconductor chip 1 Sealing is performed. After such a transfer molding process, the lead frame 2 is cut for each semiconductor chip 1 to manufacture an individual semiconductor device (for example, Japanese Patent Laid-Open No.
-129473).

At this time, as shown in FIG. 9, a plurality of cavities 4a to 4d, a resin source 5 for injecting a resin, a runner 6, and each of the cavities 4a Gate 7 for pouring resin into 4d
Are provided. These are all grooves provided on the surface of the mold 3. In the case of a strip-shaped lead frame, for example, ten semiconductor chips 1 are mounted on one lead frame, and ten cavities 4 and ten gates 7 correspond to one lead frame. And one runner 6 is provided. A cavity 4 for, for example, 20 lead frames is provided on the surface of the mold 3.

FIG. 10 is a diagram showing a semiconductor device manufactured by the above transfer molding. A semiconductor chip 1 on which elements such as transistors are formed is fixedly mounted on an island 8 of a lead frame by a brazing material 9 such as solder, and electrode pads of the semiconductor chip 1 and leads 10 are connected by wires 11. Is coated with a resin 12 conforming to the shape of the cavity,
The tip of the lead terminal 10 is led out of the resin 12.

[0006]

In the conventional package, since the lead terminals 10 for external connection are projected from the resin 12, the distance to the tip of the lead terminals 10 must be considered as a mounting area. There is a disadvantage that the mounting area is much larger than the outer dimensions of the resin 12.

In the transfer molding technique,
The resin is cured in the runner 6 and the gate 7 because the resin is cured while the pressure is continuously applied.
Residual resin is disposed of. Therefore, in the method using the above-described lead frame, the gate 7 is provided for each semiconductor device to be manufactured, so that the use efficiency of the resin is low,
There is a disadvantage that the number of semiconductor devices that can be manufactured is small relative to the amount of resin.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional disadvantages, and comprises an insulating substrate having a thick portion and a thin portion, and a semiconductor chip fixed on the thin portion. And a conductive pattern drawn on the surface of the thick portion,
Means for connecting an electrode of the semiconductor chip to the conductive pattern, and an insulating resin for covering an upper portion of the insulating substrate including the semiconductor chip, wherein an outer peripheral end surface of the insulating substrate and an outer peripheral end surface of the insulating resin are provided. Are the same plane, these constitute side surfaces of the package outer shape, the thick portion is provided along one side of the insulating substrate, and the thin portion extends on the other three sides. It is assumed that.

[0009]

Embodiments of the present invention will be described below in detail.

FIG. 1A is a sectional view showing a semiconductor device of the present invention, FIG. 1B is a plan view thereof, FIG. 2A is a perspective view of the device as viewed from above, and FIG. () Is a perspective view of the apparatus as viewed from below.

Referring to FIGS. 1 and 2, this semiconductor device comprises an insulating substrate 21 on which first and second insulating substrates 21a and 21b are adhered, and a transistor fixed on first insulating substrate 21a. The semiconductor device includes a semiconductor chip 22 on which elements and the like are formed, and a resin layer 23 for sealing the entirety including the semiconductor chip 22.

The first insulating substrate 21a has a thickness (FIG. 1: t
1) is a substrate made of ceramic or glass epoxy of 50 to 200 μm, the surface of which is provided with an island portion 24 a by a gold plating layer, and the back surface of which is also formed by an external electrode 25 a by the same gold plating layer.
The first insulating substrate 21a is provided with a through hole 26a penetrating the first insulating substrate 21a, and the inside of the through hole 26a is buried with a conductive material such as tungsten or Ag-Pd so that the island portion 24 and the external electrode 25a are formed. It is electrically connected.

The second insulating substrate 11b has a thickness (FIG. 1: t
2) is a substrate of 100 to 250 μm made of ceramic, glass epoxy, or the like, which has a size excluding a region where the semiconductor chip 22 is to be mounted, and is bonded and integrated with the first insulating substrate 21a. Internal electrodes 24b and 24c are formed on the surface of the second insulating substrate 21b by a gold plating layer. The lower first insulating substrate 21a and the second insulating substrate 21b have through holes 26 therethrough.
b, 26c are provided, and the through holes 26b, 26c are provided.
Is embedded with a conductive material such as tungsten, Ag-Pd, or Au, and the internal electrodes 24b and 24c are electrically connected to external electrodes 25b and 25c provided on the back surface of the first insulating substrate 21a.

The semiconductor chip 22 includes a first insulating substrate 21a.
Adhesive 27 such as Ag paste on the island portion 24a
The electrode pads 28 on the surface of the semiconductor chip 22 and the internal electrodes 24b and 24c formed on the surface of the second insulating substrate 21b are wire-bonded by gold wires 29, respectively. As a result, the external electrode 25a becomes a collector electrode, and the external electrodes 25b and 25c become base and emitter electrodes. Then, an epoxy-based insulating resin layer 23 covers the insulating substrate 21 on which the die bonding and the wire bonding have been performed to seal the semiconductor chip 22 and form a substantially rectangular parallelepiped package.

At least four side surfaces 23a to 23d of the outer shape of the package are constituted by cut surfaces irrespective of the mold surface. Outer peripheral end surface 30 of first insulating substrate 21a
One of the outer peripheral end surfaces 31 of the second insulating substrate 21b is exposed on the surface of the resin layer 23, and the side surface 23a of the resin layer 23,
23b, 23c and 23d form the same continuous plane. These are composed of the resin layer 23 and the insulating substrates 21a, 21b.
Are simultaneously formed in a cutting step, for example, by a dicing blade.

The second insulating substrate 21b is a semiconductor chip 2
2 extend at a constant width along the side surface 23d corresponding to one side. The end portions are in contact with the side surfaces 23b and 23c adjacent to the side surface 23d, and two sides of the outer peripheral end surface 31 of the second insulating substrate 21b are exposed on the side surfaces 23b and 23c. The remaining one of the outer peripheral end surfaces 31 of the second insulating substrate 21b is buried in the resin layer 23.

Since the semiconductor device of the present invention has a structure in which the external electrodes 25a, 25b, and 25c do not protrude beyond the outer dimensions of the package, the size of the semiconductor device can be further reduced as compared with a semiconductor device using a lead frame. The occupation area when mounting is reduced, and high-density mounting can be realized.

Further, the gold plating layers of the island portions 24a and the internal electrodes 24b and 24c formed on the surface of the insulating substrate 21 do not reach the side surfaces 23a to 23d of the resin layer 23, but extend over the entire periphery of the insulating substrate 21. From a distance of 30-70μ. Also, the first insulating substrate 21a
The external electrodes 25a, 25b, 25c formed on the back surface of
It is retracted from the outer peripheral end surface 30 of the first insulating substrate 21a. This configuration offers two advantages.

One of the advantages is that the sides 23a, 23b, 23
Obtained when c and 23d are cut with a dicing blade. That is, a gold plating layer having excellent properties as a conductive material is a material having excellent ductility at the same time. for that reason,
When the gold-plated layer is cut by a dicing blade, the gold-plated layer is elongated by the blade, and burrs are generated, which results in poor appearance. Such an accident can be prevented by not contacting the dicing blade.

Two advantages are obtained when the above semiconductor device is mounted on a printed circuit board. That is, when the above-described semiconductor device is mounted, the external electrodes 25a of the first insulating substrate 21a are attached to the conductive patterns formed on the printed circuit board.
25b and 25c are positioned and installed, and they are fixed by soldering, but gold has the characteristic of extremely high wettability to solder. Therefore, when the gold plating layer is exposed on the side surfaces 23a to 23d of the package and comes into contact with the solder, the solder enters the interface between the insulating substrate 21 and the resin layer 23, causing an accident such as resin peeling or electrical short circuit. Such an accident can be prevented by not exposing the gold plating layer on the side surface of the package.

In the semiconductor device of the present invention, the side surfaces 23a to 23b of the package outer shape are formed by cut surfaces.
That is, the semiconductor chip 22 is used with the insulating substrate 21 as a supporting substrate.
Is mounted, molded, and then cut. Therefore, the above semiconductor device is obtained by cutting from one large-sized insulating substrate.

Thus, the first gist of the present invention is that the insulating substrate 21 where the semiconductor chip 21 is mounted has a small thickness.
In addition, it has a thick part. In the above example, a difference in plate thickness is realized by laminating two substrates. That is, the portion on which the semiconductor chip 22 is mounted is constituted by the thickness t1 of the first insulating substrate 21a, and the internal electrodes 24 are formed.
b and 24c are located on the first and second insulating substrates 2
It is composed of the sum (t1 + t2) of the plate thicknesses of 1a and 21b. Such a difference in plate thickness is an important factor in maintaining the mechanical strength in manufacturing using the above-described large-sized insulating substrate and in reducing the size of the semiconductor device.

That is, by partially thinning the portion on which the semiconductor chip 22 is mounted, it is possible to keep the overall height of the semiconductor device (t3 in FIG. 1) low. At this time, the thin plate thickness t1 is set to be smaller than the thickness that maintains the mechanical strength that can be handled when the substrate is flowed in the production line. Specifically, the plate thickness is set to 50 to 200 μ. If the entire large-sized insulating substrate is made to have this thickness, the substrate is easily broken and handling in manufacturing becomes difficult.

To deal with this difficulty in handling, the thickness is increased except for the portion where the semiconductor chip 22 is mounted (t1).
+ T2) enhances the overall mechanical strength.
Specifically, a second insulating substrate 21b having a thickness equal to or greater than the thickness of the first insulating substrate 21a is attached to make the overall thickness 150 μ or more, for example, 300 μ. Therefore, the large-sized insulating substrate has a thick second plate thickness (t1 + t2) and a locally thin first plate thickness (t1).
Since it has only 1), it is possible to have sufficient mechanical strength for manufacturing.
After the molding with the resin layer 23, the resin layer 23 maintains the mechanical strength.

Further, by increasing the thickness of the portion where the internal electrodes 24b and 24c are provided,
Electrode pad 28 on semiconductor chip 22 and internal electrode 24
The heights of b and 24c can be approximated. Thereby, the bondability of the wire can be improved in the wire bonding step, and a contact accident with the semiconductor chip 23 due to the “drip” of the wire 29 can be avoided.

The second gist of the present invention is the second insulating substrate 2
1a extends only along the side surface 23d. This has a close relationship with the suction collet that transports the semiconductor chip 22 when manufacturing the product of the present invention.

That is, referring to FIG. 1, the suction collet 50 has a pyramid-shaped inclined surface 51 on the inner side, and the inclined surface 51 is brought into line contact with the upper end of the semiconductor chip 22 by using a vacuum suction device (not shown). Is a tool for sucking and holding the semiconductor chip 22 by reducing the air pressure between the suction collet 50 and the semiconductor chip 22.
This is a tool used in the step of die bonding on 4a.

The suction collet has a larger dimension than the function of holding the semiconductor chip 22. For example, the suction collet 50 for conveying the semiconductor chip 22 of 0.35 × 0.35 mm is 0.55 × 0. It has an outer dimension of .55 mm. At the time of the die bonding, if the suction collet 50 collides with the second insulating substrate 21b, die bonding becomes impossible. Therefore, the distance 52d between the semiconductor chip 22 and the second insulating substrate 21b is a distance that can avoid the collision. is necessary.

Therefore, by arranging the second insulating substrate 21b so as to be limited to only one of the four sides of the semiconductor chip 22, the semiconductor chip 22 and the side surfaces 23a, 23b, and 23c are separated from each other. Distances 52a, 52b, 52
shorten c. For example, considering a configuration in which the second insulating substrate 21b surrounds the semiconductor chip 22 in an annular shape, the resin layer 2
It can be easily understood that the outer dimensions of No. 3 increase. The relationship between the distance 52d and the distances 52a, 52b, 52c is substantially equal or the distance 52d is larger.

Hereinafter, a method for manufacturing the above-described semiconductor device will be described.

First Step: See FIGS. 3, 4A and 4B First, a large-sized substrate 32 corresponding to, for example, 100 devices as shown in FIG. 3 is prepared. This substrate 32 has a first
And the second insulating substrates 21a and 21b. A large number of through holes 33 corresponding to a plurality of semiconductor chips, for example, every four semiconductor chips are regularly provided in the second insulating substrate 21b. Exposed. Therefore, the thickness of the through hole 33 is small (t1), whereas the other regions have a large thickness (t1 + t2).

FIG. 4 shows an enlarged plan view (A) and a sectional view (B) of the large-size substrate 32. On the surface of the first insulating substrate 21a exposed to the through hole 33 of the second insulating substrate 21b, an island 24a is formed by a gold plating layer. Second
Internal electrodes 24b and 24c are drawn by a gold plating layer on the surface of the insulating substrate 21b. First insulating substrate 21
The gold plating pattern corresponding to the external electrode 25 is drawn on the back surface of a. In the figure, a region surrounded by a line 34 'is cut out later as one semiconductor device.

Second step: See FIGS. 5A and 5B. The semiconductor chip 22 is placed on the large substrate 32 in this state.
Is die-bonded. First, the adhesive 27 is supplied onto the island portion 24 a inside the through hole 33, and the semiconductor chip 22 is transported and fixed on the island portion 24 a by the suction collet 50. The through hole 33 has a size that can accommodate the suction collet 50.

In a dicing step performed after this step, a region surrounded by the dicing line 34 is cut out as one semiconductor device. Dicing blade 35 of constant width
And the center line of the dicing blade 35 is aligned with the dicing line 34, so that the outer shape 53 of the semiconductor device is located inside the dicing line 34.

Third step: See FIG. 6 Bonding pads 28 formed on the semiconductor chip 22
And the internal electrodes 24b and 24c are connected to the bonding wires 29.
Wire bond.

Fourth step: see FIG. 7 A resin layer 23 is formed on a large-sized substrate 32 and molded so as to cover the entire die-bonded semiconductor chip 22. The mold is supplied and cured by potting, or is molded by an upper and lower mold having one cavity for one large-sized substrate 32.
The resin layer 23 does not individually cover the semiconductor chips 22 but collectively covers a plurality of semiconductor chips 22 with a continuous resin. For example, one large-format substrate 32 has 100
When the semiconductor chips 22 are mounted, all 100 chips are collectively covered. The amount of wasted resin in potting is extremely small. Further, even in the case of transfer molding using a mold, only one gate is required for 100 devices, so that the amount of waste is small.

Fourth Step: See FIGS. 6 and 7 Referring again to FIG. 7, the resin layer 23 and the first and second insulating substrates are cut along the dicing line 34 by a dicing blade 35 having a width of 100 to 300 μm. 21a and 21b are cut at the same time and separated into individual semiconductor devices. The side surfaces 23a to 23b of the individual semiconductor devices are formed by dicing in this step, and the outer peripheral end surfaces 30, 31 of the first and second insulating substrates 21a, 21b are exposed on the cut surface and are the same as the resin layer 23. Form a plane.

The semiconductor device manufactured by the above method has the following advantages.

Since a large number of elements are packaged together with a resin, the amount of wasted resin material can be reduced as compared with the case of packaging individually. This leads to a reduction in material costs.

While the positioning accuracy between the mold and the lead frame is approximately ± 50 μm, the positioning accuracy of the dicing device is as high as ± 10 μm. Therefore, by forming the resin outer shape by dicing, it is possible to obtain a package having a smaller outer size than before.

The entire large-size substrate 32 has a relatively large thickness (t1).
+ T2) and only the plate thickness (t1) of the island portion 24a is reduced, so that the large-size substrate 32 is prevented from being cracked or chipped in the manufacturing process, and is easily handled.
Since the mounting position of the semiconductor chip 22 is concave, there is an advantage that the height (t3) of the device can be kept low and a small package can be manufactured. The inventor of the present application has determined that a vertical x
A small package transistor of 1.0 mm × 0.5 mm × 0.5 mm in width × height was realized.

In the above embodiment, the thin plate and the thick plate are formed using two substrates. For example, a bottomed hole is formed at a position corresponding to the through hole 33 on one substrate. A substrate provided with a difference in plate thickness may be used.

[0043]

As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size than a semiconductor device using a lead frame. At this time, since the lead terminals do not protrude, the area occupied by mounting is reduced, and high-density mounting can be realized.

Furthermore, since a large number of semiconductor chips 22 are collectively molded with the continuous resin layer 23, the amount of resin consumed per device can be saved, and waste can be reduced.

Further, by forming a thickness difference between the first insulating substrate 21a and the second insulating substrate 21b, the height (t3) of the outer shape of the device can be suppressed and a small package can be realized. There is an advantage that the handling of the substrate 32 is facilitated and the bondability of the wire bond can be improved.

Further, since the second insulating substrate 21b extends along one side of the chip without surrounding the entire semiconductor chip 22, the interference of the suction collet 50 in the die bonding step is avoided. This has the advantage that the overall dimensions of the device can be reduced.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view taken along the line AA, and FIG. 1B is a plan view showing a semiconductor device of the present invention.

FIG. 2 is a perspective view showing a semiconductor device of the present invention.

FIG. 3 is a perspective view illustrating a manufacturing method of the present invention.

FIG. 4A is a plan view illustrating a manufacturing method of the present invention,
(B) It is sectional drawing.

FIG. 5A is a plan view illustrating a manufacturing method of the present invention,
(B) It is sectional drawing.

FIG. 6A is a plan view illustrating a manufacturing method of the present invention,
(B) It is sectional drawing.

FIG. 7 is a perspective view illustrating a manufacturing method of the present invention.

FIG. 8 is a cross-sectional view illustrating a conventional example.

FIG. 9 is a plan view illustrating a conventional example.

FIG. 10 is a cross-sectional view illustrating a conventional example.

 ────────────────────────────────────────────────── ─── Continued on front page (72) Inventor Takao Shibuya 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5F044 AA02 JJ03 5F061 AA01 BA03 CA21 CB13

Claims (6)

[Claims] An insulating substrate having a portion having a first plate thickness, a portion having a second plate thickness sufficient to maintain mechanical strength, and a portion having a first plate thickness. A semiconductor chip fixed thereon, a conductive pattern drawn on a surface of the portion having the second plate thickness, means for connecting an electrode of the semiconductor chip to the conductive pattern, and the insulating including the semiconductor chip An insulating resin covering an upper portion of the substrate, wherein an outer peripheral end surface of the insulating substrate and an outer peripheral end surface of the insulating resin are flush with each other, and these constitute side surfaces of the package outer shape; Wherein a portion having the following is provided only along one side of the semiconductor chip. 2. An insulating substrate to which two insulating substrates, a first insulating substrate and a second insulating substrate, are adhered, wherein the first plate thickness is the plate thickness of the first insulating substrate. 2. The semiconductor device according to claim 1, wherein the thickness of the first and second insulating substrates is the sum of the thicknesses of the first and second insulating substrates. 3. The semiconductor device according to claim 1, wherein said first and second conductive patterns are recessed inward from an outer peripheral end of said insulating substrate. 4. A step of preparing an insulating substrate having a portion having a first plate thickness and a portion having a second plate thickness sufficient to maintain mechanical strength; Adsorbing, transporting, repeating the step of fixing the semiconductor chip at the first thickness, and the step of fixing the semiconductor chip a plurality of times;
A step of fixing a plurality of semiconductor chips at the first thickness, and a step of electrically connecting an electrode of the semiconductor chip and a conductive pattern formed at the second thickness. Covering the upper portion of the insulating substrate with an insulating resin, sealing the plurality of semiconductor chips with a common resin layer, and insulating the insulating substrate and the insulating resin with the second plate thickness. Separating the plurality of semiconductor chips individually such that the substrate remains only along one side of the semiconductor chip. 5. An insulating substrate to which two insulating substrates, a first insulating substrate and a second insulating substrate, are adhered. The first thickness is the thickness of the first insulating substrate. 5. The method according to claim 4, wherein the thickness of the first and second insulating substrates is the sum of the thicknesses of the first and second insulating substrates. 6. The method for manufacturing a semiconductor device according to claim 4, wherein said separating step is cutting with a dicing blade.