JPH11176856A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor device whose effective area rate is improved in the case of mounting. SOLUTION: A lead frame 30 having at least islands 33 and lead terminals 34 is prepared. A matching mark 37 is made in advance to the frame 32 of the lead frame 30. Die-bonding and wire-bonding are applied to each semiconductor chip 39, and the entire semiconductor chips 39 are molded by a resin in common. Resin 41 on the rear side is partially removed to expose a metal surface at a position of an external connection electrode. The matching marks 37 of the frame 32 are used to cut off the resin 41 to surround each semiconductor ship 39 and the individual semiconductor devices are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of improving a mounting efficiency by reducing a mounting area.

[0002]

2. Description of the Related Art When manufacturing semiconductor elements such as ICs and discrete elements, a sealing technique as shown in FIG. 9A is mainly used. That is, the semiconductor chip 1 is mounted (die-bonded) on the island 2, and the lead terminals 3 arranged around the semiconductor chip 1 and the base electrode and the emitter electrode of the transistor element are respectively bonded to the bonding wires 4.
The semiconductor chip 1 and the lead terminals 3 are completely covered and protected by transfer molding of the semiconductor chip 1 with a thermosetting resin 4 such as an epoxy resin. The lead terminal 3 led out of the resin 5 is bent in a Z-shape and is suitable for surface mounting applications.

For example, when a semiconductor chip 1 on which an NPN transistor element is formed is sealed, a semiconductor device having a three-terminal structure using an island 2 as a collector electrode is provided. Reference numeral 6 denotes an adhesive such as solder for fixing the semiconductor chip 1. In the above-described semiconductor device manufacturing process, the island 2 and the lead terminals 3 are supplied in the form of a hoop-shaped or strip-shaped lead frame made of a copper material or an iron material. Individual islands 2 and lead terminals 3 are formed.

Further, in the transfer mold in the above-described manufacturing process, referring to FIG. 9 (B), the space is matched with the outer shape of each semiconductor device by the upper mold 7 and the lower mold 8. A cavity 9 is formed, a lead frame on which die bonding and wire bonding are performed is installed inside the cavity, and in this state, resin is injected into the cavity 9 to perform transfer molding. Further, the semiconductor device is separated into individual elements by cutting the lead portions and the like from the lead frame after resin sealing.

[0005]

A first problem is that a resin-molded semiconductor device is usually mounted on a printed board such as a glass epoxy board, and is electrically connected to other elements also mounted on the printed board. The connection forms a desired circuit network. At this time, the semiconductor device in which the lead terminals 3 are led out of the resin 5 has a disadvantage that the mounting area is large because the distance 10 from the tip of the lead terminal 3 to the tip is occupied as the mounting area.

Second problem: The positioning accuracy between the lead frame and the cavity 9 when installed in a mold is limited to about ± 50 μm. Therefore, the size of the island 2 must be designed in consideration of the alignment accuracy. Therefore, the problem of alignment accuracy is
The size of the island 2 with respect to the external dimensions of the package is reduced, and this limits the maximum size of the semiconductor chip 1 that can be accommodated with respect to the external dimensions of the package.

[0007]

According to the present invention, there are provided a plurality of element mounting portions for fixing a semiconductor chip, a frame portion disposed around the plurality of element mounting portions and holding the plurality of element mounting portions, A plurality of alignment marks formed on the frame portion;
Preparing a substrate comprising at least, and mounting the semiconductor chip on an island of the substrate,
Including the semiconductor chip, a step of coating the plurality of element mounting portions with a continuous resin layer, and dicing the resin layer and the substrate with reference to alignment marks formed on the frame portion, The semiconductor chips mounted on the element mounting portion are individually separated to form individual semiconductor elements.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The production method of the present invention will be described below in detail. First step: (FIG. 1) First, a lead frame 30 is prepared. FIG. 1A is a plan view of the lead frame 30, and FIG.
It is an AA sectional view of (A).

The lead frame 30 used in the present invention
Are a large number of element mounting portions 3 for mounting a semiconductor chip.
1, 31A. . . . Are arranged in a row and column direction (or only in one of the directions) in a repetitive pattern, and the multiple element mounting portions 31 are held by a frame portion 32 arranged so as to surround the periphery thereof. Have been.
The element mounting portion 31 includes at least an island 33 for fixing a semiconductor chip and a plurality of lead terminals 34 serving as external connection electrodes. The islands 33 are connected to each other by a connection bar 35, and are also connected to the frame 32 by the connection bar 35. The lead terminal 34 is connected to the island 33. At this time, a specific island 3
In the case of No. 3, the lead terminal 34 connected and held to the adjacent island 33A constitutes one element mounting part 31 correspondingly. The lead terminal 34 in the vicinity of the connection portion between the island 33 and the lead terminal 34 is formed with a recess 36 in which the line width is partially reduced. By arranging a plurality of element mounting portions 31 in the row and column directions in this manner, for example, 100 element mounting portions 31 are arranged on one strip-shaped lead frame 30.

A plurality of alignment marks 37 are formed on the frame 32 surrounding the group of element mounting portions 31. The alignment mark 37 may be any as long as it has an automatic recognition function in the manufacturing process, such as a through-hole or a mark partially recessed by stamping. Further, the shape may be a square, a rectangle, a rectangle, a circle, or the like. Then, one device is provided for each element mounting portion 31 or one device is provided for each device at equal intervals.

For the lead frame 30, for example, a strip-shaped or rectangular-shaped metal sheet for lead frame made of a copper-based metal material having a thickness of about 0.2 mm is prepared, and this metal sheet for lead frame is etched. Alternatively, it can be obtained by opening the pattern shown in the figure by stamping. The thickness of the lead frame 30 can be appropriately set as needed.

Second Step: (FIG. 2) Next, a die bonding step and a wire bonding step are performed on the lead frame 30. FIG. 2B is an AA of FIG.
It is a line sectional view. A conductive paste 38 such as Ag paste or solder is applied on one main surface of each of the islands 33 and 33A,
Each of the islands 33, 33 via the conductive paste 38
A semiconductor chip 39 is fixed on A. Gold plating can be performed on the surface of each island, and a semiconductor chip can be eutectic-connected on the plating.

Further, the bonding pads formed on the surface of the semiconductor chip 39 and the corresponding lead terminals 3
4 is wire-bonded with a wire 40. Wire 4
0 is a gold wire having a diameter of, for example, 20 μ. Here, the wires 40 are connected to the semiconductor chips 3 fixed on the respective islands 33.
9 and another island 33 adjacent to it.
A is connected to a lead terminal 34 extending from A. The back surface of the island 33 to which the semiconductor chip 39 is fixed can be used as an electrode for external connection of the semiconductor chip 39. The mode in which the back surface of the island 33 is used as one of the connection terminals is suitable as a semiconductor chip 39 such as a transistor or a power MOSFET, for example, a semiconductor device element having a vertical current path.

The conductive paste 38 applied for fixing the semiconductor chip 39 is selectively applied on the island 33 to which the semiconductor chip 39 is fixed, as is apparent from FIG. 2A. This is because, when the conductive paste 38 adheres to the lead terminals 34, when performing wire bonding, the conductive paste may be clogged at the tip end of the capillary of the bonding apparatus, which may result in poor bonding and lower productivity. If there is no such problem, a conductive paste may be applied to the entire surface of the element mounting portion 31.

Third step: (FIG. 3) Next, the whole is resin-molded. FIG.
FIG. 3A is a sectional view taken along line AA of FIG. A thermosetting sealing resin layer 41 such as an epoxy resin is formed on the lead frame 30, and each of the element mounting portions 31, 31A. . , Semiconductor chip 39
And the wire 40 is sealed and protected. The resin 41 is used for each semiconductor chip 39. . . Are not individually packaged, but are formed so as to cover all the semiconductor chips 39 in common. Also, 0.05 on the back side of the lead frame 30.
The resin 41 is applied with a thickness of about mm. Thus, the island 33 and the lead terminal 34 are completely embedded in the resin 41.

The resin layer 41 is provided in a space (cavity) formed by upper and lower molds for injection molding.
Is formed, and the space is filled with an epoxy resin and molded. Alternatively, the frame 32 has a height of several mm,
An annular dam having a width of several mm may be formed, a liquid resin may be filled so as to fill a region surrounded by the dam, and the resin may be cured by heat treatment.

Fourth Step: (FIG. 4) Next, the slit 41 is formed by partially removing the resin 41 on the back surface of the lead frame 30. FIG. 4B is a cross-sectional view taken along the line AA of FIG. The slit hole 41 is formed to form an external connection terminal later. It had a width of about 0.5 mm and was formed by cutting the resin 42 with a blade of a dicing device. The blade is prepared in various thicknesses, and the blade is formed once or a plurality of times according to the thickness of the blade to be formed into a desired width. At this time, at the same time as the resin 41 is cut, the back surface of the lead terminal 34 is also cut by about 0.1 mm to expose the metal surface of the lead frame 30.
The slit hole 42 is formed in the vicinity of the “recess 36” formed in a wedge shape in each lead terminal 34. At this time, since the concave portion 36 is covered with the resin 41 and cannot be seen, the alignment mark 37 formed in advance is used as a position reference. Then, a plating layer 43 such as solder plating is formed on the surface of the lead terminal 34 exposed inside the slit hole 42. The plating layer 43 is formed by an electrolytic plating method using the lead frame 30 as one of the electrodes. Slit hole 4
In No. 2, since the entire thickness of the lead terminal 34 is not cut, electrical conduction between the island 33 and the lead terminal 34 is still maintained. Furthermore, each island 33 is connected to the connecting bar 3.
5 are commonly connected. Since all of the exposed metal surfaces are electrically conductive, the plating layer 43 can be formed in a single plating step.

Fifth Step: (FIG. 5) Next, the resin layer 41 is cut for each of the element mounting portions 31 so that each of the elements A, B, C. . . . Is separated. That is, a semiconductor device divided for each element mounting portion 31 is formed by cutting the island 33 and the region surrounding the lead terminal 34 connected to the semiconductor chip 39 fixed thereon (the cutting line 44 in the same figure). I do. A dicing device is used for the cutting, and the resin layer 41 and the lead frame 30 are simultaneously cut by a blade of the dicing device. At the position where the slit hole 42 is located, at least the slit hole 4
2 is formed so as to leave the plating layer 43 attached to the side wall. The remaining plating layer 43 is used when mounting the semiconductor device on a printed circuit board. Further, the other one of the cut lead terminals 34 remains as a protrusion 33 a continuous to the island 33, and the cut connection bar 35 remains as a protrusion 33 b continuous to the island 33.
The cut surfaces of the cut lead terminals 34 and the protrusions 33a and 33b form the same plane as the cut surface of the resin layer 41, and are exposed on the same plane. In the dicing step, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Co., Ltd.) is attached to the back side (the side provided with the slit holes 42), and cutting is performed so that the dicing blade reaches the surface of the blue sheet Cut at depth. At this time, the alignment mark 37 formed in advance is automatically recognized on the dicing apparatus side, and dicing is performed using this as a position reference. In the present embodiment, the alignment mark 37 has a rectangular shape, and the long side of the rectangle is used as a reference position. Further, the thickness of the dicing blade is smaller than the width of the slit hole 42 (for example, 0.1 mm in width).
Along the center line of the lead terminal 3
The dicing was performed so as to pass over the concave portion 36 of No. 3. Thus, the tip of the lead terminal 33 after cutting has a tapered shape, and can be processed into a shape that does not easily fall off the resin 41.

FIG. 6A is a sectional view, FIG. 6B is a rear view, and FIG. 6C is a side view showing a completed semiconductor device formed by such a manufacturing method. FIG. 7 is a perspective view of the apparatus when viewed from the back side. A silicon semiconductor chip 39 on which a desired active element is formed is bonded on one main surface of the island 33 by a conductive adhesive. A plurality of lead terminals 34 are provided at positions apart from the island 33. The electrode pads formed on the surface of the semiconductor chip 39 and the surfaces of the lead terminals 34 are bonded to the bonding wires 4.
0 is electrically connected. The island 33 and the lead terminals 34, including the semiconductor chip 39 and the bonding wires 40, are molded with the resin 41 to form a substantially rectangular parallelepiped package shape. The resin 41 is a thermosetting epoxy resin. The island 33 and the lead terminal 34 are made of a copper-based metal material having a thickness of about 0.2 mm. Resin 41
The external dimensions of the height x width x height are about 0.7mm x 1.0
mm × 0.6 mm. At least the side surfaces 41a, 41b, 4 out of the six surfaces forming the rectangular parallelepiped package outer shape
1c and 41d are constituted by cut surfaces obtained by cutting the resin 41 (see the fifth step). The cut surface of the lead terminal 34 is exposed along the cut surface. The island 33 has a protruding portion 33a remaining on the cut lead terminal 34 and a protruding portion 33b remaining on the connecting portion 35.
The cut surface of 33b is also exposed.

Referring to FIG. 7, on the back side of side surfaces 41b and 41d, there is provided step portion 45, which is a remnant of slit hole 42 formed in the fourth step. The back surface of the portion 33a and a part of the back surface of the lead terminal 34 are exposed. Island 33 and lead terminal 34
A metal plating layer 43 such as solder plating is formed on the exposed surface of
Is formed. The space between the exposed portion of the lead terminal 34 and the exposed portion of the island 33 is covered with the resin 41.

FIG. 8 shows a state in which this device is mounted on a printed circuit board. The lead terminal 34 exposed at the step 45 and the projection 33a of the island 33 are aligned with the printed wiring 25 for element connection formed on the mounting substrate 24, and the two are connected by solder 26 or the like. At this time, the metal plating layer 43 formed in the fifth step improves the wettability of the solder.

The semiconductor device manufactured by the above method has the following advantages. In the semiconductor device manufactured by the manufacturing method of the present invention, since the metal lead terminals do not protrude from the package, the mounting area can be made as large as the size of the semiconductor device. Therefore, the active portion (the semiconductor chip 39) with respect to the mounting area of the semiconductor device
(Which means the chip size) can be greatly improved as compared with that shown in FIG. As a result, the dead space when mounted on the mounting board can be reduced, and the size of the mounting board can be reduced.

Since the plating layer 43 is formed on the surface of each external connection electrode of the divided semiconductor device, when the solder is fixed on the mounting substrate, the solder reaches the upper part of the cut surface (the upper part of the slit hole 42). (Part corresponding to side wall) Easily rises to form a solder fillet. Therefore, the solder bonding force is improved, and deterioration due to stress such as thermal stress can be prevented.

The external connection terminal of this device is exposed at the step 45, and the area between the steps 45
No exposure because it is covered by 1. Accordingly, the distance between the solders 26 when mounted on the mounting board 24 can be designed to be relatively large, and a short circuit accident between the external connection terminals due to the solder bridge can be prevented. As shown in FIG. 6B, the terminal of the lead terminal 34 of the divided semiconductor device is formed in a wedge shape at the terminal of the semiconductor device, so that the lead terminal 34 falls off the side surface of the resin layer 41. Has been prevented. In addition to the wedge shape, it may be a U-shaped concave shape.

Since a large number of elements are packaged together, wasteful materials can be reduced as compared with the case of individually packaging. Since the outer shape of the package, which leads to a reduction in material cost, is formed by cutting the outer shape of the package with a blade of a dicing device, the positioning accuracy of the outer shape of the resin 41 relative to the pattern of the lead frame 30 can be improved. That is, while the alignment accuracy between the molding die and the lead frame 30 by the transfer molding technique is approximately ± 50 μ, the alignment accuracy between the dicing blade and the lead frame 30 by the dicing device is approximately ± 10 μ. Can be smaller. Reducing the alignment precision means that the area of the island 33 can be increased and the chip area of the mountable semiconductor chip 39 can be increased, which also improves the effective mounting area efficiency. At this time, an alignment mark 37 is formed on the outer frame 32 of the lead frame 30 in advance, and dicing is performed using the mark 37, so that the alignment accuracy of the dicing apparatus can be utilized, and the outer shape of the resin 41 and the island 33 can be narrowed.

Although the above embodiment has been described using a lead frame for three terminals, the present invention can be applied to an apparatus having three or more lead terminals. Also,
In the above-described embodiment, one semiconductor chip 39 is fixed to each island. However, for example, a plurality of transistors are fixed to one island, and a composite fixing of a transistor and another element such as a vertical power MOSFET is performed. Is also possible.

Further, in this embodiment, the semiconductor chip 3
9, a power MOS
It goes without saying that the present invention can be applied to the present invention even with a semiconductor chip on which devices such as FETs, IGBTs, and HBTs are formed. In addition, by increasing the number of lead terminals, the present invention can be applied to an integrated circuit such as a BIP or MOS type.

[0028]

As described above, according to the present invention,
A semiconductor device in which the lead terminals 34 do not protrude from the package can be obtained. Therefore, a dead space when the semiconductor device is mounted can be reduced, and a semiconductor device suitable for high-density mounting can be obtained. Since the structure between the external connection terminal and the external connection terminal is covered with the resin layer 41, it is possible to prevent a short circuit between terminals due to a solder bridge or the like when the device is mounted.

By forming the outer shape of the package with a cut surface by a dicing blade, the dimensional accuracy between the island 33 and the end face of the resin 41 can be improved. Therefore, the area of the island 33 can be increased, and the chip size of the semiconductor chip 39 that can be stored can be increased. Lead frame 30
Despite embedding the entire pattern with resin 41,
Since the alignment mark 37 is formed on the frame 32 in advance and the dicing is performed using the alignment mark 37 as a position reference, the alignment accuracy of the dicing apparatus can be maximized.

[Brief description of the drawings]

FIG. 1A is a plan view and FIG. 1B is a cross-sectional view for explaining a manufacturing method of the present invention.

FIG. 2A is a plan view and FIG. 2B is a cross-sectional view for explaining the manufacturing method of the present invention.

3A is a plan view and FIG. 3B is a cross-sectional view for explaining the manufacturing method of the present invention.

4A is a plan view and FIG. 4B is a cross-sectional view for explaining the manufacturing method of the present invention.

5A is a plan view and FIG. 5B is a cross-sectional view for explaining the manufacturing method of the present invention.

6A is a cross-sectional view, FIG. 6B is a rear view, and FIG. 6C is a side view for explaining the semiconductor device of the present invention.

FIG. 7 is a perspective view of the semiconductor device of the present invention as viewed from the back side.

FIG. 8 is a cross-sectional view illustrating a state when the semiconductor device of the present invention is mounted.

FIG. 9 is a diagram illustrating a conventional semiconductor device.

Claims (3)

[Claims] 1. A plurality of device mounting portions for fixing a semiconductor chip, a frame portion disposed around the device mounting portions and holding the plurality of device mounting portions, and a plurality of frame portions formed on the frame portion. A step of preparing a substrate having at least a plurality of alignment marks; a step of mounting the semiconductor chip on an island of the substrate; and a resin in which the plurality of element mounting portions including the semiconductor chip are continuous. A step of coating with a layer, with reference to an alignment mark formed on the frame portion,
A method of manufacturing a semiconductor device, comprising: dicing the resin layer and the substrate; and separating a semiconductor chip mounted on the element mounting portion to form a semiconductor element. 2. The method according to claim 1, wherein the substrate is a lead frame. 3. The method according to claim 1, wherein the step of forming the resin layer is transfer molding.