JP2000164609A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, in which mounting area is reduced, cost reduction is attained and gradation in the alignment precision of dicing is eliminated. SOLUTION: A substrate, in which a first and a second insulating substrate 22, 23 are stacked, is prepared. The substrate has a large number of mounting parts 20. Reference marks 42 are formed on the surface of the first insulating substrate 22, and parts of the second insulating substrate 23 on the reference marks 42 are opened. Semiconductor chips 33 are mounted on the respective mounting parts 20 and are covered with a resin layer. By using the reference marks 42 as alignment reference, the respective mounting parts 20 are subjected to dicing and separated into individual semiconductor devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device capable of reducing a package outer shape, a mounting area, and cost.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor device, a semiconductor chip separated by dicing from a wafer is fixed to a lead frame, and the semiconductor chip fixed on the lead frame is sealed by a transfer mold using a mold and resin injection. In addition, a process of separating a sealed semiconductor chip into individual semiconductor devices has been performed. A strip-shaped or hoop-shaped frame is used as the lead frame. In any case, a plurality of semiconductor devices are simultaneously sealed in one sealing step.

FIG. 7 is a diagram showing a state of a transfer molding process. In the transfer molding process,
The lead frame 2 to which the semiconductor chip 1 is fixed by die bonding or wire bonding is placed inside the cavity 4 formed by the upper and lower molds 3A and 3B, and the epoxy resin is injected into the cavity 4 so that the semiconductor chip 1 Sealing is performed. After such a transfer molding process, the lead frame 2 is cut for each semiconductor chip 1 to manufacture an individual semiconductor device (for example, Japanese Patent Laid-Open No.
-129473).

At this time, as shown in FIG. 8, a plurality of cavities 4a to 4f, a resin source 5 for injecting a resin, a runner 6, and each of the cavities 4a are formed on the surface of the mold 3B. To 4f are provided with gates 7 for pouring resin. These are all grooves provided on the surface of the mold 3B. In the case of a strip-shaped lead frame, for example, ten semiconductor chips 1 are mounted on one lead frame.
One cavity 4, ten gates 7, and one runner 6 are provided. A cavity 4 for, for example, 20 lead frames is provided on the surface of the mold 3.

FIG. 9 is a diagram showing a semiconductor device manufactured by the above transfer molding. A semiconductor chip 1 on which elements such as transistors are formed is fixedly mounted on an island 8 of a lead frame by a brazing material 9 such as solder, and electrode pads of the semiconductor chip 1 and leads 10 are connected by wires 11. Is covered with a resin 12 conforming to the shape of the cavity, and the leading end of the lead terminal 10 is led out of the resin 12.

[0006]

In the conventional package, since the lead terminals 10 for external connection are projected from the resin 12, the distance to the tip of the lead terminals 10 must be considered as a mounting area. There is a disadvantage that the mounting area is much larger than the outer dimensions of the resin 12.

Further, in the conventional transfer molding technique, the resin is cured in a state where pressure is continuously applied, so that the resin is also cured in the runner 6 and the gate 7, and the resin remaining in the runner 6 and the like is discarded. Therefore, in the above-described method using a lead frame, since the gate 7 is provided for each semiconductor device to be manufactured, the use efficiency of the resin is poor, and the number of semiconductor devices that can be manufactured is small with respect to the amount of the resin. Was.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and provides a substrate having a plurality of mounting portions, and affixes a semiconductor chip to each of the mounting portions. A method of manufacturing a semiconductor device, wherein the substrate is covered with a resin layer, and each of the mounting portions is separated to manufacture an individual semiconductor device, wherein a first insulating film having an island portion on which the semiconductor chip is mounted is formed. A substrate and a second insulating substrate having an opening in the island portion are superimposed on each other to form the substrate, and a reference mark indicating a dividing position for separating each mounting portion is formed on the first insulating substrate. The second insulating substrate on the reference mark is opened to be recognizable, and the substrate is divided by recognizing the reference mark as a reference for alignment.

[0009]

Embodiments of the present invention will be described below in detail.

First step: First, as shown in FIG.
A large-sized substrate 21 in which a plurality of, for example, 100 mounting portions 20 corresponding to a plurality of semiconductor devices are arranged vertically and horizontally is prepared. An area 41 for forming a reference mark for recognizing the position of each mounting section 20 is arranged in a peripheral portion of the substrate 21 surrounding the mounting sections 20.

The substrate 21 is an insulating substrate made of ceramic, glass epoxy, or the like. At least two of them are superimposed on each other to have a total thickness of 200 to 350 μm, which is sufficient to maintain the mechanical strength in the manufacturing process. Have. The following is the first insulating substrate 22 (plate thickness: about 100 μm).
m) on the second insulating substrate 23 (plate thickness: about 100 μm)
This is an example of superimposing.

A conductive pattern is formed on the surface of each mounting portion 20 of the substrate 21 by printing a metal paste such as tungsten and by electroplating gold. These are the first and second insulating substrates 2 each having finished printing the metal paste.
It is obtained by laminating 2, 23, baking, and forming a gold plating layer on a metal paste by an electrolytic plating method.

FIG. 2A is a plan view showing a conductive pattern formed on the surface of the first insulating substrate 22. FIG. Each mounting portion 20 surrounded by a dotted line has a long side × a short side of 1.0 mm ×
It has a rectangular shape of 0.8 mm, which is
They are arranged vertically and horizontally with an interval of 0 to 50 μm. The interval becomes a dicing line 24 in a later step. The conductive pattern is provided in each of the mounting portions 20 in the island portion 2.
5 and lead portions 26 are formed, and these patterns have the same shape in each mounting portion 20. The island portion 25 is where the semiconductor chip is mounted, and the lead portion 26 is where the wire is connected to the electrode pad of the semiconductor chip.
From the island portion 25, two first connecting portions 27 are extended in a continuous pattern. These line widths are narrower than the island portion 25 and extend with a line width of, for example, 0.1 mm. The first connecting portion 27 extends beyond the dicing line 24 until it is connected to the lead portion 26 of the adjacent mounting portion 20. Further, each of the second connecting portions 28
However, it extends in a direction perpendicular to the first connecting portion 27 and extends beyond the dicing line 24 so that the lead portion 2 of the adjacent mounting portion 20
4 until it is connected. The second connecting portion 28 further includes
It is connected to a common connection part 29 surrounding the periphery of the mounting part 20.
By extending the first and second connecting portions 27 and 28 in this manner, the island portion 25 and the lead portion 26 of each mounting portion 20 are electrically connected in common.

The first insulating substrate 22 is provided with a through hole 30 for each mounting section 20. Through hole 3
The inside of 0 is buried with a conductive material such as tungsten. Then, an external electrode 31 is formed on the back surface side corresponding to each through hole 30. These external electrodes 31
Are formed in a pattern recessed from the end of the mounting portion 20 by about 0.05 to 0.1 mm. Electrically, it is connected to the common connecting portion 29 through each through hole 30.

FIG. 2B shows an area 4 for forming a reference mark.
FIG. A region 41 for forming a reference mark is provided along four sides of the substrate 21, and a reference mark 42 is formed in the region 41 by the conductive pattern. One reference mark 42 is provided for each dicing line, and one end of each pattern is arranged so as to indicate the position of the dicing line 24.

FIGS. 3A and 3B are a plan view and a sectional view showing a state in which the first and second insulating substrates 22 and 23 are attached to each other. The mounting section 20 and an area 41 where a reference mark is formed are shown. FIG. 4 is a perspective view of the vicinity thereof. The second insulating substrate 23 is provided with an opening 40 for opening the upper part of the island 25. A region 41 for forming a reference mark is also formed by opening the second insulating substrate 23. The opening allows the reference mark 42 to be recognized even after the second insulating substrate 23 is bonded.

The lead portion 26 on the surface of the second insulating substrate 23
The lead portion 32 is provided at a location corresponding to the above.
A through hole 33 is provided below the lead portion 32, and each is electrically connected to the lead portion 26 on the surface of the first insulating substrate 22. Therefore, the lead portion 32 is electrically connected to the external electrode 31. These lead portions 32 are also formed in a pattern recessed from the end of each mounting portion 20 by about 0.05 to 0.1 mm. That is, only the first and second connecting portions 27 and 28 having a narrow line width cross the dicing line 24.

Then, the first and second insulating substrates 22 and 23
Then, a gold plating layer is formed on the exposed conductive pattern by electrolytic plating using the conductive pattern as one electrode. Since each conductive pattern is electrically connected by the common connection portion 29, it is possible to use an electrolytic plating technique.

Second step: See FIG. 5A A semiconductor chip 33 is die-bonded and wire-bonded for each mounting portion 20 of the substrate 21 on which the gold plating layer is formed. The semiconductor chip 33 is fixed to the surface of the island portion 25 with an adhesive such as an Ag paste.
And the lead portions 32 are connected by wires 34 respectively. As the semiconductor chip 33, a three-terminal active element such as a bipolar transistor or a power MOSFET is formed. When a bipolar element is mounted, the external electrode 31 connected to the island portion 25 is a collector terminal, and the external electrodes 31 connected to the lead portions 32 are base / emitter electrodes.

Third step: See FIG. 5 (B) A predetermined amount of epoxy liquid resin is dropped (potted) from a dispenser (not shown) transferred above the substrate 21.
Then, all the semiconductor chips 33 are covered with a common resin layer 35. For example, when 100 semiconductor chips 33 are mounted on one substrate 21, all 100 semiconductor chips 33 are collectively covered. As the liquid resin, for example, C
V576AN (manufactured by Matsushita Electric Works) was used. Since the dropped liquid resin has relatively high viscosity and surface tension, its surface is curved. In addition, the resin layer 35 is not extended to the area 41 where the reference mark is formed, and is left exposed.

Fourth step: See FIG. 5C The curved surface of the resin layer 35 is processed into a flat surface. To process the resin, a flat molding member is pressed before the resin is cured to form a flat surface.
After hardening by heat treatment (curing) for 0 to 200 degrees for several hours, a method of processing a curved surface into a flat surface by grinding the curved surface is considered. The surface of the resin layer 35 is ground by a dicing blade using a dicing blade so that the surface of the resin layer 35 is aligned with a predetermined height from the substrate 21. In this step, the thickness of the resin layer 35 is set to 0.3 to 1.
Mold to 0 mm. The flat surface is extended to the end so that at least when the outermost semiconductor chip 33 is separated into individual semiconductor devices, a resin outer shape having a standardized package size can be formed. The blade is prepared in various thicknesses, and the whole is formed into a flat surface by repeating cutting a plurality of times using a relatively thick blade.

Fifth Step: See FIG. 5D Next, the resin layer 35 is cut for each mounting portion 20 to separate each semiconductor device. The dicing device is used for the cutting, and the resin layer 35 and the substrate 21 are simultaneously cut along the dicing line 24 by the dicing blade 36, thereby forming a semiconductor device divided for each mounting portion 20.
In the dicing step, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Corporation) is attached to the back surface of the substrate 21 and cut at a cutting depth such that the dicing blade 36 reaches the surface of the blue sheet. . In the dicing step, the reference mark 42 formed in the area 41 is automatically recognized on the dicing apparatus side, and the dicing blade 36 is moved on the dicing line 24.
Is diced so that the center line of the dicing passes. This is used as a position reference.

FIG. 6 is a diagram showing each semiconductor device formed by the above-described steps. (A) is a plan view and (B) is a sectional view.

The four peripheral sides of the package are formed by cutting the resin layer 35 and the substrate 21, the upper surface of the package is formed by the flattened surface of the resin layer 35, and the lower surface of the package is formed by the first insulating substrate 22. It is formed on the back side.

The second insulating substrate 23 is a first insulating substrate 2
The height difference is given to the second island portions 25. This height difference improves the bondability during wire bonding. Further, the thickness of the second insulating substrate 23 plays a role in maintaining the mechanical strength in the manufacturing process. However, if the second insulating substrate 23 surrounds the entire periphery of the semiconductor chip 33, the package size increases, so that it is provided partially along one side of the package. Along with this, the island part 2
5 is formed not at the center of the package but at one of the left and right sides, and the lead portion 32 is formed at the opposite side of the package.

This semiconductor device has a size of, for example, 1.0 mm × 0.6 mm × 0.5 mm in length × width × height. 0.5 m on the first insulating substrate 22
The semiconductor chip 33 is sealed with a resin layer 35 having a thickness of about m. The semiconductor chip 33 has a thickness of about 150 μm. The bonding wire 34 draws a loop rising from the surface of the semiconductor chip 33 to a height of about 150 μm at the highest point. Island part 25 and lead part 32
a and 32b are receded from the end face of the package, and only cut portions of the first and second connection portions 27 and 28 are exposed on the side surfaces of the package.

In a semiconductor device formed by such a method, a large number of elements are packaged together with a resin, so that wasteful resin material can be reduced and material costs can be reduced as compared with the case of packaging individually. Leads to.
Further, since a lead frame is not used, the package outer shape can be significantly reduced as compared with the conventional transfer molding method. Furthermore, since terminals for external connection are formed on the back surface of the substrate 21 and do not protrude from the outer shape of the package, the mounting area of the device can be significantly reduced.

Further, by superimposing two insulating substrates, it is possible to maintain the mechanical strength in the manufacturing process, and at the same time, by mounting the semiconductor chip 33 on the surface of the first insulating substrate 22, The overall height can be reduced.

Further, by using the reference mark 42 formed on the surface of the first insulating substrate 22, accurate positioning can be achieved without being affected by displacement when the first and second insulating substrates 22 and 23 are overlapped. Can be cut in position. As a result, the size of the package can be further reduced.

[0030]

As described above, according to the present invention, there is an advantage that it is possible to provide a package structure that can be further reduced in size than a semiconductor device using a lead frame. At this time, since the lead terminals do not protrude, the area occupied by mounting is reduced, and high-density mounting can be realized.

Further, since the molds 3A and 3B for forming the cavity are not required, there is an advantage that the cost can be greatly reduced.

The alignment and dicing are performed using the reference mark 42 formed on the surface of the first insulating substrate 22 similarly to the island 25 and the like, so that the first and second insulating substrates 22 and 23 are affected by the displacement. There is an advantage that the dicing step can be performed without receiving the light. This has an advantage that the package size can be further reduced.

[Brief description of the drawings]

FIG. 1 is a perspective view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

3A is a plan view and FIG. 3B is a cross-sectional view for explaining the present invention.

FIG. 4 is a perspective view for explaining the present invention.

FIG. 5 is a cross-sectional view for explaining the present invention.

6A is a plan view and FIG. 6B is a cross-sectional view for explaining the present invention.

FIG. 7 is a cross-sectional view for explaining a conventional example.

FIG. 8 is a plan view for explaining a conventional example.

FIG. 9 is a cross-sectional view for explaining a conventional example.

Continued on the front page (72) Inventor Takao Shibuya 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5F061 AA01 BA03 CA04 CA06 CA06 CB13

Claims (4)

[Claims] 1. A substrate having a plurality of mounting portions is prepared, a semiconductor chip is fixed to each of the mounting portions, the substrate is covered with a resin layer, and each of the mounting portions is separated into individual semiconductors. A method for manufacturing a semiconductor device for manufacturing a device, comprising: a first insulating substrate having an island portion on which the semiconductor chip is mounted; and a second insulating substrate having an opening in the island portion.
Forming a reference mark on the first insulating substrate, the reference mark indicating a dividing position for separating each mounting portion, and the second insulating substrate on the reference mark Wherein the substrate is divided so as to be recognizable by recognizing the reference mark as a reference for positioning. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said alignment reference is formed by a conductive pattern. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said alignment reference and said island portion are formed simultaneously. 4. The method according to claim 1, wherein the step of separating each mounting portion is a dicing step.