JP3877402B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP3877402B2
JP3877402B2 JP32796897A JP32796897A JP3877402B2 JP 3877402 B2 JP3877402 B2 JP 3877402B2 JP 32796897 A JP32796897 A JP 32796897A JP 32796897 A JP32796897 A JP 32796897A JP 3877402 B2 JP3877402 B2 JP 3877402B2
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island
semiconductor device
semiconductor chip
lead
resin
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JPH11163007A (en
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治雄 兵藤
孝行 谷
隆生 渋谷
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having an improved space factor. SOLUTION: A semiconductor chip 38 is fixed on an island 33 and is connected with a lead terminal 34 by a wire 39. The entire body is molded by a resin 40. The resin 40 on the back side is partially removed to expose the metal surface at a position corresponding to an external connection electrode. The resin 40 is cut so as to surround the periphery of the semiconductor chip 38, thus dividing the entire body into individual semiconductor devices.

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に関し、特に、半導体装置のチップ面積と、半導体装置をプリント基板等の実装基板上に実装する実装面積との比率で表す実装有効面積率を向上させた半導体装置に関する。
【０００２】
【従来の技術】
一般的にシリコン基板上にトランジスタ素子が形成された半導体装置は、図１１（Ａ）に示すような構成が主に用いられる。１はシリコン基板、２はシリコン基板１が実装される放熱板等のアイランド、３はリード端子、及び４は封止用の樹脂モールドである。
トランジスタ素子が形成されたシリコン基板１は、同図に示すように、銅ベースの放熱板等のアイランド２に半田等のろう材５を介して固着実装され、シリコン基板１の周辺に配置されたリード端子３にトランジスタ素子のベース電極、エミッタ電極とがそれぞれワイヤーボンディングによってワイヤー６で電気的に接続されている。コレクタ電極に接続されるリード端子はアイランドと一体に形成されており、シリコン基板をアイランド上に実装することで電気的に接続された後、エポキシ樹脂等の熱硬化型樹脂４によりトランスファーモールドによって、シリコン基板とリード端子の一部を完全に被覆保護し、３端子構造の半導体装置が提供される。
【０００３】
図１１（Ｂ）を参照して、上記のトランスファーモールドでは、上下金型７、８で形成したキャビティ９の内部にダイボンド及びワイヤボンドを施したリードフレーム１０を設置し、この状態でキャビティ９内に樹脂を注入することにより行われる。
【０００４】
【発明が解決しようとする課題】
第１の課題：
樹脂モールドされた半導体装置は、通常、ガラスエポキシ基板等の実装基板に実装され、実装基板上に実装された他の半導体装置や回路素子と電気的に接続され、所定の回路動作を行うための一部品として取り扱われる。
【０００５】
図１２（Ａ）は、実装基板上に半導体装置を実装したときの断面図を示し、２０は半導体装置、２１、２３はベース又はエミッタ電極用のリード端子、２２はコレクタ用のリード端子、２４は実装基板である。
実装基板２４上に半導体装置２０が実装される実装面積は、リード端子２１、２２、２３の先端部分で囲まれた領域によって表される。実装面積は半導体装置２０内のシリコン基板（半導体チップ）面積に比べ大きく、実際に機能を持つ半導体チップの面積に比べ実装面積の殆どはモールド樹脂とリード端子が占めている。
【０００６】
ここで、実際に機能を持つ半導体チップ面積と実装面積との比率を有効面積率として考慮すると、樹脂モールドされた半導体装置では有効面積率が極めて低いことが確認されている。有効面積率が低いことは、実装面積の殆どが半導体チップとは直接関係のないデッドスペースとなるので、実装基板２４の高密度小型化の妨げとなる。
例えば、ＥＩＡＪ規格であるＳＣ−７５Ａ外形に搭載される半導体チップの最大サイズは、図１２（Ｂ）に示すように、概ね０．４０mm×０．４０mm（０．１６平方ｍｍ）が最大であり、パッケージの実装面積は１．６ｍｍ×１．６ｍｍ（２．５６平方ｍｍ）となる。従って有効面積率は約６．２５％であり、実装面積の殆どがデットスペースとなっていることが伺える。
【０００７】
第２の課題：
金型内に設置したときのリードフレーム１０とキャビティ９との位置合わせ精度はプラス・マイナス５０μ程度が限界である。このため、アイランド２の大きさは前記合わせ精度を考慮した大きさに設計しなければならない。従って、合わせ精度の問題は、パッケージの外形寸法に対するアイランド２の寸法を小さくし、これがパッケージの外形寸法に対して収納可能な半導体チップ１の最大寸法に制限を与えていた。
【０００８】
本発明は、上述した事情に鑑みて成されたものであり、本発明は、半導体装置のベース、エミッタ及びコレクタ用の外部接続電極を同一平面上に配置し、半導体チップ面積と実装基板上に実装される半導体装置の実装面積との比率である有効面積率を最大限向上させ、実装面積のデットスペースを最小限小さくできる半導体装置の製造方法を提供する。
【０００９】
【課題を解決するための手段】
本発明は、半導体チップを固着する為のアイランドと、該アイランドに先端を近接する複数本のリード端子と、前記アイランドおよびリード端子を保持するための枠体部とを具備し、前記アイランドと前記リード端子とが多数個行列状に配置され、前記アイランドが互いに連結されかつ互いに連結されたアイランドが前記枠体に保持され、１つのアイランドに対応するリード端子がその隣に位置するアイランドに連結保持されているリードフレームを準備する工程と、
前記アイランドの表面に半導体チップを固着する工程と、
前記半導体チップの表面に形成した電極と前記リード端子とを電気的に接続する工程と、
前記半導体チップを含め、前記アイランドとリード端子を絶縁材料で封止する工程と、
前記絶縁材料の一部を除去してリード端子の裏面側の一部を露出する工程と、
前記絶縁材料を除去した部分を切断して、前記半導体チップを囲む領域で個々のパッケージを形成する工程と、を具備ることを特徴としている。
【００１０】
【発明の実施の形態】
以下に本発明の製造方法を詳細に説明する。
第１工程：（図１）
先ず、リードフレーム３０を準備する。図１（Ａ）はリードフレーム３０の平面図であり、図１（Ｂ）は図１（Ａ）のＸ−Ｘ断面図である。本発明で用いられるリードフレーム３０は、多数のフレーム３１が行方向（又は列方向）に複数個配置されており、複数のフレーム３１は連結バー３２によって互いに連結されている。該フレーム３１は、半導体チップの搭載部となるアイランド３３と、外部接続用電極となる複数のリード端子３４、３５を有する。そして、互いに連結された複数のフレーム３１が同じく連結バー３２によって外枠３６、３６の間に連結される。更に、フレーム３１に隣接して他のフレーム３１Ａが連結バー３２Ａによって同様に連結される。フレーム３１のアイランド３３に対して、隣のフレーム３１Ａのアイランド３３Ａに保持されたリード端子３４Ａ、３５Ａが対応する。この様にフレーム３１を行・列方向に複数配置することで、１本の短冊状のリードフレーム３０に例えば１００個のフレーム３１を配置する。各アイランド３３、３３Ａから延在される各リード端子３４、３５、３４Ａ、３５Ａは、その中間部分の両側がくさび状に形成され、部分的に細く形成されている。
【００１１】
上記のリードフレーム３０は、例えば、約０．２ｍｍ厚の銅系の金属材料で形成された帯状あるいは矩形状のリードフレーム用金属薄板を用意し、このリードフレーム用金属薄板をエッチング加工またはスタンピング加工によってパターニングすることにより得ることができる。ここでは、リードフレーム３０の板厚は必要に応じて適宜に設定することができる。
【００１２】
第２工程：（図２）
次に、リードフレーム３０に対してダイボンド工程とワイヤボンド工程を行う。図２（Ａ）及び図２（Ｂ）に示すように、各アイランド３３、３３Ａの一主面上にＡｇペースト、半田等の導電ペースト３７を塗布し、その導電ペースト３７を介して各アイランド３３、３３Ａ上に半導体チップ３８を固着する。各アイランド表面に金メッキを行い、そのメッキ上に半導体チップを共晶接続することも可能である。
【００１３】
更に、半導体チップ３８の表面に形成されたボンディングパッドと、これに対応するリード端子３４、３５とをワイヤ３９でワイヤボンディングする。ワイヤ３９は例えば直径が２０μの金線から成る。ここで、ワイヤ３９は各アイランド３３上に固着した半導体チップ３８の表面電極と、その隣に隣接した他のアイランド３３Ａから延在するリード端子３４Ａ、３５Ａとを接続する。
半導体チップ３８が固着された各アイランド３３、３３Ａの裏面は、係る半導体チップ３８の外部接続用の電極となり、ワイヤ３９で電気的に接続されたリード３４Ａ、３５Ａ、３４、３５も外部接続用の電極となる。アイランド３３、３３Ａの裏面を接続用端子の１つとして用いる形態は、半導体チップ３８として例えばトランジスタ、パワーＭＯＳＦＥＴ等の、電流経路が垂直方向になる半導体デバイス素子に適している。
【００１４】
半導体チップ３８を固着するために塗布した導電性ペースト３７は、図２（Ａ）から明らかなように、半導体チップ３８が固着されるアイランド３３、３４Ａ上に選択的に塗布形成する。リード端子３４、３５．．．上に導電性ペースト３７が付着すると、ワイヤボンディングを行う場合に、ボンディング装置のキャピラリーの先端部分に導電性ペーストがつまりボンディング不良が生じ生産性が低下する恐れがあるためである。この様な問題がない場合には、導電性ペーストをフレーム３１、３１Ａ全面に塗布しても良い。
【００１５】
第３工程：（図３）
次に、全体を樹脂モールドする。図３（Ａ）に示すように、リードフレーム３０上にエポキシ樹脂等の熱硬化性の封止用樹脂層４０を形成し、各フレーム３１、３１Ａ．．、半導体チップ３８及びワイヤ３９を封止保護する。樹脂層４０は、素子Ａ、素子Ｂ、素子Ｃ……を個別にパッケージングするものではなく、半導体チップ３８の全部を被うように形成する。また、リードフレーム３０の裏面側にも０．０５ｍｍ程度の厚みで樹脂を被着する。これで、アイランド３３とリード端子３４、３５は完全に樹脂４０内部に埋設されることになる。モールド後のリードフレーム３０の状態を図３（Ｂ）に示す。
【００１６】
この樹脂層４０は、射出成形用の上下金型が形成する空間（キャビティ）内にリードフレーム３０を設置し、該空間内にエポキシ樹脂を充填、成形する事によって形成する。
第４工程：（図４）
次に、リードフレーム３０の裏面側の樹脂４０を部分的に除去してスリット孔４１を形成する。このスリット孔４１は、ダイシング装置のブレードによって樹脂４０を切削することによって形成したものであり、前記ブレード厚みに応じて切削を複数回繰り返すことにより、幅が約０．５ｍｍのスリット孔４１を形成する。また、樹脂４０を切削すると同時にリード端子３４、３５の裏面側も約０．１ｍｍ程切削して、リードフレーム２０の金属表面を露出させる。このスリット孔４１は、各リード端子３４、３５．．．の中間に形成した「くさび状部分」の付近に一本、あるいは複数本形成する。
【００１７】
第５工程：（図５（Ａ））
次に、図５（Ａ）に示すように、スリット孔４１の内部に露出したリード端子３４、３５、３４Ａ、３５Ａ．．の表面に半田メッキ等のメッキ層４２を形成する。このメッキ層４２は、リードフレーム３０を電極の一方とする電解メッキ法により行われる。スリット孔４１はリード端子３４、３５の板厚の全部を切断していないので、アイランド３３とリード端子３４、３５は未だ電気的な導通が保たれている。更に各フレーム３１、３１Ａ．．が連結バー３２、３２Ａによって共通接続されている。このように露出した金属表面のすべてが電気的に導通しているので、一回のメッキ工程でメッキ層４２を形成することができる。
【００１８】
第６工程：（図５（Ｂ））
次に、樹脂層４０を切断して各々の素子Ａ、素子Ｂ、素子Ｃ．．．．を分離する。即ち、アイランド３３とこの上に固着された半導体チップ３８に接続されたリード端子３４Ａ、３５Ａとを囲む領域（同図の矢印４３、及び図３Ａの一点鎖線４３）で切断することにより、個々に分割した半導体装置を形成する。切断にはダイシング装置が用いられ、ダイシング装置のブレードによって樹脂層４０とリードフレーム３０とを同時に切断する。切断する際には裏面側（スリット孔９１を設けた側）にブルーシート（例えば、商品名：ＵＶシート、リンテック株式会社製）を貼り付けた状態で、前記ダイシングブレードがブルーシートの表面に到達するような切削深さで行う。スリット孔４１が位置する箇所では、少なくともスリット孔４１の側壁に付着したメッキ層４２を残すように形成する。この様に残存させたメッキ層４２は、半導体装置をプリント基板上に実装する際に利用される。また、切断したリード端子３４、３５の他方はアイランド３３に連続する突起部３３ａとして残存し、切断した連結バー３２、３２Ａはアイランド３３に連続する突起部３３ｂ（図６Ｂに示した）として残存する。切断されたリード端子３４、３５及び突起部３３ａ、３３ｂの切断面は、樹脂層４０の切断面と同一平面を形成し、該同一平面に露出する。
【００１９】
図６は斯かる製造方法によって形成した完成後の半導体装置を示す、（Ａ）断面図、（Ｂ）裏面図、（Ｃ）側面図である。更に図７は、装置を裏面側からみたときの斜視図である。
所望の能動素子を形成したシリコン半導体チップ３８が導電性の接着剤によってアイランド３３の一主面上に接着されている。アイランド３３は外部接続電極の一部として使用される。リード端子３４、３５がアイランド３３とは離れた位置に複数本設けられている。半導体チップ３８の表面部分に形成した電極パッドとリード端子３４、３５の表面とがボンディングワイヤ３９によって電気的に接続される。半導体チップ３８とボンディングワイヤ３９を含めて、アイランド３３とリード端子３４、３５が樹脂４０でモールドされて、大略直方体のパッケージ形状を形成する。樹脂４０は熱硬化性エポキシ樹脂である。アイランド３３とリード端子３４、３５は、厚さが約０．２ｍｍの銅系の金属材料から成る。樹脂４０の外形寸法は、縦×横×高さが、約０．７ｍｍ×１．０ｍｍ×０．６ｍｍである。
【００２０】
直方体のパッケージ外形を形成する６面のうち、上面４０ａと裏面４０ｂはモールド金型によって形成された面で構成される。前記６面の内、側面４０ｃ、４０ｄ、４０ｅ、４０ｆは樹脂４０を切断した（第６工程参照）切断面で構成される。該切断面に沿ってリード端子３３、３５の切断面が露出する。アイランド３３には切断されたリード端子３４、３５の名残である突起部３３ａと連結部３２の名残である突起部３３ｂを有し、これらの突起部３３ａ、３３ｂの切断面も露出する。
【００２１】
図７を参照して、側面４０ｄ、４０ｆの裏面側には第４工程で形成したスリット孔４１の名残である段差部４３を有し、該段差部４３の表面にアイランド３３の裏面側と、リード端子３４、３５の裏面側の一部が露出する。アイランド３とリード端子３４、３５の露出した表面には半田メッキなどの金属メッキ層４２が形成される。リード端子３４、３５の露出部分とアイランド３３の露出部との間は、樹脂４０で被覆される。
【００２２】
この装置をプリント基板上に実装した状態を図８に示す。実装基板２４上に形成した素子間接続用のプリント配線２５に対して段差部４３に露出したリード端子３４、３５とアイランド３３の突起部３３ａを位置合わせし、半田２６等によって両者を接続する。この時、上記の第５工程で形成した金属メッキ層４２が半田の塗れ性を良好にする。
【００２３】
以上の方法によって製造された半導体装置は、以下のメリットを有する。
図９を参照して、本願発明者は、チップサイズが０．４０ｍｍ×０．４０ｍｍのトランジスタチップをアイランド３３上に設置し、上述の製造方法によってパッケージサイズが１．０ｍｍ×０．７ｍｍの半導体装置を実現した。この時の、アイランド３３のサイズは０．５ｍｍ×０．５ｍｍ、リード端子３４、３５のサイズは０．２５ｍｍ×０．１５ｍｍとすることができた。これらのサイズは実装される半導体チップサイズに応じて任意に設定することができる。
【００２４】
ここで、上述した本発明の半導体装置の製造方法によって製造された半導体装置の有効面積率を、図１２（Ｂ）に示した従来の半導体装置と比較する。従来の半導体装置のチップサイズは、０．４０ｍｍ×０．４０ｍｍ（０．１６平方ｍｍ）で、半導体装置の実装面積は１．６ｍｍ×１．６ｍｍ（２．５６平方ｍｍ）である。従って、従来の半導体装置の有効面積率は約６．２５％である。
【００２５】
それに対して、本発明の製造方法によって製造した半導体装置は、金属製リード端子がパッケージから突出しないので、実装面積を半導体装置の大きさと同じ程度の大きさにすることができる。即ち１．０ｍｍ×０．７ｍｍ（０．７平方ｍｍ）とすることができる。。従って、本発明の有効面積率は２２．８５％となり、従来と比べて約３．６倍向上する事ができた。これにより、実装基板上に実装する実装面積のデットスペースを小さくすることができ、実装基板の小型化に寄与することができる。
【００２６】
上記のメリットに加えて、本発明では以下のメリットを得ることができる。
分割された半導体装置の各外部接続用電極の表面にはメッキ層４２が形成されているので、実装基板上に半田固着した際に該半田が切断面の上部まで（スリット孔４１の側壁に相当する部分）容易に盛り上がって半田フィレットを形成する。従って半田接合力が向上し熱ストレス等の応力による劣化を防止することができる。
【００２７】
この装置の外部接続端子は、段差部４３に露出し、段差部４３と段差部４３との間の領域は樹脂４０によって被覆されるので露出しない。従って実装基板２４上に実装した際に半田２６と半田２６との距離を比較的大きく設計でき、半田ブリッジによる外部接続端子間の短絡事故を防止できる。
分割された半導体装置のリード端子３４、３５の終端は、図６（Ｂ）に示すように、半導体装置の終端部分でくさび状に形成されるために、リード端子３４、３５が樹脂層４０の側面から抜け落ちることを防止している。
【００２８】
多数個の素子をまとめてパッケージングするので、個々にパッケージングする場合に比べて無駄にする材料を少なくでき。材料費の低減につながる
パッケージの外形をダイシング装置のブレードで切断することにより構成したので、あらかじめリードフレーム３０の外枠３６に位置あわせマークを形成しておき、該マークを使用してダイシングを行うことにより、リードフレーム３０のパターンに対する樹脂外形の精度を向上できる。即ち、モールド金型による合わせ精度がプラス・マイナス５０μ程度であるのに対して、ダイシング装置によって切断した樹脂外形はプラス・マイナス１０μ程度に小さくできる。合わせ精度を小さくできることは、アイランド３３の面積を増大して、搭載可能な半導体チップ３８のチップ面積を増大できることを意味する。
【００２９】
尚、上述した実施形態では、３端子用のリードフレームを用いて説明をしたが、４端子用にする場合には、図１０に示すように、アイランド３３から３本のリード端子３４、３５、５０を延在させて上述した方法で製造を行えば４端子用の半導体装置を提供することができる。
また、上述した実施形態では、各アイランドに１つの半導体チップ３８を固着したが、１つのアイランドに、例えばトランジスタを複数個固着すること、及び、トタンジスタと縦型パワーＭＯＳＦＥＴ等の他の素子との複合固着も可能である。この様な場合には、リードフレームは図１０に示すような多数のリード端子を有するものが使用される。
【００３０】
さらに、本実施形態では、半導体チップ３８にトランジスタを形成したが、縦型或いは比較的発熱量の少ない横型のデバイスであればこれに限らず、例えば、パワーＭＯＳＦＥＴ、ＩＧＢＴ、ＨＢＴ等のデバイスを形成した半導体チップであっても、本発明に応用ができることは説明するまでもない。加えて、リード端子の本数を増大することでＢＩＰ、ＭＯＳ型等の集積回路等にも応用することができる。
【００３１】
【発明の効果】
以上説明したように、本発明によれば、リード端子３４，３５がパッケージから突出しない半導体装置を得ることができる。従って、半導体装置を実装したときのデッドスペースを削減し、高密度実装に適した半導体装置を得ることができる。
【００３２】
外部接続端子と外部接続端子との間を樹脂層４０で被覆した構造にできるので、装置を実装したときの半田ブリッジ等による端子間短絡の事故を防止できる。パッケージの外形をダイシングブレードによる切断面で構成することにより、アイランド３３と樹脂４０の端面との寸法精度を向上できる。従って、アイランド３３の面積を増大して、収納可能な半導体チップ３８のチップサイズを増大できる。
【図面の簡単な説明】
【図１】本発明の製造方法を説明する図。
【図２】本発明の製造方法を説明する図。
【図３】本発明の製造方法を説明する図。
【図４】本発明の製造方法を説明する図。
【図５】本発明の製造方法を説明する図。
【図６】本発明の半導体装置を説明する図。
【図７】本発明の半導体装置を説明する図。
【図８】本発明の半導体装置を実装したときの状態を説明する図。
【図９】本発明の半導体装置を説明する図。
【図１０】他の実施の形態を説明する図。
【図１１】従来の半導体装置を説明する図。
【図１２】従来の半導体装置を説明する図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved mounting effective area ratio expressed by a ratio between a chip area of the semiconductor device and a mounting area where the semiconductor device is mounted on a mounting substrate such as a printed circuit board.
[0002]
[Prior art]
In general, a semiconductor device in which a transistor element is formed over a silicon substrate mainly has a structure as shown in FIG. 1 is a silicon substrate, 2 is an island such as a heat sink on which the silicon substrate 1 is mounted, 3 is a lead terminal, and 4 is a resin mold for sealing.
As shown in the figure, the silicon substrate 1 on which the transistor elements are formed is fixedly mounted on an island 2 such as a copper-based heat dissipation plate via a brazing material 5 such as solder, and is arranged around the silicon substrate 1. The base electrode and emitter electrode of the transistor element are electrically connected to the lead terminal 3 by wires 6 by wire bonding. The lead terminal connected to the collector electrode is formed integrally with the island, and after being electrically connected by mounting the silicon substrate on the island, transfer molding with a thermosetting resin 4 such as epoxy resin, A semiconductor device having a three-terminal structure in which a silicon substrate and a part of a lead terminal are completely covered and protected is provided.
[0003]
Referring to FIG. 11B, in the transfer mold described above, a lead frame 10 to which die bonding and wire bonding are applied is placed inside the cavity 9 formed by the upper and lower molds 7 and 8, and in this state the inside of the cavity 9 This is done by injecting resin into the resin.
[0004]
[Problems to be solved by the invention]
First issue:
A resin-molded semiconductor device is usually mounted on a mounting substrate such as a glass epoxy substrate, and is electrically connected to other semiconductor devices and circuit elements mounted on the mounting substrate to perform a predetermined circuit operation. Treated as a single part.
[0005]
FIG. 12A shows a cross-sectional view when a semiconductor device is mounted on a mounting substrate, where 20 is a semiconductor device, 21 and 23 are base or emitter electrode lead terminals, 22 is a collector lead terminal, and 24. Is a mounting substrate.
The mounting area where the semiconductor device 20 is mounted on the mounting substrate 24 is represented by a region surrounded by the tip portions of the lead terminals 21, 22, and 23. The mounting area is larger than the area of the silicon substrate (semiconductor chip) in the semiconductor device 20, and most of the mounting area is occupied by the mold resin and the lead terminal as compared to the area of the semiconductor chip that actually has a function.
[0006]
Here, it is confirmed that the effective area ratio is extremely low in the resin-molded semiconductor device when the effective area ratio is considered as the ratio between the actually functioning semiconductor chip area and the mounting area. When the effective area ratio is low, most of the mounting area becomes a dead space that is not directly related to the semiconductor chip, which hinders high-density downsizing of the mounting substrate 24.
For example, as shown in FIG. 12B, the maximum size of the semiconductor chip mounted on the EIAJ standard SC-75A outline is approximately 0.40 mm × 0.40 mm (0.16 square mm). The package mounting area is 1.6 mm × 1.6 mm (2.56 square mm). Therefore, the effective area ratio is about 6.25%, and it can be seen that most of the mounting area is a dead space.
[0007]
Second issue:
The alignment accuracy between the lead frame 10 and the cavity 9 when installed in the mold is limited to about plus or minus 50 μm. For this reason, the size of the island 2 must be designed in consideration of the alignment accuracy. Accordingly, the problem of alignment accuracy is that the size of the island 2 is reduced with respect to the package outer dimension, which limits the maximum size of the semiconductor chip 1 that can be accommodated with respect to the package outer dimension.
[0008]
The present invention has been made in view of the above-described circumstances. In the present invention, external connection electrodes for a base, an emitter, and a collector of a semiconductor device are arranged on the same plane, and the semiconductor chip area and the mounting substrate are arranged. Provided is a semiconductor device manufacturing method capable of improving the effective area ratio, which is a ratio to the mounting area of the semiconductor device to be mounted, to the maximum, and reducing the dead space of the mounting area to the minimum.
[0009]
[Means for Solving the Problems]
The present invention comprises an island for fixing a semiconductor chip, a plurality of lead terminals having tips close to the island, and a frame body portion for holding the island and the lead terminals, A plurality of lead terminals are arranged in a matrix, the islands are connected to each other, and the islands connected to each other are held by the frame, and the lead terminals corresponding to one island are connected and held by the island located next to the island. a step of preparing a lead frame that has been,
Fixing a semiconductor chip to the surface of the island;
Electrically connecting the electrode formed on the surface of the semiconductor chip and the lead terminal;
Including the semiconductor chip, sealing the island and the lead terminal with an insulating material;
Removing a portion of the insulating material to expose a portion of the back side of the lead terminal;
Cutting the portion from which the insulating material has been removed, and forming individual packages in regions surrounding the semiconductor chip.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The production method of the present invention will be described in detail below.
First step: (Fig. 1)
First, the lead frame 30 is prepared. 1A is a plan view of the lead frame 30, and FIG. 1B is a cross-sectional view taken along line XX of FIG. 1A. In the lead frame 30 used in the present invention, a plurality of frames 31 are arranged in the row direction (or column direction), and the plurality of frames 31 are connected to each other by a connecting bar 32. The frame 31 includes an island 33 serving as a semiconductor chip mounting portion and a plurality of lead terminals 34 and 35 serving as external connection electrodes. A plurality of frames 31 connected to each other are also connected between the outer frames 36 and 36 by the connecting bar 32. Further, another frame 31A adjacent to the frame 31 is similarly connected by the connection bar 32A. The lead terminals 34A and 35A held by the island 33A of the adjacent frame 31A correspond to the island 33 of the frame 31. In this manner, by arranging a plurality of frames 31 in the row and column directions, for example, 100 frames 31 are arranged on one strip-like lead frame 30. Each lead terminal 34, 35, 34 A, 35 A extending from each island 33, 33 A is formed in a wedge shape on both sides of the intermediate portion and partially formed in a thin shape.
[0011]
The lead frame 30 is prepared by, for example, preparing a strip or rectangular lead frame metal thin plate made of a copper metal material having a thickness of about 0.2 mm, and etching or stamping the lead frame metal thin plate. Can be obtained by patterning. Here, the plate thickness of the lead frame 30 can be appropriately set as required.
[0012]
Second step: (FIG. 2)
Next, a die bonding process and a wire bonding process are performed on the lead frame 30. As shown in FIGS. 2A and 2B, a conductive paste 37 such as Ag paste or solder is applied on one main surface of each of the islands 33 and 33A, and each island 33 is interposed through the conductive paste 37. , 33A is fixed to the semiconductor chip 38. It is also possible to perform gold plating on the surface of each island and connect the semiconductor chip to the eutectic connection on the plating.
[0013]
Further, the bonding pads formed on the surface of the semiconductor chip 38 and the corresponding lead terminals 34 and 35 are wire-bonded with wires 39. The wire 39 is made of, for example, a gold wire having a diameter of 20 μm. Here, the wire 39 connects the surface electrode of the semiconductor chip 38 fixed on each island 33 to the lead terminals 34A and 35A extending from the other adjacent island 33A.
The back surfaces of the islands 33 and 33A to which the semiconductor chip 38 is fixed serve as external connection electrodes of the semiconductor chip 38, and the leads 34A, 35A, 34, and 35 electrically connected by the wire 39 are also used for external connection. It becomes an electrode. The form in which the rear surfaces of the islands 33 and 33A are used as one of the connection terminals is suitable for a semiconductor device element such as a transistor or a power MOSFET as the semiconductor chip 38, in which the current path is vertical.
[0014]
As is apparent from FIG. 2A, the conductive paste 37 applied for fixing the semiconductor chip 38 is selectively applied and formed on the islands 33 and 34A to which the semiconductor chip 38 is fixed. Lead terminals 34, 35. . . If the conductive paste 37 adheres to the top, there is a possibility that when wire bonding is performed, the conductive paste at the tip portion of the capillary of the bonding apparatus, that is, bonding failure may occur and productivity may be reduced. If there is no such problem, conductive paste may be applied to the entire surfaces of the frames 31 and 31A.
[0015]
Third step: (Fig. 3)
Next, the whole is resin-molded. As shown in FIG. 3A, a thermosetting sealing resin layer 40 such as an epoxy resin is formed on the lead frame 30, and the frames 31, 31A. . The semiconductor chip 38 and the wire 39 are sealed and protected. The resin layer 40 does not package the elements A, B, C, etc. individually, but is formed so as to cover the entire semiconductor chip 38. The resin is also applied to the back side of the lead frame 30 with a thickness of about 0.05 mm. As a result, the island 33 and the lead terminals 34 and 35 are completely embedded in the resin 40. The state of the lead frame 30 after molding is shown in FIG.
[0016]
The resin layer 40 is formed by installing a lead frame 30 in a space (cavity) formed by upper and lower molds for injection molding, filling the space with an epoxy resin, and molding the space.
Fourth step: (FIG. 4)
Next, the resin 40 on the back side of the lead frame 30 is partially removed to form slit holes 41. The slit hole 41 is formed by cutting the resin 40 with a blade of a dicing apparatus, and the slit hole 41 having a width of about 0.5 mm is formed by repeating cutting a plurality of times according to the blade thickness. To do. At the same time as the resin 40 is cut, the back surfaces of the lead terminals 34 and 35 are also cut by about 0.1 mm to expose the metal surface of the lead frame 20. The slit hole 41 is connected to each lead terminal 34, 35. . . One or more are formed in the vicinity of the “wedge-shaped portion” formed in the middle.
[0017]
Fifth step: (FIG. 5A)
Next, as shown in FIG. 5A, the lead terminals 34, 35, 34A, 35A. . A plating layer 42 such as solder plating is formed on the surface of the substrate. The plating layer 42 is performed by an electrolytic plating method using the lead frame 30 as one of the electrodes. Since the slit hole 41 does not cut the entire thickness of the lead terminals 34 and 35, the island 33 and the lead terminals 34 and 35 are still electrically connected. Further, each frame 31, 31A. . Are commonly connected by connecting bars 32 and 32A. Since all the exposed metal surfaces are electrically connected in this way, the plating layer 42 can be formed in a single plating step.
[0018]
Sixth step: (FIG. 5B)
Next, the resin layer 40 is cut and each element A, element B, element C. . . . Isolate. That is, by cutting along the region (the arrow 43 in the figure and the one-dot chain line 43 in FIG. 3A) surrounding the island 33 and the lead terminals 34A and 35A connected to the semiconductor chip 38 fixed on the island 33, individually A divided semiconductor device is formed. A dicing apparatus is used for cutting, and the resin layer 40 and the lead frame 30 are simultaneously cut by a blade of the dicing apparatus. When cutting, the dicing blade reaches the surface of the blue sheet with a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Co., Ltd.) attached to the back side (the side where the slit hole 91 is provided). The cutting depth is as follows. In the place where the slit hole 41 is located, at least the plating layer 42 attached to the side wall of the slit hole 41 is formed. The plating layer 42 left in this way is used when the semiconductor device is mounted on a printed board. Further, the other of the cut lead terminals 34 and 35 remains as a protrusion 33a continuous with the island 33, and the cut connection bars 32 and 32A remain as a protrusion 33b (shown in FIG. 6B) continuous with the island 33. . The cut surfaces of the cut lead terminals 34 and 35 and the protrusions 33a and 33b form the same plane as the cut surface of the resin layer 40 and are exposed to the same plane.
[0019]
FIG. 6A is a cross-sectional view, FIG. 6B is a back view, and FIG. 6C is a side view showing a completed semiconductor device formed by such a manufacturing method. Furthermore, FIG. 7 is a perspective view when the apparatus is viewed from the back side.
A silicon semiconductor chip 38 on which a desired active element is formed is bonded onto one main surface of the island 33 with a conductive adhesive. The island 33 is used as a part of the external connection electrode. A plurality of lead terminals 34 and 35 are provided at positions distant from the island 33. The electrode pads formed on the surface portion of the semiconductor chip 38 and the surfaces of the lead terminals 34 and 35 are electrically connected by bonding wires 39. The island 33 and the lead terminals 34 and 35 including the semiconductor chip 38 and the bonding wire 39 are molded with the resin 40 to form a substantially rectangular parallelepiped package shape. The resin 40 is a thermosetting epoxy resin. The island 33 and the lead terminals 34 and 35 are made of a copper-based metal material having a thickness of about 0.2 mm. The external dimensions of the resin 40 are about 0.7 mm × 1.0 mm × 0.6 mm in length × width × height.
[0020]
Of the six surfaces forming the outer shape of the rectangular parallelepiped package, the upper surface 40a and the rear surface 40b are configured by surfaces formed by a mold. Of the six surfaces, the side surfaces 40c, 40d, 40e, and 40f are constituted by cut surfaces obtained by cutting the resin 40 (see the sixth step). The cut surfaces of the lead terminals 33 and 35 are exposed along the cut surface. The island 33 has a protruding portion 33a which is a remnant of the cut lead terminals 34 and 35 and a protruding portion 33b which is a remnant of the connecting portion 32, and the cut surfaces of these protruding portions 33a and 33b are also exposed.
[0021]
With reference to FIG. 7, the back surface side of the side surfaces 40 d and 40 f has a stepped portion 43 that is a remnant of the slit hole 41 formed in the fourth step, and the back surface side of the island 33 is formed on the surface of the stepped portion 43. A part of the back side of the lead terminals 34 and 35 is exposed. A metal plating layer 42 such as solder plating is formed on the exposed surfaces of the island 3 and the lead terminals 34 and 35. The exposed portion of the lead terminals 34 and 35 and the exposed portion of the island 33 are covered with a resin 40.
[0022]
FIG. 8 shows a state in which this apparatus is mounted on a printed circuit board. The lead terminals 34 and 35 exposed at the stepped portion 43 and the projection 33a of the island 33 are aligned with the printed wiring 25 for inter-element connection formed on the mounting substrate 24, and both are connected by solder 26 or the like. At this time, the metal plating layer 42 formed in the fifth step improves solderability.
[0023]
The semiconductor device manufactured by the above method has the following merits.
Referring to FIG. 9, the present inventor installed a transistor chip having a chip size of 0.40 mm × 0.40 mm on an island 33, and a semiconductor having a package size of 1.0 mm × 0.7 mm by the above-described manufacturing method. Realized the device. At this time, the size of the island 33 could be 0.5 mm × 0.5 mm, and the size of the lead terminals 34 and 35 could be 0.25 mm × 0.15 mm. These sizes can be arbitrarily set according to the size of the semiconductor chip to be mounted.
[0024]
Here, the effective area ratio of the semiconductor device manufactured by the semiconductor device manufacturing method of the present invention described above is compared with the conventional semiconductor device shown in FIG. The chip size of the conventional semiconductor device is 0.40 mm × 0.40 mm (0.16 square mm), and the mounting area of the semiconductor device is 1.6 mm × 1.6 mm (2.56 square mm). Therefore, the effective area ratio of the conventional semiconductor device is about 6.25%.
[0025]
On the other hand, in the semiconductor device manufactured by the manufacturing method of the present invention, since the metal lead terminals do not protrude from the package, the mounting area can be made as large as the size of the semiconductor device. That is, it can be set to 1.0 mm × 0.7 mm (0.7 square mm). . Therefore, the effective area ratio of the present invention is 22.85%, which is an improvement of about 3.6 times compared to the conventional case. Thereby, the dead space of the mounting area mounted on a mounting board | substrate can be made small, and it can contribute to size reduction of a mounting board | substrate.
[0026]
In addition to the above merits, the present invention can obtain the following merits.
Since the plating layer 42 is formed on the surface of each external connection electrode of the divided semiconductor device, when the solder is fixed on the mounting substrate, the solder reaches the upper part of the cut surface (corresponding to the side wall of the slit hole 41). Part to be raised easily to form a solder fillet. Therefore, the solder bonding force is improved and deterioration due to stress such as thermal stress can be prevented.
[0027]
The external connection terminal of this device is exposed at the stepped portion 43, and the region between the stepped portion 43 and the stepped portion 43 is covered with the resin 40 and is not exposed. Therefore, when mounted on the mounting substrate 24, the distance between the solder 26 and the solder 26 can be designed to be relatively large, and a short circuit accident between the external connection terminals due to the solder bridge can be prevented.
As shown in FIG. 6B, the terminal ends of the divided semiconductor device lead terminals 34 and 35 are formed in a wedge shape at the terminal portion of the semiconductor device. Prevents falling off from the side.
[0028]
Since many devices are packaged together, less material is wasted compared to individual packaging. Since the outer shape of the package that leads to a reduction in material costs is cut by the blade of the dicing apparatus, alignment marks are formed in advance on the outer frame 36 of the lead frame 30, and dicing is performed using the marks. Thereby, the precision of the resin outer shape with respect to the pattern of the lead frame 30 can be improved. That is, while the alignment accuracy by the mold is about plus / minus 50 μm, the outer shape of the resin cut by the dicing apparatus can be reduced to about plus / minus 10 μm. The fact that the alignment accuracy can be reduced means that the area of the island 33 can be increased and the chip area of the mountable semiconductor chip 38 can be increased.
[0029]
In the above-described embodiment, the description has been given using the lead frame for three terminals. However, when the lead frame is used for four terminals, as shown in FIG. 10, three lead terminals 34, 35, If 50 is extended and manufactured by the method described above, a four-terminal semiconductor device can be provided.
In the above-described embodiment, one semiconductor chip 38 is fixed to each island. For example, a plurality of transistors are fixed to one island, and a transistor and other elements such as a vertical power MOSFET are connected. Composite fixing is also possible. In such a case, a lead frame having a large number of lead terminals as shown in FIG. 10 is used.
[0030]
Furthermore, in the present embodiment, the transistor is formed on the semiconductor chip 38, but the device is not limited to this as long as it is a vertical type or a horizontal type device with a relatively small amount of heat generation. For example, a device such as a power MOSFET, IGBT, or HBT is formed. It goes without saying that the semiconductor chip can be applied to the present invention. In addition, by increasing the number of lead terminals, it can be applied to integrated circuits such as BIP and MOS type.
[0031]
【The invention's effect】
As described above, according to the present invention, a semiconductor device in which the lead terminals 34 and 35 do not protrude from the package can be obtained. Therefore, the dead space when the semiconductor device is mounted can be reduced, and a semiconductor device suitable for high-density mounting can be obtained.
[0032]
Since it can be made the structure which coat | covered between the external connection terminal and the external connection terminal with the resin layer 40, the accident of the short circuit between terminals by the solder bridge etc. when a device is mounted can be prevented. By configuring the outer shape of the package with a cut surface by a dicing blade, the dimensional accuracy between the island 33 and the end surface of the resin 40 can be improved. Therefore, the area of the island 33 can be increased, and the chip size of the semiconductor chip 38 that can be accommodated can be increased.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a production method of the present invention.
FIG. 2 is a view for explaining a production method of the present invention.
FIG. 3 is a view for explaining a production method of the present invention.
FIG. 4 is a view for explaining a production method of the present invention.
FIG. 5 is a view for explaining a manufacturing method of the present invention.
6A and 6B illustrate a semiconductor device of the present invention.
FIG. 7 illustrates a semiconductor device of the present invention.
FIG. 8 illustrates a state when a semiconductor device of the present invention is mounted.
FIG 9 illustrates a semiconductor device of the present invention.
FIG. 10 illustrates another embodiment.
FIG. 11 illustrates a conventional semiconductor device.
FIG. 12 illustrates a conventional semiconductor device.

Claims (4)

半導体チップを固着する為のアイランドと、該アイランドに先端を近接する複数本のリード端子と、前記アイランドおよびリード端子を保持するための枠体部とを具備し、前記アイランドと前記リード端子とが多数個行列状に配置され、前記アイランドが互いに連結されかつ互いに連結されたアイランドが前記枠体に保持され、１つのアイランドに対応するリード端子がその隣に位置するアイランドに連結保持されているリードフレームを準備する工程と、
前記アイランドの表面に半導体チップを固着する工程と、
前記半導体チップの表面に形成した電極と前記リード端子とを電気的に接続する工程と、前記半導体チップを含め、前記アイランドとリード端子を絶縁材料で封止する工程と、
前記絶縁材料の一部を除去してリード端子の裏面側の一部を露出する工程と、
前記絶縁材料を除去した部分を切断して個々のパッケージを形成する工程と、
を具備することを特徴とする半導体装置の製造方法。An island for fixing a semiconductor chip; a plurality of lead terminals having tips close to the island; and a frame portion for holding the island and the lead terminal, wherein the island and the lead terminal A plurality of leads arranged in a matrix, the islands are connected to each other and the islands connected to each other are held by the frame, and lead terminals corresponding to one island are connected to and held by an island located next to the island. Preparing the frame;
Fixing a semiconductor chip to the surface of the island;
Electrically connecting the electrode formed on the surface of the semiconductor chip and the lead terminal; sealing the island and the lead terminal with an insulating material including the semiconductor chip;
Removing a portion of the insulating material to expose a portion of the back side of the lead terminal;
Cutting the portion from which the insulating material has been removed to form individual packages;
A method for manufacturing a semiconductor device, comprising: 前記絶縁材料を除去した後に前記露出したリード端子表面に金属メッキを施す工程を具備することを特徴とする請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing metal plating on the exposed lead terminal surface after removing the insulating material. 前記リードフレームには、前記アイランドと前記リード端子とが行列状に多数個配置されていることを特徴とする請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of the islands and the lead terminals are arranged in a matrix on the lead frame. 前記絶縁材料を除去する工程が、ダイシング装置のブレードによるものであることを特徴とする請求項１記載の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the insulating material is performed by a blade of a dicing apparatus.
JP32796897A 1997-11-28 1997-11-28 Manufacturing method of semiconductor device Expired - Fee Related JP3877402B2 (en)

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