WO2022202242A1

WO2022202242A1 - Semiconductor device and manufacturing method for semiconductor device

Info

Publication number: WO2022202242A1
Application number: PCT/JP2022/009631
Authority: WO
Inventors: 聡紀谷口; 賢太郎那須
Original assignee: ローム株式会社
Priority date: 2021-03-25
Filing date: 2022-03-07
Publication date: 2022-09-29
Also published as: JP2024099856A

Abstract

This semiconductor device comprises: a semiconductor element; a first lead on which the semiconductor element is mounted; a second lead which is disposed away from the first lead in a first direction perpendicular to the thickness direction of the first lead and which has electrical continuity with the semiconductor element; and a sealing resin which covers the semiconductor element. The first lead comprises: a first main surface to which the semiconductor element is joined; a first rear surface which faces the opposite direction of the first main surface in the thickness direction and which is exposed from the sealing resin; and a first internal surface which is connected to the first rear surface and which is covered by the sealing resin. The first internal surface comprises: a first convex part that projects in the direction toward which the first rear surface faces; and a first concave part that is arrayed, relative to the first convex part, in a second direction perpendicular to the first direction and the thickness direction and that is recessed, relative to the first convex part, in the direction toward which the first rear surface faces.

Description

Semiconductor device and method for manufacturing semiconductor device

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Various configurations have been proposed for semiconductor devices that include semiconductor elements. As an example of a semiconductor device, there is a semiconductor device in which a semiconductor element mounted on a die pad is connected to leads by wires and these are covered with a sealing resin. In such a semiconductor device, the back surface of the die pad may be exposed from the sealing resin and used as a back surface terminal. In this case, in order to prevent the die pad from falling out of the back surface of the sealing resin, the die pad has an inner surface facing the same side as the back surface and covered with the sealing resin. Patent Document 1 discloses a semiconductor device in which a semiconductor element is mounted on the main surface of the mounting portion of the first lead, and the rear surface of the mounting portion is exposed from the sealing resin and becomes a rear surface terminal. In the semiconductor device, the first lead has a recess on the back side of the mounting portion recessed in the z-direction from the back surface of the mounting portion.

The inner surface is flat because it is formed by half-etching when the lead frame is formed by etching the metal plate. Therefore, the thermal stress generated by the difference in linear expansion coefficient between the die pad and the encapsulating resin may cause the encapsulating resin to peel off from the inner surface.

Japanese Unexamined Patent Application Publication No. 2021-27116

The present disclosure has been conceived under the circumstances described above, and has an object to provide a semiconductor device capable of suppressing peeling of the sealing resin on the inner surface, and a method of manufacturing the same.

A semiconductor device provided by the present disclosure includes: a semiconductor element; first leads on which the semiconductor element is mounted; a second lead arranged and conducting to the semiconductor element; and a sealing resin covering the semiconductor element, wherein the first lead has a first main surface to which the semiconductor element is bonded and the thickness of the second lead. a first back surface facing in a direction opposite to the first main surface and exposed from the sealing resin; and a first inner surface connected to the first back surface and covered with the sealing resin. and the first inner surface includes a first convex portion protruding toward the side facing the first back surface, and a second convex portion perpendicular to the thickness direction and the first direction with respect to the first convex portion. and a first concave portion that is aligned in the direction and concave toward the first main surface facing the first convex portion.

A method of manufacturing a semiconductor device according to the present disclosure is a method of manufacturing a semiconductor device including a first lead having a first main surface and a first back surface facing opposite sides in the thickness direction, preparing a metal plate having a main surface and a back surface facing opposite sides; and a first mask for forming the first back surface and a plurality of rectangular masks in a checkered pattern on the back surface of the metal plate. forming a second mask arranged in a shape; forming a lead frame by etching the metal plate from the main surface side and the back surface side; and bonding a semiconductor element to the lead frame. forming a sealing resin covering the semiconductor element; and cutting the lead frame and the sealing resin.

According to the above configuration, peeling of the sealing resin on the inner surface of the semiconductor device can be suppressed.

Other features and advantages of the present disclosure will become clearer from the detailed description given below with reference to the accompanying drawings.

1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure; FIG. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1, and is a view through a sealing resin. 3 is a bottom view of the semiconductor device shown in FIG. 1. FIG. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. FIG. 5 is a cross-sectional view along line VV in FIG. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. FIG. 7 is a cross-sectional view taken along line VII--VII in FIG. FIG. 8 is a flow chart showing a method of manufacturing the semiconductor device shown in FIG. 9A to 9D are cross-sectional views showing steps in the method of manufacturing the semiconductor device shown in FIG. 10 is a plan view of the process shown in FIG. 9. FIG. 11 is a bottom view of the process shown in FIG. 9. FIG. 12A to 12C are cross-sectional views showing steps in the method of manufacturing the semiconductor device shown in FIG. 13A and 13B are cross-sectional views showing steps in the method of manufacturing the semiconductor device shown in FIG. 14A and 14B are cross-sectional views showing steps in the method of manufacturing the semiconductor device shown in FIG. 15 is a bottom view of the semiconductor device according to the first modification of the first embodiment; FIG. 16 is a bottom view of a semiconductor device according to a second modification of the first embodiment; FIG. 17 is a bottom view of a semiconductor device according to a third modification of the first embodiment; FIG. 18 is a bottom view of a semiconductor device according to a fourth modification of the first embodiment; FIG. 19 is a bottom view of a semiconductor device according to a fifth modification of the first embodiment; FIG. FIG. 20 is a bottom view showing the semiconductor device according to the second embodiment of the present disclosure; 21 is a bottom view of a semiconductor device according to a third embodiment of the present disclosure; FIG. FIG. 22 is a bottom view showing a semiconductor device according to a fourth embodiment of the present disclosure; 23 is a plan view showing a semiconductor device according to a fifth embodiment of the present disclosure; FIG.

Preferred embodiments of the present disclosure will be specifically described below with reference to the accompanying drawings.

In the present disclosure, unless otherwise specified, the terms “a certain entity A is formed on a certain entity B” and “a certain entity A is formed on a certain entity B” mean “a certain entity A is formed on a certain entity B”. It includes "being directly formed in entity B" and "being formed in entity B while another entity is interposed between entity A and entity B". Similarly, unless otherwise specified, ``an entity A is placed on an entity B'' and ``an entity A is located on an entity B'' mean ``an entity A is located on an entity B.'' It includes "directly placed on B" and "some entity A is placed on an entity B while another entity is interposed between an entity A and an entity B." Similarly, unless otherwise specified, ``an object A is located on an object B'' means ``an object A is adjacent to an object B and an object A is positioned on an object B. and "the thing A is positioned on the thing B while another thing is interposed between the thing A and the thing B". In addition, unless otherwise specified, ``an object A overlaps an object B when viewed in a certain direction'' means ``an object A overlaps all of an object B'' and ``an object A overlaps an object B.'' It includes "overlapping a part of a certain thing B".

A semiconductor device A10 according to the first embodiment of the present disclosure will be described with reference to FIGS. 1 to 7. FIG. The semiconductor device A10 includes leads 1, leads 2, a semiconductor element 6, wires 7, and a sealing resin 8. As shown in FIG.

FIG. 1 is a perspective view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for convenience of understanding, the outer shape of the sealing resin 8 is shown by an imaginary line (chain double-dashed line) through the sealing resin 8. As shown in FIG. FIG. 3 is a bottom view showing the semiconductor device A10. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. FIG. 5 is a cross-sectional view along line VV in FIG. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. FIG. 7 is a cross-sectional view taken along line VII--VII in FIG.

The semiconductor device A10 shown in these figures is a device that is surface-mounted on circuit boards of various devices. The application and function of the semiconductor device A10 are not particularly limited. The package format of the semiconductor device A10 is DFN (Dual Flatpack No-leaded). Note that the package format of the semiconductor device A10 is not limited to DFN. The shape of the semiconductor device A10 when viewed in the thickness direction is rectangular. For convenience of explanation, the thickness direction (planar view direction) of the semiconductor device A10 is defined as the z direction, and the direction along one side of the semiconductor device A1 orthogonal to the z direction (horizontal direction in FIGS. 2 and 3) is defined as the x direction, A direction perpendicular to the z-direction and the x-direction (vertical direction in FIGS. 2 and 3) is defined as the y-direction. The z-direction is an example of the "thickness direction", the y-direction is an example of the "first direction", and the x-direction is an example of the "second direction". Each dimension of the semiconductor device A10 is not particularly limited, and in this embodiment, for example, the x-direction dimension is about 0.6 mm, the y-direction dimension is about 1 mm, and the z-direction dimension is about 0.4 mm.

The

leads

1 and 2 are electrically connected to the semiconductor element 6.

Leads

1 and 2 are formed, for example, by etching a metal plate. The leads 1 and 2 are made of metal, preferably Cu or Ni, or an alloy thereof, 42 alloy, or the like. In this embodiment, an example in which the

leads

1 and 2 are made of Cu will be described. The thickness of the

leads

1 and 2 is not particularly limited, and is, for example, 0.05 to 0.3 mm, and about 0.125 mm in this embodiment.

As shown in FIG. 2, the lead 1 is arranged at the end of the semiconductor device A10 on the y1 side in the y direction and spreads all over the x direction. The lead 2 is arranged at the end on the y-direction y2 side of the semiconductor device A10 and spreads over the entire x-direction. Lead 2 is spaced apart from lead 1 in the y-direction.

The lead 1 supports the semiconductor element 6 and has a main surface 11, a back surface 12, an inner surface 13, and connecting end surfaces 14 and 15.

The main surface 11 and the back surface 12 face opposite to each other in the z direction. The main surface 11 faces the z-direction z2 side. The main surface 11 is a surface on which the semiconductor element 6 is mounted. In this embodiment, the shape of the main surface 11 is a rectangular shape having portions protruding on both sides in the y direction y1 and in the x direction. The portion protruding in the y direction y1 reaches the edge of the semiconductor device A10 on the y direction y1 side. The portion protruding in the x direction x1 reaches the edge of the semiconductor device A10 on the x direction x1 side. The portion protruding in the x direction x2 reaches the edge of the semiconductor device A10 on the x direction x2 side. Note that the number of each projecting portion is not limited. The rear surface 12 is exposed from the sealing resin 8 and becomes a rear surface terminal. In this embodiment, the back surface 12 has a rectangular shape elongated in the x direction.

The inner surface 13 is connected to the back surface 12 and is a portion where a part of the lead 1 is recessed from the back surface 12 toward the main surface 11 side. In this embodiment, as shown in FIG. 3, the inner surface 13 is formed on the y2 side, the y1 side, the x1 side, and the x2 side of the back surface 12 in the y direction. In addition, the shape and arrangement position of the inner surface 13 are not limited. For example, the inner surface 13 may be formed so as to surround the entire periphery of the back surface 12 or may not be formed on the y-direction y1 side of the back surface 12 . As shown in FIGS. 4 to 7, the thickness (dimension in the z direction) of the portion of the lead 1 where the inner surface 13 is located is smaller than the thickness of the portion where the back surface 12 is located, for example about half. The inner surface 13 is formed, for example, by half-etching. As shown in FIG. 3 , the inner surface 13 is covered with the sealing resin 8 without being exposed from the sealing resin 8 . This prevents the lead 1 from peeling off from the sealing resin 8 toward the z1 side in the z direction.

The inner surface 13 (hereinafter referred to as “inner surface 131”) formed on the lead 2 side (y2 side in the y direction) with respect to the rear surface 12 in the y direction has a plurality of protrusions 16 and a plurality of recesses 17. I have.

As shown in FIGS. 4 to 7, each convex portion 16 protrudes from the periphery toward the side facing the back surface 12 (the z-direction z1 side). This is a portion located on the z-direction z1 side of the imaginary line a (indicated by a two-dot chain line in FIGS. 4 to 7) indicating the position. The entire inner surface 13 is covered with the sealing resin 8 , and the protrusions 16 are also not exposed from the sealing resin 8 . The z-direction dimension T2 (see FIG. 4) of each protrusion 16 from the main surface 11 is not particularly limited, but is 50% or more and 90% or less of the z-direction dimension T1 from the main surface 11 to the back surface 12 of the lead 1. is desirable.

Each recess 17 is recessed on the side (z direction z2 side) facing the main surface 11 with respect to each protrusion 16, and is a portion of the inner surface 131 located on the z direction z2 side from the imaginary line a. . The dimension T3 of the unevenness difference, which is the dimension in the z direction from the bottom of the concave portion 17 to the top of the convex portion 16, is not particularly limited, but is preferably 10% or more and 50% or less of the dimension T1. The protrusions 16 and the recesses 17 are aligned in the x direction as shown in FIGS. 4 and 5, and are also aligned in the y direction as shown in FIGS.

As shown in FIG. 3, the convex portions 16 are arranged in a checkered pattern when viewed in the z direction. That is, the convex portions 16 and the concave portions 17 are alternately arranged in the x direction, and the convex portions 16 and the concave portions 17 are also alternately arranged in the y direction. In this embodiment, the convex portions 16 are arranged in six rows in the x direction and three rows in the y direction. In FIG. 3, each convex portion 16 is hatched for convenience of understanding. Note that the number of projections 16 arranged in the x-direction and the y-direction is not particularly limited. The number of each arrangement is appropriately set according to the size of the inner surface 131 as viewed in the z direction and the size of the convex portion 16 as viewed in the z direction. It is desirable that the number of arrays in both the x-direction and the y-direction should be three or more. The shape of each projection 16 when viewed in the z direction is not particularly limited, and may be a square shape, a rectangular shape elongated in the x direction, or a rectangular shape elongated in the y direction. good too. Also, the shape of each projection 16 as viewed in the z-direction may be other shapes such as a circular shape or an elliptical shape.

The plurality of protrusions 16 includes

protrusions

161 , 162 , 163 and 164 . The convex portion 161 is arranged on the inner surface 13 closest to the x1 side in the x direction and closest to the y1 side in the y direction. The convex portion 162 is arranged adjacent to the convex portion 161 on the x-direction x2 side of the convex portion 161 . That is, the convex portion 162 is arranged in the x direction with respect to the convex portion 161 . A recess 17 is arranged between the protrusion 161 and the protrusion 162 . In other words, the concave portion 17 is arranged in the x direction with respect to the convex portion 161 . The convex portion 163 is arranged adjacent to the convex portion 161 on the y-direction y2 side of the convex portion 161 . That is, the convex portion 163 is arranged in the y direction with respect to the convex portion 161 . A recess 17 is arranged between the protrusion 161 and the protrusion 163 . That is, the recess 17 is arranged in the y direction with respect to the protrusion 161 .

The convex portion 164 is arranged between the

convex portions

161 and 162 in the x direction and between the

convex portions

161 and 163 in the y direction. The convex portion 164 is located on a line segment b (indicated by a chain double-dashed line in FIG. 3) connecting the vertex of the convex portion 162 and the vertex of the convex portion 163 when viewed in the z direction. As will be described later, the protrusions 16 and the recesses 17 of the inner surface 13 are formed by etching from the back surface 12 side using a mask arranged in a checkered pattern.

The connecting end surfaces 14 and 15 are surfaces orthogonal to the main surface 11 and the back surface 12 and are connected to the main surface 11 and the inner surface 13 . The connecting end surfaces 14 and 15 are exposed from the sealing resin 8 . There is one connecting end face 14, and it faces the y direction y1 side. There are two connecting end faces 15, one connecting end face 15 faces the x direction x1 side, and the other connecting end face 15 faces the x direction x2 side. The connecting end surfaces 14 and 15 are formed by dicing in the cutting process in the manufacturing process.

It should be noted that the shape of the lead 1 is not limited to the one described above. For example, the back surface 12 extends to the edge of the semiconductor device A10 on the y-direction y1 side, the connection end surface 14 extends to the edge on the z-direction z1 side of the semiconductor device A10, and the back surface 12 and the connection end surface 14 are connected to form a continuous line. It may be exposed from the sealing resin 8 . The shape of the lead 1 is appropriately designed according to the application and specifications.

The lead 2 is electrically connected to the semiconductor element 6 and has a main surface 21, a back surface 22, an inner surface 23, and connecting end surfaces 24 and 25.

The main surface 21 and the back surface 22 face opposite sides in the z direction. The main surface 21 faces the same side as the main surface 11 of the lead 1 (z2 side in the z direction). The main surface 21 is the surface to which the wire 7 is joined. In this embodiment, the main surface 21 has a rectangular shape that is long in the x direction and has portions that protrude on the y2 side in the y direction and on both sides in the x direction. The portion protruding in the y direction y2 reaches the edge of the semiconductor device A10 on the y direction y2 side. The portion protruding in the x direction x1 reaches the edge of the semiconductor device A10 on the x direction x1 side. The portion protruding in the x direction x2 reaches the edge of the semiconductor device A10 on the x direction x2 side. Note that the number of each projecting portion is not particularly limited. The back surface 22 faces the same side as the back surface 12 of the lead 1 (z1 side in the z direction). The rear surface 22 is exposed from the sealing resin 8 and becomes a rear surface terminal. In this embodiment, the shape of the back surface 22 is a rectangular shape elongated in the x direction.

The inner surface 23 is connected to the back surface 22 and is a portion in which a part of the lead 2 is recessed from the back surface 22 toward the main surface 21 side. In this embodiment, as shown in FIG. 3, the inner surface 23 is formed on the y-direction y2 side, the x-direction x1 side, and the x-direction x2 side of the back surface 22, respectively. The shape and arrangement position of the inner surface 23 are not particularly limited. For example, the inner surface 23 may be formed so as to surround the entire periphery of the back surface 22 or may be formed on the y-direction y1 side of the back surface 22 as well. As shown in FIGS. 4 to 7, the thickness (dimension in the z direction) of the portion of the lead 2 where the inner surface 23 is located is smaller than the thickness of the portion where the back surface 22 is located, for example about half. The inner surface 23 is formed, for example, by half-etching. As shown in FIG. 3 , the inner surface 23 is covered with the sealing resin 8 without being exposed from the sealing resin 8 . This prevents the lead 2 from peeling off from the sealing resin 8 toward the z1 side in the z direction.

The connecting end surfaces 24 and 25 are surfaces perpendicular to the main surface 21 and the back surface 22 and are connected to the main surface 21 and the inner surface 23 . The connecting end surfaces 24 and 25 are exposed from the sealing resin 8 . There is one connecting end surface 24, and it faces the y direction y2 side. There are two connecting end faces 25, one connecting end face 25 faces the x direction x1 side, and the other connecting end face 25 faces the x direction x2 side. The connecting end surfaces 24 and 25 are formed by dicing in the cutting process in the manufacturing process.

It should be noted that the shape of the lead 2 is not limited to the one described above. For example, the back surface 22 extends to the edge of the semiconductor device A10 on the y-direction y2 side, the connection end surface 24 extends to the edge on the z-direction z1 side of the semiconductor device A10, and the back surface 22 and the connection end surface 24 are connected to form a continuous line. It may be exposed from the sealing resin 8 . The shape of the lead 2 is appropriately designed according to the application and specifications.

The semiconductor element 6 is an element that exerts electrical functions of the semiconductor device A10. The type of semiconductor element 6 is not particularly limited. In this embodiment, the semiconductor element 6 is a diode. The semiconductor element 6 has an element body 60 , a first electrode 631 and a second electrode 632 .

The element body 60 has a rectangular plate shape when viewed in the z direction. The element body 60 is made of a semiconductor material, and is made of Si (silicon) in this embodiment. The material of element body 60 is not particularly limited, and may be other materials such as SiC (silicon carbide) and GaN (gallium nitride). The element body 60 has an element main surface 61 and an element back surface 62 . The element main surface 61 and the element back surface 62 face opposite to each other in the z direction. The element main surface 61 faces the z-direction z2 side. The element back surface 62 faces the z-direction z1 side. The first electrode 631 is arranged on the element main surface 61 . The second electrode 632 is arranged on the element back surface 62 . In this embodiment, the first electrode 631 is the anode electrode and the second electrode 632 is the cathode electrode.

The semiconductor element 6 is bonded to the center (or approximately the center) of the main surface 11 of the lead 1 via a bonding material 79, as shown in FIGS. In this embodiment, the bonding material 79 is a conductive bonding material such as solder. Note that the bonding material 79 may be other conductive bonding materials such as silver paste and sintered silver bonding material. The semiconductor element 6 has the element rear surface 62 bonded to the main surface 11 of the lead 1 by the bonding material 79 . A second electrode 632 of the semiconductor element 6 is conductively connected to the lead 1 via a bonding material 79 . As a result, the lead 1 is conductively connected to the second electrode 632 (anode electrode) of the semiconductor element 6 and functions as an anode terminal.

The first electrode 631 of the semiconductor element 6 is conductively connected to the lead 2 via the wire 7, as shown in FIG. As a result, the lead 2 is conductively connected to the first electrode 631 (cathode electrode) of the semiconductor element 6 and functions as a cathode terminal.

The wire 7 connects the semiconductor element 6 and the lead 2 to make them conductive. The wire 7 is made of metal such as Cu, Au, Ag or Al. In addition, the material of the wire 7 is not particularly limited. As shown in FIG. 2, the wire 7 is joined to the first electrode 631 of the semiconductor element 6 and the main surface 21 of the lead 2 . In this embodiment, the first electrode 631 is connected to the lead 2 with one wire 7 . Note that the number of wires 7 is not particularly limited. Also, semiconductor element 6 and leads 2 may be connected by a conductive connection member (for example, a metal plate, a metal ribbon, or the like) other than wire 7 .

The sealing resin 8 partially covers the

leads

1 and 2, the semiconductor element 6, the bonding material 79, and the wires 7 as a whole. Sealing resin 8 is made of, for example, black epoxy resin. In addition, the material of the sealing resin 8 is not particularly limited.

The sealing resin 8 has a resin main surface 81 , a resin back surface 82 and four resin side surfaces 83 . The resin main surface 81 and the resin back surface 82 face opposite sides in the z-direction. The resin main surface 81 is a surface facing the z-direction z2 side, and the resin back surface 82 is a surface facing the z-direction z1 side.

The four resin side surfaces 83 are surfaces orthogonal to the resin main surface 81 and the resin back surface 82 and connecting the resin main surface 81 and the resin back surface 82 . Each resin side surface 83 faces outward in the x direction or the y direction. Each resin side surface 83 is formed by dicing in a cutting step in the manufacturing process. The four resin sides 83 include a resin side 831 , a resin side 832 , a resin side 833 , and a resin side 834 . The resin side surface 831 and the resin side surface 832 face opposite sides in the x direction. The resin side surface 831 is a surface arranged on the x-direction x1 side and facing the x-direction x1 side. The resin side surface 832 is a surface arranged on the x-direction x2 side and facing the x-direction x2 side. The resin side surface 833 and the resin side surface 834 face opposite sides in the y direction. The resin side surface 833 is a surface arranged on the y-direction y1 side and facing the y-direction y1 side. The resin side surface 834 is a surface that is arranged on the y-direction y2 side and faces the y-direction y2 side.

As shown in FIGS. 3, 6 and 7, the back surface 12 of the lead 1 and the back surface 22 of the lead 2 are exposed from the resin back surface 82 of the sealing resin 8 and are flush with the resin back surface 82 . The connection end surface 15 of the lead 1 facing the x-direction x1 side and the connection end surface 25 of the lead 2 facing the x-direction x1 side are exposed from the resin side surface 831 and are flush with the resin side surface 831 . The connection end surface 15 of the lead 1 facing the x-direction x2 side and the connection end surface 25 of the lead 2 facing the x-direction x2 side are exposed from the resin side surface 832 and are flush with the resin side surface 832 . The connecting end surface 14 of the lead 1 is exposed from the resin side surface 833 and is flush with the resin side surface 833 . The connecting end surface 24 of the lead 2 is exposed from the resin side surface 834 and is flush with the resin side surface 834 .

Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to FIGS. 8 to 14. FIG.

FIG. 8 is a flow chart showing the manufacturing method of the semiconductor device A10. 9 to 14 are diagrams showing steps related to the method of manufacturing the semiconductor device A10. 9 and 12 to 14 are sectional views corresponding to FIG. 6. FIG. 10 is a plan view corresponding to FIG. 2. FIG. 11 is a bottom view, corresponding to FIG. 3. FIG. Note that the x-direction, y-direction, and z-direction shown in FIGS. 9 to 14 are the same directions as in FIGS.

As shown in FIG. 8, the method for manufacturing the semiconductor device A10 includes a lead frame forming step S10, a die bonding step S20, a wire bonding step S30, a sealing step S40, and a cutting step S50.

The lead frame creation step S10 is a step of creating a lead frame from a metal plate. In this step, first, a metal plate 91 (see FIG. 9) that will be the material of the lead frame is prepared (S11). The metal plate 91 is made of Cu in this embodiment. The metal plate 91 has a main surface 911 and a back surface 912 facing opposite to each other in the z direction.

Next, as shown in FIGS. 9 to 11, a mask 92 is formed on the metal plate 91 (S12). Masks 92 are formed on both main surface 911 and back surface 912 of metal plate 91 . The mask 92 is formed, for example, by forming a photosensitive resin layer on the main surface 911 and the back surface 912 of the metal plate 91 and exposing and developing the layers. Note that the method of forming the mask 92 is not particularly limited. Mask 92 (see FIG. 10) formed on main surface 911 is a mask for forming main surface 11 of lead 1 and main surface 21 of lead 2 . Masks 92 (see FIG. 11) formed on back surface 912 include

masks

921 , 922 , and 925 . Mask 921 is a mask for forming rear surface 12 of lead 1 . A mask 925 is a mask for forming the back surface 22 of the lead 2 .

A mask 922 is a mask for forming the inner surface 131 of the lead 1 . The mask 922 has a plurality of rectangular masks 923 arranged in a checkered pattern. That is, in the mask 922, the masks 923 and the openings 924 are alternately arranged in the x direction, and the masks 923 and the openings 924 are also alternately arranged in the y direction. In this embodiment, the masks 923 are arranged in six rows in the x direction and three rows in the y direction. Note that the number of arrays of the masks 923 in the x direction and the y direction is not particularly limited.

Next, isotropic etching is performed from both the main surface 911 side and the back surface 912 side of the metal plate 91 on which the mask 92 is formed (S13). The etching process is performed, for example, by immersing the metal plate 91 with the mask 92 formed thereon in an etchant that dissolves the components of the metal plate 91 . The etching treatment may be dry etching. By the etching process, portions of the metal plate 91 where the mask 92 is not formed are etched to form a lead frame 95 as shown in FIG. A principal surface 911 of the metal plate 91 is a partially etched principal surface 951 . Also, the back surface 912 of the metal plate 91 is a back surface 952 that is partly etched.

The lead frame 95 includes a portion penetrating in the z-direction and a portion half-etched only from the z-direction z1 side. A portion of the metal plate 91 where the mask 92 is not formed on the main surface 911 and the mask 92 is not formed on the back surface 912 is penetrated by etching from both sides. As a result, in the lead frame 95, the portion that will become the lead 1 and the portion that will become the lead 2 of the same semiconductor device A10 are formed in a state separated from each other. The main surface 951 of the lead 1 portion of the lead frame 95 is the main surface 11 , and the main surface 951 of the lead 2 portion is the main surface 21 . Further, the back surface 952 of the lead 1 portion of the lead frame 95 becomes the back surface 12 , and the back surface 952 of the lead 2 portion becomes the back surface 22 . A portion of the metal plate 91 where the mask 92 is formed on the main surface 911 and the mask 921 and the mask 925 are not formed on the back surface 912 is etched only from the z-direction z1 side, and is etched from the back surface 952 to the main surface. An inner surface 953 recessed on the 951 side is formed. The inner surface 953 of the lead 1 portion of the lead frame 95 is the inner surface 13 , and the inner surface 953 of the lead 2 portion is the inner surface 23 .

In the inner surface 953 of the portion of the lead frame 95 that will become the lead 1, the portion facing the mask 922 is etched to form the convex portion 16 and the concave portion 17 by etching the back surface 912 on which the mask 922 was formed in FIG. ing. The portion of the back surface 912 on which the mask 922 is formed, where the opening 924 is located, is etched in the same manner as the portion where the mask 92 is not formed. On the other hand, isotropic etching proceeds in directions other than the z-direction, so that the portion of the back surface 912 where the mask 922 is formed, where the mask 923 is located, is also etched from the periphery. Since the portion where the mask 923 is positioned is less etched than the portion where the opening 924 is positioned, the protrusion 16 projecting from the periphery is formed. On the other hand, a concave portion 17 that is recessed from the convex portion 16 is formed in a portion where the opening portion 924 is located. Since the plurality of masks 923 are arranged in a checkered pattern in the mask 922, the convex portions 16 are also formed in a checkered pattern.

The mask 92 is then removed. The lead frame 95 is produced by the above. In the lead frame 95, a plurality of portions to be the semiconductor device A10 are connected to each other.

The die bonding step S20 is a step of bonding the semiconductor element 6 to the lead frame 95. In this step, as shown in FIG. 13, the semiconductor elements 6 are bonded to the main surfaces 951 of the portions of the lead frame 95 that will become the leads 1 via the bonding material 79 . In this step, first, a solder paste that will become the joining material 79 is applied to the center of each main surface 951 of the portion that will become each lead 1 . Next, semiconductor elements 6 are placed on the applied solder paste. Next, a reflow process is performed to melt and then solidify the solder paste. As described above, the semiconductor element 6 is joined to the lead frame 95 . Incidentally, the bonding method of the semiconductor element 6 in the die bonding step S20 is not particularly limited.

The wire bonding step S30 is a step of forming the wires 7. In this step, as shown in FIG. 13, the wire 7 is joined to the first electrode 631 of the semiconductor element 6 and the main surface 951 of the portion of the lead frame 95 that will become each lead 2 . The wire 7 is formed by a wire bonder using a capillary. Specifically, first, the tip of the wire is protruded from the capillary of the wire bonder and melted to form the tip of the wire into a ball shape. This ball-shaped tip is pressed against the first electrode 631 of the semiconductor element 6 . Next, the wire is pulled out from the capillary and the capillary is moved to press the wire against the main surface 951 of the portion of the lead frame 95 that will become each lead 2 . Then, while holding down the wire with a clamper of the capillary, the capillary is lifted to cut the wire. The wire 7 is formed by the above. A method for forming the wires 7 in the wire bonding step S30 is not particularly limited.

The sealing step S40 is a step of forming the sealing resin 96. In this step, a resin material is cured to form a sealing resin 96 that covers a portion of the lead frame 95, the semiconductor element 6, and the wires 7, as shown in FIG. The process is performed, for example, by well-known transfer molding using a mold. Specifically, the lead frame 95 to which the semiconductor element 6 and the wire 7 are joined is set in a molding machine. Next, the fluidized resin material is poured into a cavity in a mold for molding. Then, the resin material is cured. As described above, the sealing resin 96 is formed. The back surface 952 of the lead frame 95 is exposed from the sealing resin 96 by setting the lead frame 95 with the back surface 952 in contact with the mold. Also, the back surface 952 of the lead frame 95 and the back surface 962 of the sealing resin 96 are flush with each other. Also, since the resin material flows between the mold and the inner surface 953 , the inner surface 953 is covered with the sealing resin 96 . The method of forming the sealing resin 96 in the sealing step S40 is not particularly limited.

The cutting step S50 is a step of cutting the lead frame 95 and the sealing resin 96 . In this step, for example, a blade is used to cut the lead frame 95 and the sealing resin 96 into individual pieces. As a result, an individual piece to be the semiconductor device A10 is formed. The leads 1 and 2 are obtained by cutting the lead frame 95 . The cut surfaces formed at this time become the connection end surfaces 14 and 15 of the lead 1 and the connection end surfaces 24 and 25 of the lead 2 . Further, the sealing resin 8 is formed by cutting the sealing resin 96 . The cut surface formed at this time becomes the resin side surface 83 . Note that the cutting method in the cutting step S50 is not particularly limited. Through the above steps, the semiconductor device A10 described above is manufactured.

Next, the effects of the semiconductor device A10 will be described.

According to this embodiment, the inner surface 131 of the lead 1 has a plurality of protrusions 16 and a plurality of recesses 17 . Compared to the case where the plurality of protrusions 16 and the plurality of recesses 17 are not provided, the contact area between the inner surface 131 and the sealing resin 8 is increased. Therefore, the adhesion of the sealing resin 8 to the inner surface 131 is improved. Thereby, the semiconductor device A10 can suppress peeling of the sealing resin 8 on the inner surface 131 .

Also, according to the present embodiment, the plurality of convex portions 16 are arranged in a checkered pattern when viewed in the z direction. Since the protrusions 16 and the recesses 17 are alternately arranged in both the x-direction and the y-direction, the thermal stress generated in the x-direction and the thermal stress in the y-direction on the inner surface 131 Peeling of the sealing resin 8 can be suppressed. Further, when a crack occurs between the inner surface 131 of the lead 1 and the sealing resin 8, the crack can be prevented from growing in the direction in which the convex portion 16 and the concave portion 17 are arranged.

Further, according to the present embodiment, in the lead frame production process, a mask 922 in which a plurality of rectangular masks 923 are arranged in a checkered pattern is formed on the back surface 912 of the metal plate 91, and isotropic from the back surface 912 side. An internal surface 131 is formed by etching. As a result, the lead frame forming process can easily form the inner surface 131 in which the plurality of protrusions 16 are arranged in a checkered pattern when viewed in the z direction.

In addition, in the present embodiment, a case has been described in which the convex portions 16 are arranged in a checkered pattern when viewed in the z direction, but the present invention is not limited to this. A method of arranging the projections 16 as viewed in the z-direction is not particularly limited. Also, in the present embodiment, the case where the shape of each convex portion 16 as viewed in the z direction is rectangular has been described, but the shape is not limited to this. The shape of each convex portion 16 when viewed in the z-direction is not particularly limited, and may be another polygonal shape or another shape such as a circular shape.

15 to 19 show modifications of the inner surface 131 according to the first embodiment. In these figures, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and redundant explanations are omitted.

FIG. 15 is a bottom view showing the semiconductor device A11 according to the first modification of the first embodiment, and corresponds to FIG. In the semiconductor device A11, the projections 16 arranged on the inner surface 131 have smaller dimensions in the x-direction and the y-direction than the semiconductor device A10, and the projections 16 are arranged in a larger number. In this modification, the convex portions 16 are arranged in nine rows in the x direction and five rows in the y direction on the inner surface 131 . The number of projections 16 arranged in the x-direction and the y-direction is not particularly limited, and may be larger or smaller than in this modification. Also, it may be less than in the case of the semiconductor device A10 according to the first embodiment. The convex portions 16 may be arranged in two or more rows in the x direction, and may also be arranged in two or more rows in the y direction.

FIG. 16 is a bottom view showing the semiconductor device A12 according to the second modification of the first embodiment, corresponding to FIG. The semiconductor device A12 differs from the semiconductor device A10 in the method of arranging the plurality of protrusions 16 on the inner surface 131 as viewed in the z direction. In the semiconductor device A12, the protrusions 16 and the recesses 17 are alternately arranged in the x direction, and the rows of the same arrangement are arranged across the recesses 17 in the y direction. That is, the arrangement of the protrusions 16 in the semiconductor device A12 is similar to the arrangement of the protrusions 16 in the semiconductor device A10, in which the protrusions 16 in the central row in the y direction (the protrusion 164 and the two protrusions aligned in the x direction x2 side thereof) are arranged. 16) is deleted. In this embodiment, the convex portions 16 are arranged in three rows in the x direction and two rows in the y direction. Note that the number of projections 16 arranged in the x-direction and the y-direction is not particularly limited. The number of each arrangement is appropriately set according to the size of the inner surface 131 and the size of the convex portion 16 when viewed in the z direction. Also, the arrangement intervals of the projections 16 in the x-direction or the y-direction, that is, the dimensions of the recesses 17 in the x-direction or the y-direction may be reduced or increased.

FIG. 17 is a bottom view showing the semiconductor device A13 according to the third modification of the first embodiment, corresponding to FIG. The semiconductor device A13 differs from the semiconductor device A10 in the shape and arrangement method of the plurality of protrusions 16 on the inner surface 131 as viewed in the z direction. In the semiconductor device A13, each projection 16 has a rectangular shape that is long in the y direction when viewed in the z direction, and three projections 16 are arranged with the recess 17 interposed therebetween in the x direction. That is, the convex portions 16 and the concave portions 17 are alternately arranged in the x-direction and extend in the y-direction. The number of projections 16 arranged in the x direction is not particularly limited. The number of arrays is appropriately set according to the x-direction dimension of the inner surface 131 and the x-direction dimension of the projections 16 and the recesses 17 . Also, the arrangement interval of each convex portion 16 in the x direction, that is, the dimension of each concave portion 17 in the x direction may be reduced or increased.

FIG. 18 is a bottom view showing the semiconductor device A14 according to the fourth modification of the first embodiment, corresponding to FIG. The semiconductor device A14 differs from the semiconductor device A10 in the size and arrangement method of the plurality of protrusions 16 on the inner surface 131 as viewed in the z direction. In the semiconductor device A14, each projection 16 is arranged irregularly. In addition, the size of each projection 16 as viewed in the z direction is smaller than that of the semiconductor device A10. Note that the size of each convex portion 16 when viewed in the z direction is not particularly limited.

FIG. 19 is a bottom view showing the semiconductor device A15 according to the fifth modification of the first embodiment, corresponding to FIG. The semiconductor device A15 differs from the semiconductor device A10 in the shape of the plurality of protrusions 16 on the inner surface 131 as viewed in the z direction. In the semiconductor device A15, each projection 16 has a circular shape when viewed in the z direction. Note that the shape of each projection 16 as viewed in the z-direction is not limited to a rectangular shape or a circular shape, and may be other shapes such as other polygonal shapes and elliptical shapes.

Also, in the present embodiment, the case where each convex portion 16 is arranged on the inner surface 131 has been described, but the present invention is not limited to this. Each protrusion 16 may be arranged on another inner surface 13 . Also, each convex portion 16 may be arranged on the inner surface 23 of the lead 2 . Even if each convex portion 16 is arranged on another inner surface 13 or inner surface 23, the shape, size, and arrangement method of each convex portion 16 when viewed in the z-direction are not particularly limited. Even in these cases, variations similar to those of the first to fifth modifications are conceivable.

20 to 23 show other embodiments of the present disclosure. In these figures, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and redundant explanations are omitted.

FIG. 20 is a diagram for explaining the semiconductor device A20 according to the second embodiment of the present disclosure. FIG. 20 is a bottom view of the semiconductor device A20, corresponding to FIG. The semiconductor device A20 according to the present embodiment differs from the semiconductor device A10 according to the first embodiment in that a plurality of protrusions 16 are arranged on the inner surface 13 other than the inner surface 131. FIG. The configuration and operation of other portions of this embodiment are the same as those of the first embodiment. In addition, each part of said 1st Embodiment may be combined arbitrarily.

The area of the inner surface 131 of the lead 1 according to this embodiment is smaller than that of the first embodiment. On the other hand, among the inner surfaces 13, the area of the inner surface 13 (hereinafter referred to as "inner surface 132") formed on the opposite side (y1 side in the y direction) of the lead 2 with respect to the back surface 12 in the y direction. is larger than in the first embodiment. In this embodiment, the plurality of protrusions 16 are arranged on the inner surface 132 instead of the inner surface 131 . In this embodiment, the shape, size, and arrangement method of each projection 16 as viewed in the z-direction are the same as those of the first modification of the first embodiment. The shape, size, and arrangement method of each projection 16 when viewed in the z direction are not particularly limited, and various variations shown in the first embodiment are conceivable.

According to this embodiment, the inner surface 132 of the lead 1 has a plurality of protrusions 16 and a plurality of recesses 17 . Compared to the case where the plurality of protrusions 16 and the plurality of recesses 17 are not provided, the contact area between the inner surface 132 and the sealing resin 8 is increased. Therefore, the adhesion of the sealing resin 8 to the inner surface 132 is improved. Thereby, the semiconductor device A20 can suppress peeling of the sealing resin 8 on the inner surface 132 . Moreover, the semiconductor device A20 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.

FIG. 21 is a diagram for explaining the semiconductor device A30 according to the third embodiment of the present disclosure. FIG. 21 is a bottom view of the semiconductor device A30, corresponding to FIG. The semiconductor device A30 according to the present embodiment is different from the semiconductor device A10 according to the first embodiment in that a plurality of protrusions 16 are also arranged on the inner surface 13 other than the inner surface 131 . The configuration and operation of other portions of this embodiment are the same as those of the first embodiment. Note that each part of the above first and second embodiments may be combined arbitrarily.

The area of the back surface 12 of the lead 1 according to this embodiment is smaller than that of the first embodiment. On the other hand, among the inner surfaces 13, the inner surface 132, the inner surface 13 formed on the x-direction x1 side of the back surface 12 (hereinafter referred to as the “inner surface 133”), and the x-direction x2 side of the back surface 12 The area of the formed inner surface 13 (hereinafter referred to as "inner surface 134") is larger than in the first embodiment. In this embodiment, the inner surfaces 131 to 134 are connected and formed so as to surround the entire circumference of the back surface 12 . In this embodiment, the plurality of protrusions 16 are arranged not only on the inner surface 131 but also on the

inner surfaces

132 , 133 , and 134 . In this embodiment, the shape, size, and arrangement method of each projection 16 as viewed in the z-direction are the same as those of the first modification of the first embodiment. The shape, size, and arrangement method of each projection 16 when viewed in the z direction are not particularly limited, and various variations shown in the first embodiment are conceivable.

According to this embodiment, the inner surfaces 131 to 134 of the lead 1 are provided with a plurality of protrusions 16 and a plurality of recesses 17, respectively. Compared to the case where the plurality of protrusions 16 and the plurality of recesses 17 are not provided, the contact area between the inner surfaces 131 to 134 and the sealing resin 8 is increased. Therefore, the adhesion of the sealing resin 8 to the inner surfaces 131-134 is improved. Thereby, the semiconductor device A30 can suppress peeling of the sealing resin 8 on the inner surfaces 131 to 134 . Further, the semiconductor device A30 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.

FIG. 22 is a diagram for explaining a semiconductor device A40 according to the fourth embodiment of the present disclosure. FIG. 22 is a bottom view of the semiconductor device A40, corresponding to FIG. The semiconductor device A40 according to the present embodiment differs from the semiconductor device A10 according to the first embodiment in that a plurality of protrusions 16 are also arranged on the inner surface 23 of the lead 2 . The configuration and operation of other portions of this embodiment are the same as those of the first embodiment. Note that each part of the above first to third embodiments may be combined arbitrarily.

The inner surface 23 of the lead 2 according to the present embodiment is formed on the lead 1 side (the y1 side in the y direction) with respect to the rear surface 22 in the y direction (hereinafter referred to as "inner surface 231"). is further provided. In this embodiment, the plurality of protrusions 16 are arranged not only on the inner surface 131 of the lead 1 but also on the inner surface 231 of the lead 2 . Note that the plurality of protrusions 16 may be arranged on another inner surface 23 of the lead 2 . In this embodiment, the shape, size, and arrangement method of each projection 16 as viewed in the z-direction are the same as those of the first modification of the first embodiment. The shape, size, and arrangement method of each projection 16 when viewed in the z direction are not particularly limited, and various variations shown in the first embodiment are conceivable.

According to this embodiment, the inner surface 131 of lead 1 and the inner surface 231 of lead 2 are provided with a plurality of protrusions 16 and a plurality of recesses 17, respectively. The contact area between the

inner surfaces

131 and 231 and the sealing resin 8 is increased compared to the case where the plurality of protrusions 16 and the plurality of recesses 17 are not provided. Therefore, the adhesion of the sealing resin 8 to the

inner surfaces

131, 231 is improved. Thereby, the semiconductor device A40 can suppress peeling of the sealing resin 8 on the

inner surfaces

131 and 231 . In addition, the semiconductor device A40 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.

FIG. 23 is a diagram for explaining the semiconductor device A50 according to the fifth embodiment of the present disclosure. FIG. 23 is a plan view showing the semiconductor device A50, corresponding to FIG. The semiconductor device A50 according to the present embodiment is different from the semiconductor device A10 according to the first embodiment in the type of the semiconductor element 6, and is further provided with leads 3, unlike the semiconductor device A10 according to the first embodiment. different. The configuration and operation of other portions of this embodiment are the same as those of the first embodiment. It should be noted that each part of the above-described first to fourth embodiments may be combined arbitrarily.

The semiconductor device A50 according to this embodiment further includes leads 3 . Lead 3 is spaced apart from lead 1 and lead 2 . In this embodiment, the lead 2 is arranged on the y-direction y2 side of the semiconductor device A50 at the end portion on the x-direction x1 side (the upper left corner in FIG. 23), and the lead 3 is arranged on the y-direction y2 side of the semiconductor device A50. It is arranged at the end on the direction x2 side (upper right corner in FIG. 23). That is, the lead 3 is arranged on the same side as the lead 2 with respect to the lead 1 in the y direction. The lead 3 is electrically connected to the semiconductor element 6 and has a principal surface 31 , a back surface 32 , an inner surface 33 , and connecting end surfaces 34 and 35 .

The main surface 31 and the back surface 32 face opposite sides in the z direction. The main surface 31 faces the same side as the main surface 11 of the lead 1 (z2 side in the z direction). The main surface 31 is the surface to which the wire 7 is joined. In this embodiment, the shape of the main surface 31 is a rectangular shape having portions protruding in the y direction y2 and in the x direction x2. The portion protruding in the y direction y2 reaches the edge of the semiconductor device A50 on the y direction y2 side. The portion protruding in the x direction x2 reaches the edge of the semiconductor device A50 on the x direction x2 side. Note that the number of each projecting portion is not particularly limited. The back surface 32 faces the same side as the back surface 12 of the lead 1 (z1 side in the z direction). The rear surface 32 is exposed from the sealing resin 8 and becomes a rear surface terminal. In this embodiment, the shape of the back surface 32 is rectangular.

The inner surface 33 is connected to the back surface 32 and is a portion where a part of the lead 3 is recessed from the back surface 32 toward the main surface 31 side. In this embodiment, the inner surface 33 is formed on the y-direction y2 side and the x-direction x2 side of the back surface 32, respectively. The shape and arrangement position of the inner surface 33 are not particularly limited. For example, the inner surface 33 may be formed so as to surround the entire periphery of the back surface 32, or may be formed on the y-direction y1 side or the x-direction x1 side of the back surface 32 as well. The thickness (dimension in the z direction) of the portion of the lead 3 where the inner surface 33 is located is smaller than the thickness of the portion where the back surface 32 is located, for example about half. The inner surface 33 is formed, for example, by half-etching. The inner surface 33 is covered with the sealing resin 8 without being exposed from the sealing resin 8 . This prevents the leads 3 from peeling off from the sealing resin 8 toward the z1 side in the z direction.

The connecting end surfaces 34 , 35 are surfaces perpendicular to the main surface 31 and the back surface 32 and are connected to the main surface 31 and the inner surface 33 . The connecting end surfaces 34 and 35 are exposed from the sealing resin 8 . There is one connecting end surface 24, and it faces the y direction y2 side. There is one connection end surface 35, and it faces the x direction x2 side. The connecting end surfaces 34 and 35 are formed by dicing in the cutting process in the manufacturing process.

The shape of the lead 3 is not limited to the one described above. For example, the back surface 32 extends to the edge of the semiconductor device A50 on the y-direction y2 side, the connection end surface 34 extends to the edge on the z-direction z1 side of the semiconductor device A50, and the back surface 32 and the connection end surface 34 are connected to form a continuous line. It may be exposed from the sealing resin 8 . The shape of the lead 3 is appropriately designed according to the application and specifications.

The semiconductor element 6 according to this embodiment is, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor). The semiconductor element 6 may be another transistor such as an IGBT (Insulated Gate Bipolar Transistor). The semiconductor element 6 further includes a third electrode 633 arranged on the element main surface 61 . In this embodiment, the first electrode 631 is the source electrode, the second electrode 632 is the drain electrode, and the third electrode 633 is the gate electrode. A second electrode 632 of the semiconductor element 6 is conductively connected to the lead 1 via a bonding material 79 . Thereby, the lead 1 is conductively connected to the second electrode 632 (drain electrode) of the semiconductor element 6 and functions as a drain terminal. A first electrode 631 of the semiconductor element 6 is conductively connected to the lead 2 via the wire 7 . As a result, the lead 2 is conductively connected to the first electrode 631 (source electrode) of the semiconductor element 6 and functions as a source terminal. A third electrode 633 of the semiconductor element 6 is conductively connected to the lead 3 via the wire 7 . As a result, the lead 3 is conductively connected to the third electrode 633 (gate electrode) of the semiconductor element 6 and functions as a gate terminal.

Also in this embodiment, the inner surface 131 of the lead 1 has a plurality of protrusions 16 and a plurality of recesses 17 . Compared to the case where the plurality of protrusions 16 and the plurality of recesses 17 are not provided, the contact area between the inner surface 131 and the sealing resin 8 is increased. Therefore, the adhesion of the sealing resin 8 to the inner surface 131 is improved. Thereby, the semiconductor device A50 can suppress peeling of the sealing resin 8 on the inner surface 131 . Moreover, the semiconductor device A50 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.

In this embodiment, the case where the lead 3 is arranged on the same side as the lead 2 with respect to the lead 1 in the y direction has been described, but the present invention is not limited to this. Lead 3 may be arranged on the opposite side of lead 1 to lead 2 in the y-direction.

In the first to fourth embodiments, an example in which the semiconductor element 6 is a diode was described, and in the fifth embodiment, an example in which the semiconductor element 6 is a transistor was described, but the present invention is not limited to this. The type of semiconductor element 6 is not particularly limited, and other semiconductor elements such as integrated circuits may be used. Also, in the above-described first to fifth embodiments, the case where two or three leads are arranged has been described, but the present invention is not limited to this. The number and arrangement of leads to be arranged are not particularly limited, and are appropriately set according to the number and arrangement of electrodes arranged on the element main surface 61 of the semiconductor element 6 .

The semiconductor device and the semiconductor device manufacturing method according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the method for manufacturing the semiconductor device of the present disclosure can be changed in design in various ways. The present disclosure includes embodiments described in the appendices below.

Appendix 1.
a semiconductor element (6);
a first lead (1) on which the semiconductor element is mounted;
a second lead (2) spaced apart from the first lead in a first direction perpendicular to the thickness direction of the first lead and conducting to the semiconductor element;
a sealing resin (8) covering the semiconductor element;
with
The first lead is
a first main surface (11) to which the semiconductor element is bonded;
a first rear surface (12) facing the side opposite to the first main surface in the thickness direction and exposed from the sealing resin;
a first inner surface (131) connected to the first back surface and covered with the sealing resin;
with
The first inner surface is
a first protrusion (161) protruding toward the side facing the first back surface;
A first concave portion arranged in a second direction orthogonal to the thickness direction and the first direction with respect to the first convex portion and concave on a side of the first convex portion facing the first main surface. (17) and
A semiconductor device comprising:
Appendix 2.
The first internal surface according to appendix 1, wherein the first inner surface is provided with a second convex portion (162) that protrudes toward the first back surface and is aligned in the second direction with respect to the first convex portion. semiconductor device.
Appendix 3.
According to appendix 2, the first inner surface has a third protrusion (163) that protrudes toward the first rear surface and is aligned in the first direction with respect to the first protrusion. semiconductor device.
Appendix 4.
The first inner surface protrudes toward the side facing the first back surface, and is between the first convex portion and the second convex portion in the second direction, and the first convex portion in the first direction 3. The semiconductor device of claim 3, further comprising a fourth protrusion (164) positioned between the third protrusion and the third protrusion.
Appendix 5.
The semiconductor device according to appendix 4, wherein the fourth protrusion is positioned on a line segment connecting a vertex of the second protrusion and a vertex of the third protrusion when viewed in the thickness direction.
Appendix 6.
The semiconductor device according to appendix 1, wherein the first protrusion and the first recess extend in the first direction.
Appendix 7.
7. The semiconductor device according to any one of appendices 1 to 6, wherein the first protrusion is not exposed from the sealing resin.
Appendix 8.
The first protrusion has a dimension (T2) in the thickness direction from the first main surface that is equal to a dimension (T1) in the thickness direction from the first main surface to the first rear surface of the first lead. 8. The semiconductor device according to any one of appendices 1 to 7, wherein 50% or more and 90% or less of ).
Appendix 8-1.
The dimension (T3) in the thickness direction from the bottom of the first recess to the top of the first protrusion is the dimension in the thickness direction from the first main surface to the first rear surface of the first lead. 9. The semiconductor device according to any one of Appendixes 1 to 8, wherein (T1) is 10% or more and 50% or less.
Appendix 9.
9. The semiconductor device according to any one of appendices 1 to 8, wherein the first protrusion and the first recess are arranged on the second lead side with respect to the first back surface in the first direction.
Appendix 10. (Third Embodiment, FIG. 21)
The first inner surface protrudes toward the first rear surface and is located on the opposite side of the first rear surface to the second lead in the first direction. The semiconductor device according to Appendix 9, comprising:
Appendix 11. (Second embodiment, FIG. 20)
9. The semiconductor according to any one of appendices 1 to 8, wherein the first convex portion and the first concave portion are arranged on a side opposite to the second lead with respect to the first back surface in the first direction. Device.
Appendix 12. (Fourth embodiment, FIG. 22)
The second lead is
a second main surface (21) facing the same side as the first main surface;
a second back surface (22) facing the same side as the first back surface and exposed from the sealing resin;
A second inner surface (23) connected to the second back surface and covered with the sealing resin,
12. The semiconductor device according to any one of appendices 1 to 11, wherein the second inner surface has a sixth projection (16) projecting toward the second back surface.
Appendix 12-1.
13. The semiconductor device according to any one of Appendixes 1 to 12, wherein the semiconductor element is a diode.
Appendix 13. (Fifth embodiment, FIG. 23)
13. The semiconductor device according to any one of appendices 1 to 12, further comprising a third lead (3) spaced apart from said first lead and said second lead and conducting to said semiconductor element.
Appendix 13-1.
14. The semiconductor device according to appendix 13, wherein the third lead is arranged on the same side as the second lead with respect to the first lead in the first direction.
Appendix 13-2.
14. The semiconductor device according to appendix 13, wherein the semiconductor element is a transistor.
Appendix 14.
A method of manufacturing a semiconductor device including a first lead having a first main surface and a first back surface facing opposite sides in a thickness direction, the method comprising:
a step of preparing a metal plate having a main surface and a back surface facing opposite to each other in the thickness direction (S11);
forming a first mask for forming the first back surface and a second mask in which a plurality of rectangular masks are arranged in a checkered pattern on the back surface of the metal plate (S12);
a step (S13) of creating a lead frame by etching the metal plate from the main surface side and the back surface side;
a step of bonding a semiconductor element to the lead frame (S20);
forming a sealing resin covering the semiconductor element (S40);
a step of cutting the lead frame and the sealing resin (S50);
A method of manufacturing a semiconductor device, comprising:
Appendix 15.
In the second mask, the rectangular masks are arranged in three or more rows in a first direction orthogonal to the thickness direction and in a second direction orthogonal to the thickness direction and the first direction. 15. The method of manufacturing a semiconductor device according to appendix 14, wherein

A10 to A15, A20, A30, A40, A50: Semiconductor device 1: Lead 11: Main surface 12: Back

surface

13, 131 to 134: Internal surface 14: Connection end surface 15:

Connection end surface

16, 161 to 164: Convex portion 17: Recess 2: Lead 21: Main surface 22: Back surface 23: Internal surface 231: Internal surface 24: Connection end surface 25: Connection end surface 3: Lead 31: Main surface 32: Back surface 33: Internal surface 34: Connection end surface 35: Connection end surface 6 : Semiconductor element 60: Element body 61: Element principal surface 62: Element back surface 631: First electrode 632: Second electrode 633: Third electrode 7: Wire 79: Bonding material 8: Sealing resin 81: Resin principal surface 82: Resin back surface 83, 831 to 834: Resin side surface 91: Metal plate 911: Main surface 912: Back surface
92, 921, 922, 923: Mask 924: Opening 925: Mask 95: Lead frame 951: Main surface 952: Back surface 953: Internal surface 96: Sealing resin 962: Back surface

Claims

a semiconductor element;
a first lead on which the semiconductor element is mounted;
a second lead spaced apart from the first lead in a first direction perpendicular to the thickness direction of the first lead and conducting to the semiconductor element;
a sealing resin covering the semiconductor element;
with
The first lead is
a first main surface to which the semiconductor element is bonded;
a first rear surface facing the side opposite to the first main surface in the thickness direction and exposed from the sealing resin;
a first inner surface connected to the first back surface and covered with the sealing resin;
with
The first inner surface is
a first convex portion protruding toward the side facing the first back surface;
A first concave portion arranged in a second direction orthogonal to the thickness direction and the first direction with respect to the first convex portion and concave on a side of the first convex portion facing the first main surface. When,
A semiconductor device comprising:
2. The semiconductor device according to claim 1, wherein said first inner surface has a second protrusion projecting toward said first back surface and arranged in said second direction with respect to said first protrusion. .
3. The semiconductor device according to claim 2, wherein said first inner surface has a third protrusion projecting toward said first back surface and arranged in said first direction with respect to said first protrusion. .
The first inner surface protrudes toward the side facing the first back surface, and is between the first convex portion and the second convex portion in the second direction, and the first convex portion in the first direction 4. The semiconductor device according to claim 3, further comprising a fourth protrusion positioned between said third protrusion.
5. The semiconductor device according to claim 4, wherein said fourth protrusion is positioned on a line segment connecting a vertex of said second protrusion and a vertex of said third protrusion when viewed in said thickness direction.
The semiconductor device according to claim 1, wherein said first protrusion and said first recess extend in said first direction.
The semiconductor device according to any one of claims 1 to 6, wherein said first convex portion is not exposed from said sealing resin.
The first protrusion has a dimension in the thickness direction from the first main surface that is 50% or more of a dimension in the thickness direction from the first main surface to the first rear surface of the first lead. % or less, the semiconductor device according to claim 1 .
9. The semiconductor device according to claim 1, wherein said first protrusion and said first recess are arranged on said second lead side with respect to said first back surface in said first direction.
The first inner surface has a fifth protrusion projecting toward the first back surface and positioned on the opposite side of the first back surface to the second lead in the first direction. 10. The semiconductor device according to claim 9, wherein
9. The first convex portion and the first concave portion according to claim 1, wherein the first convex portion and the first concave portion are arranged on a side opposite to the second lead with respect to the first back surface in the first direction. semiconductor device.
The second lead is
a second main surface facing the same side as the first main surface;
a second back surface facing the same side as the first back surface and exposed from the sealing resin;
a second inner surface connected to the second back surface and covered with the sealing resin;
with
12. The semiconductor device according to any one of claims 1 to 11, wherein said second inner surface has a sixth protrusion projecting toward said second back surface.
13. The semiconductor device according to claim 1, further comprising a third lead spaced apart from said first lead and said second lead and conducting to said semiconductor element.
A method of manufacturing a semiconductor device including a first lead having a first main surface and a first back surface facing opposite sides in a thickness direction, the method comprising:
preparing a metal plate having a main surface and a back surface facing opposite to each other in the thickness direction;
forming a first mask for forming the first back surface and a second mask in which a plurality of rectangular masks are arranged in a checkered pattern on the back surface of the metal plate;
a step of etching the metal plate from the main surface side and the back surface side to create a lead frame;
bonding a semiconductor element to the lead frame;
forming a sealing resin covering the semiconductor element;
cutting the lead frame and the sealing resin;
A method of manufacturing a semiconductor device, comprising:
In the second mask, the rectangular masks are arranged in three or more rows in a first direction orthogonal to the thickness direction and in a second direction orthogonal to the thickness direction and the first direction. 15. The method of manufacturing a semiconductor device according to claim 14, wherein