JPH11191562A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11191562A JPH11191562A JP9359750A JP35975097A JPH11191562A JP H11191562 A JPH11191562 A JP H11191562A JP 9359750 A JP9359750 A JP 9359750A JP 35975097 A JP35975097 A JP 35975097A JP H11191562 A JPH11191562 A JP H11191562A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- island
- resin
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に、実装面積を縮小して実装効率を向上できる半導体
装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device capable of improving a mounting efficiency by reducing a mounting area.
【０００２】[0002]
【従来の技術】ＩＣ、ディスクリート素子等の半導体素
子を製造する際には、図１０（Ａ）に示すような封止技
術が主に用いられる。即ち、半導体チップ１をアイラン
ド２上に実装（ダイボンド）し、半導体チップ１の周辺
に配置したリード端子３とトランジスタ素子のベース電
極、エミッタ電極とをそれぞれボンディングワイヤー４
で電気的に接続（ワイヤボンド）し、半導体チップ１を
エポキシ樹脂等の熱硬化型樹脂４によるトランスファー
モールドによって、半導体チップ１とリード端子３の一
部を完全に被覆保護したものである。樹脂５の外部に導
出されたリード端子３はＺ字型に折り曲げられて表面実
装用途に適したものとしてある。2. Description of the Related Art When manufacturing semiconductor elements such as ICs and discrete elements, a sealing technique as shown in FIG. 10A is mainly used. That is, the semiconductor chip 1 is mounted (die-bonded) on the island 2, and the lead terminals 3 arranged around the semiconductor chip 1 and the base electrode and the emitter electrode of the transistor element are respectively bonded to the bonding wires 4.
The semiconductor chip 1 and the lead terminals 3 are completely covered and protected by transfer molding of the semiconductor chip 1 with a thermosetting resin 4 such as an epoxy resin. The lead terminal 3 led out of the resin 5 is bent in a Z-shape and is suitable for surface mounting applications.
【０００３】例えばＮＰＮ型トランジスタ素子を形成し
た半導体チップ１を封止した場合は、アイランド２をコ
レクタ電極として３端子構造の半導体装置が提供され
る。尚、６は半導体チップ１を固着するための半田など
の接着剤である。上記の半導体装置の製造工程にあって
は、アイランド２とリード端子３は、銅素材または鉄素
材からなるフープ状あるいは短冊状のリードフレームの
状態で供給され、該リードフレームには例えば半導体装
置２０個分のアイランド２とリード端子３が形成されて
いる。For example, when a semiconductor chip 1 on which an NPN transistor element is formed is sealed, a semiconductor device having a three-terminal structure using an island 2 as a collector electrode is provided. Reference numeral 6 denotes an adhesive such as solder for fixing the semiconductor chip 1. In the above-described semiconductor device manufacturing process, the island 2 and the lead terminals 3 are supplied in the form of a hoop-shaped or strip-shaped lead frame made of a copper material or an iron material. Individual islands 2 and lead terminals 3 are formed.
【０００４】また、上記の製造工程のトランスファーモ
ールドにあっては、図１０（Ｂ）を参照して、上金型７
及び下金型８によって個々の半導体装置の外形形状に合
致した空間であるキャビティ９を構成し、該キャビティ
の内部にダイボンド及びワイヤボンドを施したリードフ
レームを設置し、この状態でキャビティ９内に樹脂を注
入することによりトランスファーモールドが行われる。
更に、樹脂封止した後に前記リードフレームからリード
部分他を切断することで半導体装置を個々の素子に分離
している。[0004] In the transfer mold of the above-described manufacturing process, referring to FIG.
And the lower mold 8 forms a cavity 9 which is a space conforming to the outer shape of each semiconductor device, and a lead frame on which die bonding and wire bonding are performed is installed inside the cavity. Transfer molding is performed by injecting a resin.
Further, the semiconductor device is separated into individual elements by cutting the lead portions and the like from the lead frame after resin sealing.
【０００５】[0005]
【発明が解決しようとする課題】第１の課題：樹脂モー
ルドされた半導体装置は、通常、ガラスエポキシ基板等
のプリント基板に実装され、同じくプリント基板上に実
装された他の素子と電気的に接続することにより、所望
の回路網を構成する。この時、リード端子３が樹脂５の
外部に導出された半導体装置では、リード端子３の先端
から先端までの距離１０を実装面積として占有するの
で、実装面積が大きいという欠点がある。A first problem is that a resin-molded semiconductor device is usually mounted on a printed board such as a glass epoxy board, and is electrically connected to other elements also mounted on the printed board. The connection forms a desired circuit network. At this time, the semiconductor device in which the lead terminals 3 are led out of the resin 5 has a disadvantage that the mounting area is large because the distance 10 from the tip of the lead terminal 3 to the tip is occupied as the mounting area.
【０００６】第２の課題：金型内に設置したときのリー
ドフレームとキャビティ９との位置合わせ精度はプラス
・マイナス５０μ程度が限界である。このため、アイラ
ンド２の大きさは前記合わせ精度を考慮した大きさに設
計しなければならない。従って、合わせ精度の問題は、
パッケージの外形寸法に対するアイランド２の寸法を小
さくし、これがパッケージの外形寸法に対して収納可能
な半導体チップ１の最大寸法に制限を与えていた。Second problem: The positioning accuracy between the lead frame and the cavity 9 when installed in a mold is limited to about ± 50 μm. Therefore, the size of the island 2 must be designed in consideration of the alignment accuracy. Therefore, the problem of alignment accuracy is
The size of the island 2 with respect to the external dimensions of the package is reduced, and this limits the maximum size of the semiconductor chip 1 that can be accommodated with respect to the external dimensions of the package.
【０００７】第３の課題：樹脂５の外形寸法を極限まで
縮小すると、樹脂５内部に埋設されるリード端子３と樹
脂５との密着面積が小さくなる。これによってリード端
子３が抜け易くなるので、パッケージサイズを増大させ
ない、何らかの抜け防止策が必要であった。Third problem: When the outer dimensions of the resin 5 are reduced to the limit, the contact area between the lead terminals 3 embedded in the resin 5 and the resin 5 decreases. This makes it easier for the lead terminals 3 to come off. Therefore, some measures for preventing the lead-out from occurring are required without increasing the package size.
【０００８】[0008]
【課題を解決するための手段】本発明は、半導体チップ
を固着する為のアイランドと、前記アイランドに先端を
近接する複数本の外部接続用リード端子と、前記半導体
チップの電極パッドと前記外部接続リードとを接続する
ボンディングワイヤと、前記半導体チップを含めて全体
を封止する樹脂とを具備し、前記リード端子の先端部が
前記樹脂の表面で終端すると共に、前記リード端子の先
端部が先細りの形状を具備するように形成したものであ
る。According to the present invention, there is provided an island for fixing a semiconductor chip, a plurality of external connection lead terminals adjacent to the island, and an electrode pad of the semiconductor chip and the external connection. A bonding wire for connecting a lead, and a resin for sealing the entirety including the semiconductor chip. The tip of the lead terminal terminates on the surface of the resin, and the tip of the lead terminal is tapered. Is formed so as to have the following shape.
【０００９】[0009]
【発明の実施の形態】以下に本発明の製造方法を詳細に
説明する。 第１工程：（図１） 先ず、リードフレーム３０を準備する。図１（Ａ）はリ
ードフレーム３０の平面図であり、図１（Ｂ）は図１
（Ａ）のＡＡ断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The production method of the present invention will be described below in detail. First step: (FIG. 1) First, a lead frame 30 is prepared. FIG. 1A is a plan view of the lead frame 30, and FIG.
It is an AA sectional view of (A).
【００１０】本発明で用いられるリードフレーム３０
は、半導体チップを搭載するための多数の素子搭載部３
１、３１Ａ．．．．が行・列方向（又はそれらの一方方
向にのみ）に複数個繰り返しパターンで配置されてお
り、該多数個の素子搭載部３１は、それらの周囲を取り
囲む様に配置した枠体部３２によって保持されている。
素子搭載部３１は、半導体チップを固着するアイランド
３３と、外部接続用電極となる複数のリード端子３４を
少なくとも具備する。アイランド３３は連結バー３５に
よって互いに連結され、同じく連結バー３５によって枠
体部３２に連結されている。リード端子３４はアイラン
ド３３に連結されている。この時、特定のアイランド３
３に対しては、その隣に隣接するアイランド３３Ａに連
結保持されたリード端子３４が対応して１つの素子搭載
部３１を構成する。アイランド３３Ａとリード端子３４
との連結部分近傍のリード端子３４には、その切断予定
箇所にＶ字型の凹部３６を形成している。凹部３６はリ
ード端子３４の両側辺に設けてあり、その線幅が最も細
くなる箇所と切断予定中心線が合致している。この様に
素子搭載部３１を行・列方向に複数配置することで、１
本の短冊状のリードフレーム３０に例えば１００個の素
子搭載部３１を配置する。[0010] Lead frame 30 used in the present invention
Are a large number of element mounting portions 3 for mounting a semiconductor chip.
1, 31A. . . . Are arranged in a row and column direction (or only in one of the directions) in a repetitive pattern, and the multiple element mounting portions 31 are held by a frame portion 32 arranged so as to surround the periphery thereof. Have been.
The element mounting portion 31 includes at least an island 33 for fixing a semiconductor chip and a plurality of lead terminals 34 serving as external connection electrodes. The islands 33 are connected to each other by a connection bar 35, and are also connected to the frame 32 by the connection bar 35. The lead terminal 34 is connected to the island 33. At this time, a specific island 3
In the case of No. 3, the lead terminal 34 connected and held to the adjacent island 33A constitutes one element mounting part 31 correspondingly. Island 33A and lead terminal 34
A V-shaped concave portion 36 is formed in the lead terminal 34 in the vicinity of the connection portion with the portion to be cut. The concave portions 36 are provided on both sides of the lead terminal 34, and the portion where the line width becomes narrowest coincides with the center line to be cut. By arranging a plurality of element mounting sections 31 in the row and column directions in this manner,
For example, 100 element mounting portions 31 are arranged on a strip-shaped lead frame 30.
【００１１】素子搭載部３１群を取り囲む枠体部３２に
は、複数個の合わせマーク３７を形成する。合わせマー
ク３７は、貫通孔またはスタンピングによって部分的に
凹ませたもの等、製造工程における自動認識機能が働く
ものであればよい。また、形状も正方形、長方形、矩
形、円形等があげられる。そして、素子搭載部３１毎に
１個、または複数個毎に１個等間隔で配置する。A plurality of alignment marks 37 are formed on the frame 32 surrounding the group of element mounting portions 31. The alignment mark 37 may be any as long as it has an automatic recognition function in the manufacturing process, such as a through-hole or a mark partially recessed by stamping. Further, the shape may be a square, a rectangle, a rectangle, a circle, or the like. Then, one device is provided for each element mounting portion 31 or one device is provided for each device at equal intervals.
【００１２】上記のリードフレーム３０は、例えば、約
０．２ｍｍ厚の銅系の金属材料で形成された帯状あるい
は矩形状のリードフレーム用金属薄板を用意し、このリ
ードフレーム用金属薄板をエッチング加工またはスタン
ピング加工によって図示したパターンに開口することに
より得ることができる。尚、リードフレーム３０の板厚
は必要に応じて適宜に設定することができる。For the lead frame 30, for example, a strip-shaped or rectangular-shaped thin metal plate for a lead frame made of a copper-based metal material having a thickness of about 0.2 mm is prepared, and this thin metal plate for a lead frame is etched. Alternatively, it can be obtained by opening the pattern shown in the figure by stamping. The thickness of the lead frame 30 can be appropriately set as needed.
【００１３】第２工程：（図２） 次に、リードフレーム３０に対してダイボンド工程とワ
イヤボンド工程を行う。図２（Ｂ）は図２（Ａ）のＡＡ
線断面図である。各アイランド３３、３３Ａの一主面上
にＡｇペースト、半田等の導電ペースト３８を塗布し、
その導電ペースト３８を介して各アイランド３３、３３
Ａ上に半導体チップ３９を固着する。各アイランド表面
に金メッキを行い、そのメッキ上に半導体チップを共晶
接続することも可能である。Second Step: (FIG. 2) Next, a die bonding step and a wire bonding step are performed on the lead frame 30. FIG. 2B is an AA of FIG.
It is a line sectional view. A conductive paste 38 such as Ag paste or solder is applied on one main surface of each of the islands 33 and 33A,
Each of the islands 33, 33 via the conductive paste 38
A semiconductor chip 39 is fixed on A. Gold plating can be performed on the surface of each island, and a semiconductor chip can be eutectic-connected on the plating.
【００１４】更に、半導体チップ３９の表面に形成され
たボンディングパッドと、これに対応するリード端子３
４とをワイヤ４０でワイヤボンディングする。ワイヤ４
０は例えば直径が２０μの金線から成る。ここで、ワイ
ヤ４０は各アイランド３３上に固着した半導体チップ３
９の表面電極と、その隣に隣接した他のアイランド３３
Ａから延在するリード端子３４とを接続する。半導体チ
ップ３９が固着されたアイランド３３の裏面は、係る半
導体チップ３９の外部接続用の電極として用いることが
できる。アイランド３３の裏面を接続用端子の１つとし
て用いる形態は、半導体チップ３９として例えばトラン
ジスタ、パワーＭＯＳＦＥＴ等の、電流経路が垂直方向
になる半導体デバイス素子に適している。Further, the bonding pads formed on the surface of the semiconductor chip 39 and the corresponding lead terminals 3
4 is wire-bonded with a wire 40. Wire 4
0 is a gold wire having a diameter of, for example, 20 μ. Here, the wires 40 are connected to the semiconductor chips 3 fixed on the respective islands 33.
9 and another island 33 adjacent to it.
A is connected to a lead terminal 34 extending from A. The back surface of the island 33 to which the semiconductor chip 39 is fixed can be used as an electrode for external connection of the semiconductor chip 39. The mode in which the back surface of the island 33 is used as one of the connection terminals is suitable as a semiconductor chip 39 such as a transistor or a power MOSFET, for example, a semiconductor device element having a vertical current path.
【００１５】半導体チップ３９を固着するために塗布し
た導電性ペースト３８は、図２（Ａ）から明らかなよう
に、半導体チップ３９が固着されるアイランド３３上に
選択的に塗布形成する。リード端子３４上に導電性ペー
スト３８が付着すると、ワイヤボンディングを行う場合
に、ボンディング装置のキャピラリーの先端部分に導電
性ペーストがつまりボンディング不良が生じ生産性が低
下する恐れがあるためである。この様な問題がない場合
には、導電性ペーストを素子搭載部３１全面に塗布して
も良い。The conductive paste 38 applied for fixing the semiconductor chip 39 is selectively applied on the island 33 to which the semiconductor chip 39 is fixed, as is apparent from FIG. 2A. This is because, when the conductive paste 38 adheres to the lead terminals 34, when performing wire bonding, the conductive paste may be clogged at the tip end of the capillary of the bonding apparatus, which may result in poor bonding and lower productivity. If there is no such problem, a conductive paste may be applied to the entire surface of the element mounting portion 31.
【００１６】第３工程：（図３） 次に、全体を樹脂モールドする。図３（Ｂ）は図３
（Ａ）のＡＡ線断面図である。リードフレーム３０上に
エポキシ樹脂等の熱硬化性の封止用樹脂層４１を形成
し、各素子搭載部３１、３１Ａ．．、半導体チップ３９
及びワイヤ４０を封止保護する。樹脂４１は、各半導体
チップ３９．．．を個別にパッケージングするものでは
なく、全ての半導体チップ３９を共通に被うように形成
する。また、リードフレーム３０の裏面側にも０．０５
ｍｍ程度の厚みで樹脂４１を被着する。これで、アイラ
ンド３３とリード端子３４は完全に樹脂４１内部に埋設
されることになる。Third step: (FIG. 3) Next, the whole is resin-molded. FIG.
FIG. 3A is a sectional view taken along line AA of FIG. A thermosetting sealing resin layer 41 such as an epoxy resin is formed on the lead frame 30, and each of the element mounting portions 31, 31A. . , Semiconductor chip 39
And the wire 40 is sealed and protected. The resin 41 is used for each semiconductor chip 39. . . Are not individually packaged, but are formed so as to cover all the semiconductor chips 39 in common. Also, 0.05 on the back side of the lead frame 30.
The resin 41 is applied with a thickness of about mm. Thus, the island 33 and the lead terminal 34 are completely embedded in the resin 41.
【００１７】この樹脂層４１は、射出成形用の上下金型
が形成する空間（キャビティ）内にリードフレーム３０
を設置し、該空間内にエポキシ樹脂を充填、成形する事
によって形成する。あるいは、枠体３２に高さ数ｍｍ、
幅数ｍｍの環状のダムを形成しておき、該ダムで囲まれ
た領域を満たすように液状の樹脂を充填し、これを熱処
理で硬化したものであっても良い。The resin layer 41 is provided in the space (cavity) formed by the upper and lower molds for injection molding.
Is formed, and the space is filled with an epoxy resin and molded. Alternatively, the frame 32 has a height of several mm,
An annular dam having a width of several mm may be formed, a liquid resin may be filled so as to fill a region surrounded by the dam, and the resin may be cured by heat treatment.
【００１８】第４工程：（図４） 次に、リードフレーム３０の裏面側の樹脂４１を部分的
に除去してスリット孔４２を形成する。図４（Ｂ）は図
４（Ａ）のＡＡ線断面図である。スリット孔４１は、後
で外部接続端子を構成する為に形成するものである。約
０．５ｍｍの幅を有し、ダイシング装置のブレードによ
って樹脂４２を切削することにより形成した。前記ブレ
ードには様々な板厚のものが準備されており、用いるブ
レードの板厚に応じて、１回であるいは複数回繰り返す
ことで所望の幅に形成する。この時、樹脂４１を切削す
ると同時にリード端子３４の裏面側も約０．１ｍｍ程切
削して、リードフレーム３０の金属表面を露出させる。
このスリット孔４２は、各リード端子３４にくさび状に
形成した「凹部３６」の付近に形成する。そして、スリ
ット孔４２の内部に露出したリード端子３４の表面に半
田メッキ等のメッキ層４３を形成する。このメッキ層４
３は、リードフレーム３０を電極の一方とする電解メッ
キ法により行われる。Fourth Step: (FIG. 4) Next, the slit 41 is formed by partially removing the resin 41 on the back surface of the lead frame 30. FIG. 4B is a cross-sectional view taken along the line AA of FIG. The slit hole 41 is formed to form an external connection terminal later. It had a width of about 0.5 mm and was formed by cutting the resin 42 with a blade of a dicing device. The blade is prepared in various thicknesses, and the blade is formed once or a plurality of times according to the thickness of the blade to be formed into a desired width. At this time, at the same time as the resin 41 is cut, the back surface of the lead terminal 34 is also cut by about 0.1 mm to expose the metal surface of the lead frame 30.
The slit hole 42 is formed in the vicinity of the “recess 36” formed in a wedge shape in each lead terminal 34. Then, a plating layer 43 such as solder plating is formed on the surface of the lead terminal 34 exposed inside the slit hole 42. This plating layer 4
Step 3 is performed by an electrolytic plating method using the lead frame 30 as one of the electrodes.
【００１９】第５工程：（図５） 次に、素子搭載部３１毎に樹脂層４１を切断して各々の
素子Ａ、素子Ｂ、素子Ｃ．．．．を分離する。即ち、ア
イランド３３とこの上に固着された半導体チップ３９に
接続されたリード端子３４を囲む領域（同図の切断ライ
ン４４）で切断することにより、素子搭載部３１毎に分
割した半導体装置を形成する。切断にはダイシング装置
が用いられ、ダイシング装置のブレードによって樹脂層
４１とリードフレーム３０とを同時に切断する。スリッ
ト孔４２が位置する箇所では、少なくともスリット孔４
２の側壁に付着したメッキ層４３を残すように形成す
る。この様に残存させたメッキ層４３は、半導体装置を
プリント基板上に実装する際に利用される。また、切断
したリード端子３４の他方はアイランド３３に連続する
突起部３３ａとして残存し、切断した連結バー３５はア
イランド３３に連続する突起部３３ｂとして残存する。
切断されたリード端子３４及び突起部３３ａ、３３ｂの
切断面は、樹脂層４１の切断面と同一平面を形成し、該
同一平面に露出する。ダイシング工程においては裏面側
（スリット孔４２を設けた側）にブルーシート（たとえ
ば、商品名：ＵＶシート、リンテック株式会社製）を貼
り付け、前記ダイシングブレードがブルーシートの表面
に到達するような切削深さで切断する。更に、ダイシン
グブレードの板厚はスリット孔４２の幅よりも薄い（例
えば、幅０．１ｍｍ）ものを用い、スリット孔４２の中
心線に沿って、ダイシングブレードがリード端子３３の
凹部３６の中心線上を通過するようにダイシングした。
これで、切断後のリード端子３３の先端部が先細りの形
状となり、樹脂４１から容易には抜け落ちない形状に加
工できる。Fifth Step: (FIG. 5) Next, the resin layer 41 is cut for each of the element mounting portions 31 so that each of the elements A, B, C. . . . Is separated. That is, a semiconductor device divided for each element mounting portion 31 is formed by cutting the island 33 and the region surrounding the lead terminal 34 connected to the semiconductor chip 39 fixed thereon (the cutting line 44 in the same figure). I do. A dicing device is used for the cutting, and the resin layer 41 and the lead frame 30 are simultaneously cut by a blade of the dicing device. At the position where the slit hole 42 is located, at least the slit hole 4
2 is formed so as to leave the plating layer 43 attached to the side wall. The remaining plating layer 43 is used when mounting the semiconductor device on a printed circuit board. Further, the other one of the cut lead terminals 34 remains as a protrusion 33 a continuous to the island 33, and the cut connection bar 35 remains as a protrusion 33 b continuous to the island 33.
The cut surfaces of the cut lead terminals 34 and the protrusions 33a and 33b form the same plane as the cut surface of the resin layer 41, and are exposed on the same plane. In the dicing step, a blue sheet (for example, trade name: UV sheet, manufactured by Lintec Co., Ltd.) is attached to the back side (the side provided with the slit holes 42), and cutting is performed so that the dicing blade reaches the surface of the blue sheet Cut at depth. Further, the plate thickness of the dicing blade is smaller than the width of the slit hole 42 (for example, 0.1 mm in width). Dicing was performed to pass through.
Thus, the tip of the lead terminal 33 after cutting has a tapered shape, and can be processed into a shape that does not easily fall off the resin 41.
【００２０】図６は斯かる製造方法によって形成した完
成後の半導体装置を裏面側からみたときの斜視図であ
る。半導体チップ３９とボンディングワイヤ４０を含め
て、アイランド３３とリード端子３４が樹脂４１でモー
ルドされて、大略直方体のパッケージ形状を形成する。
樹脂４１は熱硬化性エポキシ樹脂である。アイランド３
３とリード端子３４は、厚さが約０．２ｍｍの銅系の金
属材料から成る。樹脂４１の外形寸法は、縦×横×高さ
が、約０．７ｍｍ×１．０ｍｍ×０．６ｍｍである。FIG. 6 is a perspective view of the completed semiconductor device formed by such a manufacturing method as viewed from the back side. The island 33 and the lead terminals 34, including the semiconductor chip 39 and the bonding wires 40, are molded with the resin 41 to form a substantially rectangular parallelepiped package shape.
The resin 41 is a thermosetting epoxy resin. Island 3
The lead 3 and the lead terminal 34 are made of a copper-based metal material having a thickness of about 0.2 mm. The external dimensions of the resin 41 are about 0.7 mm × 1.0 mm × 0.6 mm in length × width × height.
【００２１】直方体のパッケージ外形を形成する６面の
うち、少なくとも側面４１ａ、４１ｂ、４１ｃ、４１ｄ
は樹脂４１を切断した（第５工程参照）切断面で構成さ
れる。該切断面に沿ってリード端子３４の切断面が露出
する。アイランド３３には切断されたリード端子３４の
名残である突起部３３ａと連結部３５の名残である突起
部３３ｂを有し、これらの突起部３３ａ、３３ｂの切断
面も露出する。At least the side surfaces 41a, 41b, 41c and 41d among the six surfaces forming the package shape of the rectangular parallelepiped
Is constituted by a cut surface obtained by cutting the resin 41 (see the fifth step). The cut surface of the lead terminal 34 is exposed along the cut surface. The island 33 has a protruding portion 33a remaining on the cut lead terminal 34 and a protruding portion 33b remaining on the connecting portion 35, and the cut surfaces of these protruding portions 33a and 33b are also exposed.
【００２２】側面４１ｂ、４１ｄの裏面側には第４工程
で形成したスリット孔４２の名残である段差部４５を有
し、該段差部４５の表面にアイランド３３の突出部３３
ａの裏面側と、リード端子３４の裏面側の一部が露出す
る。アイランド３３とリード端子３４の露出した表面に
は半田メッキなどの金属メッキ層４３が形成される。リ
ード端子３４の露出部分とアイランド３３の露出部との
間は、樹脂４１で被覆される。On the back side of the side surfaces 41b and 41d, there is provided a step portion 45 which is a remnant of the slit hole 42 formed in the fourth step.
The back surface side of a and a part of the back surface side of the lead terminal 34 are exposed. A metal plating layer 43 such as solder plating is formed on the exposed surfaces of the island 33 and the lead terminals 34. The space between the exposed portion of the lead terminal 34 and the exposed portion of the island 33 is covered with the resin 41.
【００２３】リード端子３４の先端部と、アイランドの
突出部３３ａの先端部は、凹部３６の中心線で切断した
ことにより先細りの形状に加工される。つまり、樹脂４
１の切断面４１ｂ、４１ｄ表面に露出する部分のリード
端子３４の線幅は樹脂４１内部のアイランド３３近傍で
の線幅よりも細い。この様に加工されることで、リード
端子３４が樹脂４１からは引き抜けない状態になってい
る。The leading end of the lead terminal 34 and the leading end of the island projection 33a are cut into a tapered shape by cutting along the center line of the recess 36. That is, resin 4
The line width of the lead terminal 34 at the portion exposed on the surface of the cut surface 41b, 41d is smaller than the line width near the island 33 inside the resin 41. By being processed in this manner, the lead terminals 34 are not pulled out of the resin 41.
【００２４】この装置をプリント基板上に実装した状態
を図７に示す。実装基板２４上に形成した素子間接続用
のプリント配線２５に対して段差部４５に露出したリー
ド端子３４アイランド３３の突起部３３ａを位置合わせ
し、半田２６等によって両者を接続する。この時、上記
の第５工程で形成した金属メッキ層４３が半田の塗れ性
を良好にする。FIG. 7 shows a state in which this device is mounted on a printed circuit board. The protrusion 33a of the lead terminal 34 island 33 exposed at the step 45 is aligned with the printed wiring 25 for element connection formed on the mounting board 24, and the two are connected by solder 26 or the like. At this time, the metal plating layer 43 formed in the fifth step improves the wettability of the solder.
【００２５】以上の方法によって製造された半導体装置
は、以下のメリットを有する。本発明の製造方法によっ
て製造した半導体装置は、金属製リード端子がパッケー
ジから突出しないので、実装面積を半導体装置の大きさ
と同じ程度の大きさにすることができる。従って、半導
体装置の実装面積に対する能動部分（半導体チップ３９
のチップサイズを意味する）の比である実装有効面積
を、図１０に示したものに比べて大幅に向上できる。こ
れにより、実装基板上に実装したときの実装面積のデッ
ドスペースを小さくすることができ、実装基板の小型化
に寄与することができる。The semiconductor device manufactured by the above method has the following advantages. In the semiconductor device manufactured by the manufacturing method of the present invention, since the metal lead terminals do not protrude from the package, the mounting area can be made as large as the size of the semiconductor device. Therefore, the active portion (the semiconductor chip 39) with respect to the mounting area of the semiconductor device
(Which means the chip size) can be greatly improved as compared with that shown in FIG. Thereby, the dead space of the mounting area when mounted on the mounting board can be reduced, which can contribute to the miniaturization of the mounting board.
【００２６】分割された半導体装置の各外部接続用電極
の表面にはメッキ層４３が形成されているので、実装基
板上に半田固着した際に該半田が切断面の上部まで（ス
リット孔４２の側壁に相当する部分）容易に盛り上がっ
て半田フィレットを形成する。従って半田接合力が向上
し熱ストレス等の応力による劣化を防止することができ
る。Since the plating layer 43 is formed on the surface of each external connection electrode of the divided semiconductor device, when the solder is fixed on the mounting board, the solder reaches the upper portion of the cut surface (the slit hole 42). (Part corresponding to side wall) Easily rises to form a solder fillet. Therefore, the solder bonding force is improved, and deterioration due to stress such as thermal stress can be prevented.
【００２７】この装置の外部接続端子は、段差部４５に
露出し、段差部４５と段差部４５との間の領域は樹脂４
１によって被覆されるので露出しない。従って実装基板
２４上に実装した際に半田２６と半田２６との距離を比
較的大きく設計でき、半田ブリッジによる外部接続端子
間の短絡事故を防止できる。多数個の素子をまとめてパ
ッケージングするので、個々にパッケージングする場合
に比べて無駄にする材料を少なくでき。材料費の低減に
つながるパッケージの外形をダイシング装置のブレード
で切断することにより構成したので、リードフレーム３
０のパターンに対する樹脂４１外形の位置あわせ精度を
向上できる。即ち、トランスファーモールド技術による
モールド金型とリードフレーム３０との合わせ精度がプ
ラス・マイナス５０μ程度であるのに対して、ダイシン
グ装置によるダイシングブレードとリードフレーム３０
との合わせ精度はプラス・マイナス１０μ程度に小さく
できる。合わせ精度を小さくできることは、アイランド
３３の面積を増大して、搭載可能な半導体チップ３９の
チップ面積を増大できることを意味し、これも上記有効
実装面積効率を向上させる。The external connection terminal of this device is exposed at the step 45, and the area between the steps 45
No exposure because it is covered by 1. Accordingly, the distance between the solders 26 when mounted on the mounting board 24 can be designed to be relatively large, and a short circuit accident between the external connection terminals due to the solder bridge can be prevented. Since a large number of elements are packaged collectively, wasteful materials can be reduced as compared with the case of individually packaging. Since the outer shape of the package, which leads to a reduction in material costs, is cut by a blade of a dicing device, the lead frame 3
The alignment accuracy of the outer shape of the resin 41 with respect to the 0 pattern can be improved. That is, while the alignment accuracy between the mold and the lead frame 30 by the transfer molding technique is approximately ± 50 μm, the dicing blade and the lead frame 30 by the dicing device are used.
Can be reduced to about ± 10 μm. Reducing the alignment precision means that the area of the island 33 can be increased and the chip area of the mountable semiconductor chip 39 can be increased, which also improves the effective mounting area efficiency.
【００２８】分割された半導体装置のリード端子３４の
終端は、図６に示すように、樹脂４１表面付近で先細り
の形状に形成されるために、リード端子３４が樹脂層４
１の側面から抜け落ちることを防止している。凹部３６
の形状はＶ字型の他にも、図８に示したようにコの字型
に凹ませた形状でも良い。コの字型の凹部３６によって
形成した装置の斜視図を図９に示した。同じ箇所に同じ
符号を付して説明を省略する。As shown in FIG. 6, the end of the lead terminal 34 of the divided semiconductor device is formed in a tapered shape near the surface of the resin 41, so that the lead terminal 34
It is prevented from falling off from one side. Recess 36
In addition to the V-shape, the shape may be a U-shaped recess as shown in FIG. FIG. 9 shows a perspective view of the device formed by the U-shaped concave portion 36. The same reference numerals are given to the same portions and the description will be omitted.
【００２９】尚、上述した実施形態では、３端子用のリ
ードフレームを用いて説明をしたが、リード端子を３本
以上具備するような装置にも適用が可能である。また、
上述した実施形態では、各アイランドに１つの半導体チ
ップ３９を固着したが、１つのアイランドに、例えばト
ランジスタを複数個固着すること、及び、トタンジスタ
と縦型パワーＭＯＳＦＥＴ等の他の素子との複合固着も
可能である。Although the above embodiment has been described using a lead frame for three terminals, the present invention can be applied to an apparatus having three or more lead terminals. Also,
In the above-described embodiment, one semiconductor chip 39 is fixed to each island. However, for example, a plurality of transistors are fixed to one island, and a composite fixing of a transistor and another element such as a vertical power MOSFET is performed. Is also possible.
【００３０】さらに、本実施形態では、半導体チップ３
９にトランジスタを形成したが、例えば、パワーＭＯＳ
ＦＥＴ、ＩＧＢＴ、ＨＢＴ等のデバイスを形成した半導
体チップであっても、本発明に応用できることは説明す
るまでもない。加えて、リード端子の本数を増大するこ
とでＢＩＰ、ＭＯＳ型等の集積回路等にも応用すること
ができる。Further, in this embodiment, the semiconductor chip 3
9, a power MOS
It goes without saying that the present invention can be applied to the present invention even with a semiconductor chip on which devices such as FETs, IGBTs, and HBTs are formed. In addition, by increasing the number of lead terminals, the present invention can be applied to an integrated circuit such as a BIP or MOS type.
【００３１】[0031]
【発明の効果】以上説明したように、本発明によれば、
リード端子３４がパッケージから突出しない半導体装置
を得ることができる。従って、半導体装置を実装したと
きのデッドスペースを削減し、高密度実装に適した、小
型の半導体装置を得ることができる。As described above, according to the present invention,
A semiconductor device in which the lead terminals 34 do not protrude from the package can be obtained. Therefore, a dead space when the semiconductor device is mounted can be reduced, and a small-sized semiconductor device suitable for high-density mounting can be obtained.
【００３２】外部接続端子と外部接続端子との間を樹脂
層４１で被覆した構造にできるので、装置を実装したと
きの半田ブリッジ等による端子間短絡の事故を防止でき
る。パッケージの外形をダイシングブレードによる切断
面で構成することにより、アイランド３３と樹脂４１の
端面との寸法精度を向上できる。これにより、パッケー
ジサイズを小型化できると同時に、アイランド３３の面
積を増大して、収納可能な半導体チップ３９のチップサ
イズを増大できる。Since the structure between the external connection terminal and the external connection terminal is covered with the resin layer 41, it is possible to prevent a short circuit between terminals due to a solder bridge or the like when the device is mounted. By configuring the outer shape of the package with a cut surface by a dicing blade, the dimensional accuracy between the island 33 and the end face of the resin 41 can be improved. Thereby, the package size can be reduced, and at the same time, the area of the island 33 can be increased, and the chip size of the semiconductor chip 39 that can be stored can be increased.
【００３３】小型パッケージにも関わらず、凹部３６に
よって、リード端子３４の先端部を先細りの形状に加工
したので、リード端子３４が樹脂４１からは容易に抜け
落ちない形状に加工できる。Despite the small package, the leading end of the lead terminal 34 is formed into a tapered shape by the recess 36, so that the lead terminal 34 can be formed into a shape that does not easily fall off the resin 41.
【図１】本発明の製造方法を説明する為の（Ａ）平面
図、（Ｂ）断面図である。FIG. 1A is a plan view and FIG. 1B is a cross-sectional view for explaining a manufacturing method of the present invention.
【図２】本発明の製造方法を説明する為の（Ａ）平面
図、（Ｂ）断面図である。FIG. 2A is a plan view and FIG. 2B is a cross-sectional view for explaining the manufacturing method of the present invention.
【図３】本発明の製造方法を説明する為の（Ａ）平面
図、（Ｂ）断面図である。3A is a plan view and FIG. 3B is a cross-sectional view for explaining the manufacturing method of the present invention.
【図４】本発明の製造方法を説明する為の（Ａ）平面
図、（Ｂ）断面図である。4A is a plan view and FIG. 4B is a cross-sectional view for explaining the manufacturing method of the present invention.
【図５】本発明の製造方法を説明する為の（Ａ）平面
図、（Ｂ）断面図である。5A is a plan view and FIG. 5B is a cross-sectional view for explaining the manufacturing method of the present invention.
【図６】本発明の半導体装置を裏面側からみた斜視図で
ある。FIG. 6 is a perspective view of the semiconductor device of the present invention as viewed from the back side.
【図７】本発明の半導体装置を実装したときの状態を説
明する断面図である。FIG. 7 is a cross-sectional view illustrating a state when the semiconductor device of the present invention is mounted.
【図８】本発明の他の実施の形態を説明するための平面
図である。FIG. 8 is a plan view for explaining another embodiment of the present invention.
【図９】本発明の他の実施の形態を説明するための斜視
図である。FIG. 9 is a perspective view for explaining another embodiment of the present invention.
【図１０】従来の半導体装置を説明する図である。FIG. 10 is a diagram illustrating a conventional semiconductor device.
Claims (4)
ドと、前記アイランドに先端を近接する複数本の外部接
続用のリード端子と、前記アイランド及びリード端子を
保持するための枠体部と、前記リード端子の切断予定箇
所に部分的に線幅が細くなるように形成した凹部と、を
具備するリードフレームを準備する工程と、 前記アイランド上に前記半導体チップを搭載する工程
と、 前記アイランドと前記リード端子とを電気的に接続する
工程と、 前記凹部で前記樹脂と前記リード端子とを切断して個々
の半導体装置を分離する工程と、を具備することを特徴
とする半導体装置の製造方法。1. An island for fixing a semiconductor chip, a plurality of lead terminals for external connection near a tip of the island, a frame body for holding the island and the lead terminal, and the lead A step of preparing a lead frame having a concave portion formed so that a line width is partially reduced at a portion where a terminal is to be cut; a step of mounting the semiconductor chip on the island; and the island and the lead A method of manufacturing a semiconductor device, comprising: a step of electrically connecting a terminal; and a step of cutting the resin and the lead terminal at the recess to separate individual semiconductor devices.
する請求項３記載の半導体装置の製造方法。2. The method according to claim 3, wherein the recess has a V-shape.
とする請求項３記載の半導体装置の製造方法。3. The method according to claim 3, wherein the recess has a U-shape.
ァーモールドであることを特徴とする請求項１記載の半
導体装置の製造方法。4. The method according to claim 1, wherein the step of forming the resin layer is transfer molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35975097A JP3877410B2 (en) | 1997-12-26 | 1997-12-26 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35975097A JP3877410B2 (en) | 1997-12-26 | 1997-12-26 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11191562A true JPH11191562A (en) | 1999-07-13 |
| JP3877410B2 JP3877410B2 (en) | 2007-02-07 |
Family
ID=18466112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35975097A Expired - Lifetime JP3877410B2 (en) | 1997-12-26 | 1997-12-26 | Manufacturing method of semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3877410B2 (en) |
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