KR19990024255U - Stacked Ball Grid Array Package - Google Patents

Abstract

The present invention relates to a stacked ball grid array package in which two semiconductor chips are stacked on a substrate having a circuit pattern to increase mounting efficiency. In the stacked ball grid array package of the present invention, a plurality of first bonding pads are provided at a center portion and an edge portion of an upper surface of a substrate having a circuit pattern, and the first bonding pads provided at the center portion are disposed at an edge portion thereof. A first semiconductor chip connected to a portion of the first bonding pad and a metal line, respectively, is attached to the first semiconductor chip, and second bonding pads are provided on an upper surface of the first bonding pad, and electrical connection means are formed on the second bonding pads. The second semiconductor chip with solder bumps is attached so that its upper surface faces the upper surface of the first semiconductor chip. In this case, the first bonding pads provided in the center portion of the first semiconductor chip and the second bonding pads of the second semiconductor chip have the same position and are electrically connected by solder bumps. In addition, the first semiconductor chip is electrically connected to the first bonding pads provided at the upper surface edge thereof by the circuit pattern of the substrate and the metal wire, and the spatial region on the substrate including the semiconductor chips and the metal wire is sealed with an epoxy resin. The lower surface of the substrate is provided with solder balls for mounting.

Description

Stacked Ball Grid Array Package

The present invention relates to a semiconductor package, and more particularly, to a stacked ball grid array package in which another semiconductor chip is stacked on a semiconductor chip in order to improve mounting efficiency.

In general, semiconductor chips obtained through known semiconductor device manufacturing processes are packaged through a series of assembly processes such as chip cutting, chip attachment, wire bonding, molding, and dream / forming.

A typical example of a semiconductor package manufactured through the above assembly process is illustrated in FIG. 1, which will be described below.

As shown, the semiconductor chip 1 with a plurality of electrodes 1a is attached on the die pad 2a of the downset lead frame, and the electrodes of the semiconductor chip 1 are attached. 1a is electrically connected to the inner lead 2b of the lead frame by the metal wire 3. In addition, the spatial region including the semiconductor chip 1 and the inner lead wire-bonded thereto is sealed by an epoxy molding compound such as an epoxy resin, and the substrate is formed on the outside of the package body 4 formed of the molding compound. The out lead 2c of the lead frame for mounting on the protrusion protrudes.

However, the semiconductor package as described above has a problem in that the mounting on the substrate is very difficult as the pitch between the outleads protruding out of the package body becomes smaller and smaller.

Therefore, in recent years, as a method for solving the above problems, a Ball Grid Array (hereinafter referred to as BGA) package has been manufactured. This BGA package has the advantage of easy mounting because it mounts the package on the motherboard using solder balls, and improves electrical performance by providing a short interconnection length between the package and the motherboard. There is an advantage to this.

FIG. 2 is a view illustrating a BGA package according to the prior art, and as shown, the semiconductor chip 11 is attached to the substrate 12 with a predetermined circuit pattern by an adhesive, and the semiconductor chip 11. ) And the substrate 12 are electrically connected by the metal wire 13. Although not shown, a plurality of bonding pads are provided on an upper surface of the semiconductor chip, predetermined electrode terminals are provided on a substrate, and metal wires are electrically connected between the bonding pads and the electrode terminals, respectively.

Subsequently, a predetermined area of the substrate 12 including the semiconductor chip 11 and the electrode terminals wire-bonded thereto is sealed by the molding compound 14, and a mother board (not shown) is provided on the lower surface of the substrate 12. A plurality of solder balls 15 are formed for electrical connection with the power supply terminals provided on the < RTI ID = 0.0 >

However, the BGA package as described above has a problem in that the mounting area is large because each of them is individually mounted on the motherboard 20, and the two or more BGA packages 21 are mounted on the mother board. In the case of mounting each on the board 20, it is difficult to design a circuit pattern for signal transmission on the motherboard 20.

Therefore, the present invention has been made to solve the above problems, by stacking another semiconductor chip on the semiconductor chip, it is possible to reduce the mounting area and to simplify the circuit pattern designed on the motherboard The purpose is to provide a stacked BGA package.

1 is a cross-sectional view showing a conventional general semiconductor package.

2 is a cross-sectional view of a conventional ball grid array package.

3 is a view for explaining a method of mounting a conventional ball grid array package.

4 is a view showing a stacked ball grid array package of the present invention.

5 is a plan view illustrating bonding pads of a first semiconductor chip according to an embodiment of the present invention;

6 is a plan view illustrating bonding pads of a second semiconductor chip according to an embodiment of the present invention;

7 is a plan view illustrating bonding pads in a state in which first and second semiconductor chips are stacked according to an embodiment of the present invention;

(Explanation of symbols for the main parts of the drawing)

30: first semiconductor chip 32: first bonding pad

34 metal line 40 second semiconductor chip

42: second bonding pad 44: solder bump

50: substrate 52: adhesive

54 metal wire 56 epoxy resin

58: solder ball

In order to achieve the above object, the stacked BGA package according to the present invention includes a plurality of first bonding pads provided at a center portion and an edge portion of an upper surface of a substrate on which a circuit pattern is provided, and a first bonding portion provided at the center portion. The pads are attached to a portion of the first bonding pad provided at the edge portion and a first semiconductor chip connected to each other by metal lines. Second pads are provided on the first semiconductor chip, and second bonding pads are disposed on an upper surface thereof. On the pads, an electrical connection means is attached to the second semiconductor chip with solder bumps so that its upper surface faces the upper surface of the first semiconductor chip. In this case, the first bonding pads provided in the center portion of the first semiconductor chip and the second bonding pads of the second semiconductor chip have the same position and are electrically connected by solder bumps.

In addition, the first semiconductor chip is electrically connected to the first bonding pads provided at the upper surface edge thereof by the circuit pattern of the substrate and the metal wire, and the spatial region on the substrate including the semiconductor chips and the metal wire is sealed with an epoxy resin. The lower surface of the substrate is provided with solder balls for mounting.

According to the present invention, since two semiconductor chips are stacked to fabricate a BGA type package, the mounting area can be reduced, and the design of the substrate can be facilitated.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a cross-sectional view illustrating a stacked BGA package according to an embodiment of the present invention. As illustrated, the stacked BGA package of the present invention is bonded onto a substrate 50 having a predetermined circuit pattern (not shown). The first semiconductor chip 30 having the pads 32 provided on the upper surface is attached and fixed by an adhesive 52 such as silver paste, and is bonded to the upper surface on the first semiconductor chip 30 as well. The second semiconductor chip 40 provided with the pads 42 is attached and fixed. Here, solder bumps 44 are formed on the bonding pads 42 of the second semiconductor chip 40, respectively, and the upper surface of the second semiconductor chip 40 is the first semiconductor chip ( It is disposed to face the upper surface of the 30, it is electrically connected to the first semiconductor chip 30 by the solder bump (44).

The first semiconductor chip 30 is electrically connected to the substrate by the metal wire 54, and the upper portion of the substrate 50 including the first and second semiconductor chips 30 and 40 and the metal wire 54. The spatial region of is encapsulated by epoxy resin 56. In addition, solder balls 58, which are connection means for mounting the stacked BGA package on the motherboard, are attached to the lower surface of the substrate 50. Here, in the solder ball 58, tin (Sn) and lead (Pb) are mixed in a ratio of 63:37.

In the above, the first semiconductor chip 30, as shown in Figure 5, the first bonding pads 32 are provided in each of the central portion of the upper surface and both sides of the long direction, in particular, in the center The provided first bonding pads 32 are connected to a portion of the first bonding pads 32 provided at both edge portions thereof by metal lines 34. In addition, as illustrated in FIG. 6, the second semiconductor chip 40 includes second bonding pads 42 only at the center of the upper surface thereof. In addition, the second semiconductor chip 40 may be electrically connected to the second bonding pads 42. Solder bumps (not shown) which are means are respectively formed.

In the meantime, the first and second semiconductor chips are provided in the first bonding pads 32 and the second semiconductor chip 40 provided at the center of the first semiconductor chip 30 at the time of attachment thereof. The second bonding pads 42 are manufactured to be in the same position. Therefore, as shown in FIG. 7, when the second semiconductor chip 40 is attached to the first semiconductor chip 30 so that its upper surface faces the first semiconductor chip 30, the first semiconductor chip 30 is provided at the center of the first semiconductor chip 30. The first bonding pads 32 and the second bonding pads 42 of the second semiconductor chip 40 are at the same position, and solder bumps (not shown) are formed on the second bonding pads 42. As such, the first and second bonding pads 32 and 42 are electrically connected to each other.

Therefore, in the first semiconductor chip 30, the first bonding pads 32 provided at both edges thereof are connected to the circuit pattern of the substrate 50 by the metal wire 54, and the first semiconductor chip ( Some of the first bonding pads 32 provided at both edges of the 30 are connected to the first bonding pads 32 provided at the center thereof by the metal line 34, respectively. Since the first bonding pads 32 provided at the center of 30 are electrically connected to the second bonding pads 42 of the second semiconductor chip 40 through the solder bumps 44, eventually, The first and second semiconductor chips 30 and 40 are electrically connected to the substrate 50, respectively.

As described above, the stacked BGA package of the present invention can reduce the mounting area on the motherboard by stacking another semiconductor chip on the semiconductor chip, and can simplify the circuit pattern designed on the motherboard. have. In addition, since two semiconductor chips are manufactured in one package, manufacturing cost can be reduced.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Therefore, hereinafter, the scope of the utility model registration request can be understood to include all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (6)

A first semiconductor chip is attached and fixed on a substrate with a circuit pattern, and a second semiconductor chip is attached on the first semiconductor chip such that an upper surface thereof faces an upper surface of the first semiconductor chip. The semiconductor chips and the substrate are electrically connected by metal wires, and the spatial region on the upper part of the substrate including the semiconductor chips and the metal wires is sealed by an epoxy resin, and solder balls for mounting are mounted on the lower surface of the substrate. Stacked ball grid array package, characterized in that provided. The semiconductor chip of claim 1, wherein the first semiconductor chip has bonding pads formed at a center portion of the upper surface thereof and at both edge portions thereof in a long direction, and the bonding pads provided at the center portion each have a portion of the bonding pads provided at both edges thereof. Stacked ball grid array package, characterized in that connected by metal lines. 3. The stacked ball grid array package of claim 2, wherein the second semiconductor chip is provided with bonding pads at a central portion thereof. 4. The stacked ball grid array package of claim 3, wherein solder bumps as electrical connection means are formed on the bonding pads of the second semiconductor chip. The semiconductor device of claim 3, wherein the first semiconductor chip and the second semiconductor chip have the same bonding pads provided at the center portion of the first semiconductor chip and bonding pads provided at the second semiconductor chip. And arranged electrically connected by the solder bumps. 3. The stacked ball grid array package of claim 2, wherein the metal wires connect circuit patterns of the substrate and bonding pads provided at both edges of the second semiconductor chip.