KR100401019B1 - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
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- KR100401019B1 KR100401019B1 KR10-1999-0065930A KR19990065930A KR100401019B1 KR 100401019 B1 KR100401019 B1 KR 100401019B1 KR 19990065930 A KR19990065930 A KR 19990065930A KR 100401019 B1 KR100401019 B1 KR 100401019B1
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- circuit board
- semiconductor chip
- input
- semiconductor
- circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 볼그리드어레이 패키지 기술과 플립칩 패키지 기술을 응용하여, 반도체칩 및 반도체패키지끼리 적층가능하게 함으로써, 고밀도화 및 고기능화한 시스템을 용이하게 구현할 수 있도록, 상,하로 대향하는 면에 다수의 입출력패드가 형성된 동시에, 상기 입출력패드중 특정 입출력패드는 도전성범프에 의해 상호 접속되어 있는 다수의 반도체칩과; 상기 반도체칩의 입출력패드가 형성된 면의 반대면에 각각 접착되어 있으며, 상기 반도체칩의 입출력패드가 형성된 면을 향하는 표면에는 본드핑거를, 그 반대면에는 볼랜드를 포함하는 회로패턴이 형성된 다수의 회로기판과; 상기 각 반도체칩의 특정 입출력패드와 상기 각 회로기판의 본드핑거를 접속하는 다수의 도전성와이어와; 상기 반도체칩의 상,하면에 각각 접착된 회로기판 사이에 충진된 봉지재와; 상기 회로기판중 적어도 하나의 회로기판에 형성된 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 함.The present invention relates to a semiconductor package and a method for manufacturing the same. By applying a ball grid array package technology and a flip chip package technology, the semiconductor chip and the semiconductor package can be stacked, so that a high density and high functional system can be easily implemented. A plurality of input / output pads are formed on a surface facing up and down, and specific input / output pads among the input / output pads are connected to each other by conductive bumps; A plurality of circuits each having a circuit pattern including a bond finger on a surface facing the surface on which the input / output pad of the semiconductor chip is formed and a surface facing the surface on which the input / output pad of the semiconductor chip is formed; A substrate; A plurality of conductive wires connecting the specific input / output pads of the semiconductor chips to the bond fingers of the circuit boards; An encapsulant filled between a circuit board bonded to upper and lower surfaces of the semiconductor chip; It characterized in that it comprises a plurality of conductive balls fused to the ball land formed on at least one of the circuit board.
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 볼그리드어레이(Ball Grid Array) 패키지 기술과 플립칩(Flip Chip) 패키지 기술을 응용한 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package using a ball grid array package technology and a flip chip package technology.
통상적으로 볼그리드어레이 패키지는 써킷필름, 써킷테이프 또는 인쇄회로기판(이하 '써킷필름'으로 통칭함) 등에 반도체칩을 탑재하고, 상기 반도체칩과 써킷필름을 도전성와이어로 상호 접속한 후, 봉지재로 상기 반도체칩 등을 원사이드 몰딩하며, 입출력 단자로서 상기 써킷필름의 저면에 도전성볼을 어레이된 상태로 융착하여 제조된 반도체패키지를 말한다.In general, a ball grid array package includes a semiconductor chip mounted on a circuit film, a circuit tape or a printed circuit board (hereinafter referred to as a 'circuit film'), and interconnects the semiconductor chip and the circuit film with conductive wires, The semiconductor package is a one-side molding of the semiconductor chip and the like, and is a semiconductor package manufactured by fusion bonding conductive balls on the bottom surface of the circuit film as an input / output terminal.
한편, 플립칩 패키지는 상기와 같은 볼그리드어레이 패키지 등에서 반도체칩과 써킷필름을 접속하는 수단으로서 통상적인 도전성와이어대신 골드볼 또는 솔더볼 등의 도전성볼을 이용하여 접속한 패키지를 말한다.On the other hand, the flip chip package as a means for connecting the semiconductor chip and the circuit film in the ball grid array package as described above refers to a package connected by using conductive balls such as gold balls or solder balls instead of conventional conductive wires.
상기한 두 패키지 모두 통상 1개의 반도체칩이 탑재되며, 또한 마더보드에도 상기 1개의 반도체패키지가 실장되어 사용되고 있다.In the above two packages, one semiconductor chip is usually mounted, and one semiconductor package is mounted and used on a motherboard.
그러나 이러한 반도체패키지에 대하여 적층 가능한 반도체패키지는 아직 개시된 바 없으며, 따라서 좁은 면적의 마더보드상에서 고밀도, 고기능화한 시스템을 구현하는데는 한계가 있다.However, a stackable semiconductor package has not yet been disclosed for such a semiconductor package, and thus there is a limit in implementing a high density, highly functionalized system on a small area motherboard.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 볼그리드어레이 패키지 기술과 플립칩 패키지 기술을 응용하여, 반도체패키지끼리 적층가능하게 함으로써, 고밀도화 및 고기능화한 시스템을 용이하게 구현할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and by applying the ball grid array package technology and flip chip package technology, the semiconductor packages can be stacked, it is possible to easily implement a high-density and highly functionalized system. The present invention provides a semiconductor package and a method of manufacturing the same.
도1은 본 발명에 의한 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor package according to the present invention.
도2는 본 발명에 의한 반도체패키지를 도시한 사시도이다.2 is a perspective view showing a semiconductor package according to the present invention.
도3a 내지 도3e는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 설명도이다.3A to 3E are explanatory views showing a method for manufacturing a semiconductor package according to the present invention.
도4a 및 도4b는 본 발명에 의한 반도체패키지가 적층된 상태를 도시한 것이다.4A and 4B illustrate a state in which semiconductor packages according to the present invention are stacked.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 본 발명에 의한 반도체패키지100; Semiconductor package according to the present invention
2; 제1반도체칩 4; 입출력패드2; A first semiconductor chip 4; I / O pad
6; 제2반도체칩 8; 입출력패드6; Second semiconductor chip 8; I / O pad
10; 제1회로기판 12; 제1회로기판의 볼랜드10; A first circuit board 12; Borland of the First Circuit Board
14; 제1회로기판의 본드핑거 16; 제1회로기판의 필름14; Bond fingers 16 of the first circuit board; Film of the first circuit board
20; 제2회로기판 22; 제2회로기판의 볼랜드20; Second circuit board 22; Borland of the second circuit board
24; 제2회로기판의 본드핑거 26; 제2회로기판의 필름24; Bond fingers 26 of the second circuit board; Film of the second circuit board
30,31; 도전성와이어 40; 도전성범프30,31; Conductive wire 40; Conductive Bump
50; 봉지재 60; 도전성볼50; Encapsulant 60; Conductive ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상,하로 대향하는 면에 다수의 입출력패드가 형성된 동시에, 상기 입출력패드중 특정 입출력패드는 도전성범프에 의해 상호 접속되어 있는 다수의 반도체칩과; 상기 반도체칩의 입출력패드가 형성된 면의 반대면에 각각 접착되어 있으며, 상기 반도체칩의 입출력패드가 형성된 면을 향하는 표면에는 본드핑거를, 그 반대면에는 볼랜드를 포함하는 회로패턴이 형성된 다수의 회로기판과; 상기 각 반도체칩의 특정 입출력패드와 상기 각 회로기판의 본드핑거를 접속하는 다수의 도전성와이어와; 상기 반도체칩의 상,하면에 각각 접착된 회로기판 사이에 충진된 봉지재와; 상기 회로기판중 적어도 하나의 회로기판에 형성된 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention includes a plurality of input / output pads formed on upper and lower facing surfaces, and specific input / output pads among the input / output pads are connected to a plurality of semiconductor chips interconnected by conductive bumps. ; A plurality of circuits each having a circuit pattern including a bond finger on a surface facing the surface on which the input / output pad of the semiconductor chip is formed and a surface facing the surface on which the input / output pad of the semiconductor chip is formed; A substrate; A plurality of conductive wires connecting the specific input / output pads of the semiconductor chips to the bond fingers of the circuit boards; An encapsulant filled between a circuit board bonded to upper and lower surfaces of the semiconductor chip; It characterized in that it comprises a plurality of conductive balls fused to the ball land formed on at least one of the circuit board.
여기서, 상기 반도체패키지는 상,하로 적어도 2개 이상이 적층되어 이루어질 수 있다. 또한, 상기 반도체패키지는 첫 번째 반도체패키지의 어느 한 회로기판에 형성된 도전성볼이 두 번째 반도체패키지의 어느 한 회로기판의 볼랜드에 융착되어 상호 적층될 수 있다.Here, at least two or more semiconductor packages may be stacked up and down. In addition, the semiconductor package may be laminated on the conductive ball formed on any one circuit board of the first semiconductor package is fused to the ball land of any one circuit board of the second semiconductor package.
또한, 상기 회로기판은 수지층을 중심으로 상,하면에 본드핑거, 볼랜드 등의 회로패턴이 형성되고, 상,하면의 회로패턴은 도전성비아홀로 서로 연결된 인쇄회로기판일 수 있다.In addition, the circuit board may have a circuit pattern such as bond fingers and borland formed on upper and lower surfaces of the resin layer, and the upper and lower circuit patterns may be printed circuit boards connected to each other by conductive via holes.
또한, 상기 회로기판은 가요성 필름 또는 가요성 테이프에 본드핑거, 볼랜드 등의 회로패턴이 형성된 써킷필름 또는 써킷테이프일 수 있다.In addition, the circuit board may be a circuit film or a circuit tape on which a circuit pattern such as bond finger or borland is formed on the flexible film or the flexible tape.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 구비된 제1반도체칩과; 하면에 다수의 입출력패드가 구비된 제2반도체칩과; 상기 제1반도체칩 및 제2반도체칩의 특정한 입출력패드를 상호 전기적으로 접속하는 도전성범프와; 상기 제1반도체칩의 하면에 접착되어 있으며, 상면에는 본드핑거를, 하면에는 볼랜드를 포함하는 회로패턴이 형성된 제1회로기판과; 상기 제1반도체칩의 특정 입출력패드와 상기 제1회로기판의 본드핑거를 전기적으로 접속하는 제1도전성와이어와; 상기 제2반도체칩의 상면에 위치되어 있으며, 상면에는 볼랜드를, 하면에는 본드핑거를 포함하는 회로패턴이 형성된 제2회로기판과; 상기 제2반도체칩의 특정 입출력패드와 상기 제2회로기판의 본드핑거를 접속하는 제2도전성와이어와; 상기 제1회로기판과 제2회로기판 사이에 충진된 봉지재와; 상기 제1회로기판의 각 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In addition, the semiconductor package according to the present invention to achieve the above object is a first semiconductor chip having a plurality of input and output pads on the upper surface; A second semiconductor chip having a plurality of input / output pads formed on a bottom surface thereof; Conductive bumps electrically connecting the specific input / output pads of the first semiconductor chip and the second semiconductor chip; A first circuit board adhered to a lower surface of the first semiconductor chip, and having a circuit pattern including a bond finger on an upper surface and a ball land on a lower surface thereof; A first conductive wire electrically connecting a specific input / output pad of the first semiconductor chip to a bond finger of the first circuit board; A second circuit board positioned on an upper surface of the second semiconductor chip, the circuit pattern including a ball land on the upper surface and a bond finger on the lower surface; A second conductive wire connecting the specific input / output pad of the second semiconductor chip and the bond finger of the second circuit board; An encapsulant filled between the first circuit board and the second circuit board; It characterized in that it comprises a plurality of conductive balls fused to each ball land of the first circuit board.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 일면에는 본드핑거를, 타면에는 볼랜드를 포함하는 회로패턴이 형성된 2개의 회로기판을 제공하고, 상기 각 회로기판의 볼랜드가 형성된 면에 반도체칩을 접착하는 단계와; 상기 반도체칩중 어느 하나에는 특정 입출력패드에 도전성범프를 형성하고, 다른 입출력패드는 어느 한 회로기판의 본드핑거에 도전성와이어를 이용하여 접속하고, 또한 다른 회로기판에 접착된 반도체칩의 입출력패드는 그 회로기판의 본드핑거에 도전성와이어를 이용하여 접속하는 단계와; 상기 각 회로기판에 접착된 반도체칩을 상기 도전성범프를 이용하여 상호 접속시키는 단계와; 상기 각 회로기판 사이에 봉지재를 충진하는 단계와; 상기 회로기판중 어느 한 회로기판의 볼랜드에 도전성볼을 융착하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention provides two circuit boards each having a circuit pattern including a bond finger on one side and a ball land on the other side, and the lands of the respective circuit boards Bonding a semiconductor chip to the formed surface; In one of the semiconductor chips, a conductive bump is formed on a specific input / output pad, and another input / output pad is connected to a bond finger of one circuit board using conductive wires, and the input / output pad of the semiconductor chip bonded to the other circuit board is Connecting the bond finger of the circuit board using conductive wires; Interconnecting the semiconductor chips bonded to each of the circuit boards using the conductive bumps; Filling an encapsulant between each circuit board; And fusion bonding the conductive balls to the ball lands of any one of the circuit boards.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면 2개의 반도체칩을 상호 접속하여 고밀도 및 고기능화한 반도체패키지를 얻을 수 있다. 또한 각 반도체칩에 접착된 회로기판에는 모두 볼랜드가 형성되어 있음으로써, 적어도 2개 이상의 반도체패키지를 상,하로 적층할 수 있게 된다. 따라서, 예를 들면 SRAM, DSP, Flash Memory 칩을 동시에 다수개 적층하여 패키징하고, 더불어 이러한 반도체패키지를 또한 다수개 적층할 수 있게 됨으로써 좁은 마더보드상에서 고밀도, 고기능화한 시스템을 구현할 수 있게 된다.As described above, according to the semiconductor package and the manufacturing method of the present invention, two semiconductor chips are interconnected to obtain a high-density and highly functional semiconductor package. In addition, since all the lands are formed on the circuit boards bonded to each semiconductor chip, at least two or more semiconductor packages can be stacked up and down. Therefore, for example, by stacking and packaging a plurality of SRAM, DSP, and Flash Memory chips simultaneously, and also stacking a plurality of such semiconductor packages, a high density, high performance system can be realized on a narrow motherboard.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도1은 본 발명에 의한 반도체패키지(100)를 도시한 단면도이고, 도2는 본 발명에 의한 반도체패키지(100)를 도시한 사시도이다.1 is a cross-sectional view showing a semiconductor package 100 according to the present invention, Figure 2 is a perspective view showing a semiconductor package 100 according to the present invention.
도시된 바와 같이 중앙부에는 상,하면에 각각 다수의 입출력패드(4,8)가 구비된 반도체칩(2,6)이 위치되어 있으며, 상기 입출력패드(4,8)중 특정 입출력패드(4,8)는 도전성범프(40)에 의해 상호 접속(플립칩 기술에 의해 접속)되어 있다. 여기서 도면중 하부에 도시된 반도체칩을 제1반도체칩(2), 상부에 도시된 반도체칩을 제2반도체칩(6)으로 각각 구별하여 칭하기로 한다.As shown in the figure, semiconductor chips 2 and 6 each having a plurality of input / output pads 4 and 8 are positioned at upper and lower surfaces thereof, and specific input / output pads 4 and 8 of the input / output pads 4 and 8 are positioned. 8 is interconnected by the conductive bumps 40 (connected by flip chip technology). Here, the semiconductor chip shown in the lower part of the drawing is referred to as a first semiconductor chip 2 and the semiconductor chip shown in the upper part is referred to as a second semiconductor chip 6, respectively.
상기 도전성범프(40)는 바람직하기로 금(Au) 또는 솔더(Solder) 등이 바람직하지만 여기서 그 재질을 한정하는 것은 아니다.The conductive bump 40 is preferably gold (Au) or solder (Solder) and the like, but the material is not limited thereto.
상기 제1반도체칩(2) 및 제2반도체칩(6)의 입출력패드(4,8)가 형성된 면의 반대면에는 각각 회로기판(10,20)이 접착되어 있다. 마찬가지로 여기서 도면중 하부에 도시된 회로기판을 제1회로기판(10), 상부에 도시된 회로기판을 제2회로기판(20)으로 각각 구별하여 칭하기로 한다.The circuit boards 10 and 20 are bonded to opposite surfaces of the first semiconductor chip 2 and the second semiconductor chip 6 on the opposite surfaces of the input / output pads 4 and 8, respectively. Likewise, the circuit board shown in the lower part of the figure will be referred to as a first circuit board 10 and the circuit board shown in the upper part as a second circuit board 20, respectively.
상기 제1회로기판(10) 및 제2회로기판(20)은 서로 대향하는 형태로 형성되어 있다. 즉, 상기 반도체칩의 입출력패드(4,8)가 형성된 면을 향하여는 본드핑거(14,24)가, 그 반대면에는 볼랜드(12,22)가 포함된 회로패턴이 형성되어 있으며, 상기 회로패턴은 가요성 필름(16,26) 또는 가요성 테이프에 형성되어 상,하면으로 오픈된 형태를 한다.The first circuit board 10 and the second circuit board 20 are formed to face each other. That is, a circuit pattern including bond fingers 14 and 24 facing the surface on which the input / output pads 4 and 8 are formed on the semiconductor chip and ball lands 12 and 22 on the opposite surface is formed. The pattern is formed on the flexible films 16 and 26 or the flexible tape to form an open top and bottom surface.
여기서 주지된 바와 같이 상기 본드핑거(14,24) 및 볼랜드(12,22)를 포함하는 회로패턴은 통상적인 구리 박막이다. 또한 상기 볼랜드(12,22)에는 금(Au) 또는 은(Ag) 등이 도금될 수 있으며, 상기 볼랜드(12,22)에도 금(Au), 니켈(Ni) 및 팔라디엄(Pd) 등이 도금될 수 있다.As noted herein, the circuit pattern including the bond fingers 14 and 24 and the borland 12 and 22 is a conventional copper thin film. In addition, the ball lands 12 and 22 may be plated with gold (Au) or silver (Ag), and the ball lands 12 and 22 may be plated with gold (Au), nickel (Ni), and palladium (Pd). Can be plated.
상기 제1반도체칩(2)의 특정 입출력패드(4) 즉, 도전성범프(40)가 형성되지않은 그 둘레의 입출력패드(4)는 상기 제1회로기판(10)의 본드핑거(14)와 전기적으로 접속되어 있다. 상기 접속수단으로서는 골드와이어나 알루미늄와이어와 같은 도전성와이어(30)가 바람직하다. 마찬가지로 상기 제2반도체칩(6)의 입출력패드(8) 역시 제2회로기판의 본드핑거(24)에 도전성와이어(31)로 접속되어 있다.The specific input / output pad 4 of the first semiconductor chip 2, that is, the input / output pad 4 around the conductive bump 40, is not formed, and the bond fingers 14 of the first circuit board 10 It is electrically connected. As the connection means, a conductive wire 30 such as gold wire or aluminum wire is preferable. Similarly, the input / output pad 8 of the second semiconductor chip 6 is also connected to the bond finger 24 of the second circuit board by the conductive wire 31.
계속해서, 상기 제1회로기판(10)과 제2회로기판(20) 사이에는 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재(50)가 충진되어 제1반도체칩(2), 제2반도체칩(6), 도전성와이어(30,31) 및 도전성범프(40) 등을 외부 환경으로부터 보호하고, 반도체패키지(100)가 일정한 형태를 갖도록 되어 있다.Subsequently, an encapsulant 50 such as an epoxy molding compound or a liquid encapsulant is filled between the first circuit board 10 and the second circuit board 20 so that the first semiconductor chip 2 and the second semiconductor chip are filled. (6), the conductive wires 30 and 31, the conductive bumps 40, and the like are protected from the external environment, and the semiconductor package 100 has a certain shape.
또한, 상기 제1회로기판(10)의 하면에 형성된 각 볼랜드(12)에는 솔더볼과 같은 도전성볼(60)이 융착되어 있음으로써 마더보드에 표면실장이 가능하게 되어 있다.In addition, since the conductive balls 60 such as solder balls are fused to each ball land 12 formed on the lower surface of the first circuit board 10, surface mounting is possible on the motherboard.
이와 같이하여, 상기 반도체패키지(100)는 반도체칩이 서로 대향하여 상호 접속되어 있을 뿐만 아니라, 그 상,하면으로는 제1회로기판(10) 및 제2회로기판(20)이 구비되어 있고, 상기 제1회로기판(10)의 하면에는 도전성볼(60)이 융착되어 있고, 상기 제2회로기판(20)의 상면에는 상부를 향하여 오픈된 다수의 볼랜드(22)가 형성되어 있음으로써 다수의 반도체패키지(100)를 또한 적층할 수 있게 된다.In this way, the semiconductor package 100 is not only interconnected with the semiconductor chips facing each other, but also provided with a first circuit board 10 and a second circuit board 20 on the upper and lower surfaces thereof. The lower surface of the first circuit board 10 is fused to the conductive ball 60, the upper surface of the second circuit board 20 is formed with a plurality of ball lands 22 that are open toward the top The semiconductor package 100 can also be stacked.
여기서, 상기 회로기판은 써킷필름 및 써킷테이프에 한하여 설명하였지만, 이것으로만 한정되는 것은 아니고 딱딱한 수지층을 중심으로 상,하면에 본드핑거 및 볼랜드 등의 회로패턴이 형성되고, 상,하면의 회로패턴은 도전성비아홀로 상호연결된 통상적인 인쇄회로기판일 수도 있다.Here, although the circuit board has been described only for the circuit film and the circuit tape, the circuit boards such as bond fingers and borland are formed on the upper and lower surfaces of the upper and lower surfaces of the resin film, but are not limited thereto. The pattern may be a conventional printed circuit board interconnected with conductive via holes.
도3a 내지 도3e는 본 발명에 의한 반도체패키지(100)의 제조 방법을 도시한 설명도이다.3A to 3E are explanatory views showing a method of manufacturing the semiconductor package 100 according to the present invention.
먼저 도3a에 도시된 바와 같이, 상면에는 본드핑거(14)를 하면에는 볼랜드(12)를 포함하는 회로패턴이 형성된 제1회로기판(10)을 제공하고, 상기 제1회로기판(10)의 상면에는 다수의 입출력패드(4)가 형성된 제1반도체칩(2)을 접착제로 접착한 후, 상기 제1반도체칩(2)의 특정 입출력패드(4)와 상기 제1회로기판(10)의 본드핑거(14)를 도전성와이어(30)를 이용하여 상호 접속시킨다. 또한 상기 도전성와이어(30)가 접속되지 않은 나머지 입출력패드(4)에는 도전성범프(40)를 형성한다.First, as shown in FIG. 3A, a bond finger 14 is provided on an upper surface thereof, and a first circuit board 10 on which a circuit pattern including a ball land 12 is formed is provided on an upper surface thereof. The first semiconductor chip 2 having the plurality of input / output pads 4 formed thereon is bonded to the upper surface with an adhesive, and then the specific input / output pads 4 and the first circuit board 10 of the first semiconductor chip 2 are bonded to each other. Bond fingers 14 are interconnected using conductive wires 30. In addition, the conductive bumps 40 are formed on the remaining input / output pads 4 to which the conductive wires 30 are not connected.
여기서, 상기 도전성범프(40)는 제1반도체칩(2)을 제1회로기판(10)에 접착하기 전에 미리 형성할 수도 있으며, 이를 한정하는 것은 아니다.Here, the conductive bumps 40 may be formed in advance before bonding the first semiconductor chip 2 to the first circuit board 10, but is not limited thereto.
계속해서, 도3b에 도시된 바와 같이, 하면에는 본드핑거(24)를 상면에는 볼랜드(22)를 포함하는 회로패턴이 형성된 제2회로기판(20)을 제공하고, 상기 제2회로기판(20)의 하면에는 다수의 입출력패드(8)가 형성된 제2반도체칩(6)을 접착제로 접착한 후, 상기 제2반도체칩(6)의 특정 입출력패드(8)와 상기 제2회로기판(20)의 본드핑거(24)를 도전성와이어(31)를 이용하여 상호 접속시킨다.Subsequently, as shown in FIG. 3B, a second circuit board 20 having a circuit pattern including a bond finger 24 on a lower surface and a borland 22 on an upper surface thereof is provided, and the second circuit board 20 is provided. ), After bonding the second semiconductor chip 6 having the plurality of input / output pads 8 formed thereon with an adhesive, the specific input / output pad 8 and the second circuit board 20 of the second semiconductor chip 6 are bonded to each other. Bond fingers 24 are connected to each other using conductive wires 31.
여기서, 상기 제1회로기판(10)과 제2회로기판(20)은 실질적으로 동일한 구조의 회로기판일 수 있지만, 이를 한정하는 것은 아니다.Here, the first circuit board 10 and the second circuit board 20 may be a circuit board having substantially the same structure, but is not limited thereto.
계속해서, 도3c에 도시된 바와 같이 상기 제1반도체칩(2) 및 제2반도체칩(6)의 특정 입출력패드(8)를 미리 형성되어 있던 도전성범프(40)를 이용하여 상호 접속시킴으로써 제1반도체칩(2)과 제2반도체칩(6)의 전기적 신호가 서로 도통 가능하게 한다.Subsequently, as shown in FIG. 3C, the specific input / output pads 8 of the first semiconductor chip 2 and the second semiconductor chip 6 are interconnected by using the conductive bumps 40 formed in advance. The electrical signals of the first semiconductor chip 2 and the second semiconductor chip 6 can be conducted with each other.
계속해서, 도3d에 도시된 바와 같이 제1회로기판(10) 및 제2회로기판(20) 사이를 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재(50)를 이용하여 봉지함으로써 제1반도체칩(2), 제2반도체칩(6), 도전성와이어(30,31), 도전성범프(40) 등을 외부 환경으로부터 보호한다.Subsequently, as shown in FIG. 3D, the first semiconductor chip is sealed between the first circuit board 10 and the second circuit board 20 by using an encapsulant 50 such as an epoxy molding compound or a liquid encapsulant. (2), the second semiconductor chip 6, the conductive wires 30 and 31, the conductive bumps 40, and the like are protected from the external environment.
계속해서, 도3e에 도시된 바와 같이 제1회로기판(10)(또는 제2회로기판(20))의 볼랜드(12)에 솔더볼과 같은 도전성볼(60)을 융착함으로써 상기 반도체패키지(100)가 마더보드 등에 표면 실장 가능한 형태가 되도록 한다.Subsequently, as shown in FIG. 3E, the semiconductor package 100 is fused by welding conductive balls 60 such as solder balls to the ball lands 12 of the first circuit board 10 (or the second circuit board 20). Should be shaped like a surface mountable motherboard.
도4a 및 도4b는 본 발명에 의한 반도체패키지가 적층된 상태를 도시한 것이다.4A and 4B illustrate a state in which semiconductor packages according to the present invention are stacked.
본 발명에 의한 반도체패키지(100)는 상호 접속된 제1반도체칩 및 제2반도체칩을 중심으로 그 상,하면에 각각 제1회로기판 및 제2회로기판이 구비되고, 상기 회로기판중 제2반도체칩의 상부에 위치하는 제2회로기판은 상부를 향해 오픈된 볼랜드가 형성되고, 제1반도체칩의 하부에 위치하는 제1회로기판은 하부에 다수의 도전성볼이 융착되어 있음으로써 상호 적층 가능한 형태를 한다. 따라서 예를 들면 SRAM이나 DSP칩을 탑재한 반도체패키지 또는 Flash Memory, SRAM, 또는 DSP칩을 탑재한 반도체패키지를 모두 적층하여 하나의 반도체패키지로 통합할 수 있게 됨으로써 고밀도, 고기능화한 시스템을 구현할 수 있게 된다.In the semiconductor package 100 according to the present invention, a first circuit board and a second circuit board are provided on the upper and lower surfaces of the first semiconductor chip and the second semiconductor chip, respectively. The second circuit board positioned on the upper portion of the semiconductor chip has a ballland open toward the upper portion, and the first circuit board positioned on the lower portion of the first semiconductor chip can be stacked on the lower portion by bonding a plurality of conductive balls to the lower portion. Form. Therefore, for example, a semiconductor package containing an SRAM or a DSP chip or a semiconductor package containing a Flash memory, an SRAM, or a DSP chip can be stacked and integrated into a single semiconductor package, thereby realizing a high-density and highly functional system. do.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기 예만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, only the examples are not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면 2개의 반도체칩을 상호 접속하여 고밀도 및 고기능화한 반도체패키지를 얻을 수 있는 효과가 있다.As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, there is an effect that a semiconductor package having high density and high functionality can be obtained by interconnecting two semiconductor chips.
더불어, 각 반도체칩에 접착된 회로기판에는 모두 볼랜드가 형성되어 있음으로써, 적어도 2개 이상의 반도체패키지를 상,하로 적층할 수 있는 효과가 있다.In addition, since all the lands are formed on the circuit boards bonded to each semiconductor chip, at least two or more semiconductor packages can be stacked up and down.
따라서, 본 발명에 의한 반도체패키지를 채용한 전자제품은 적은 크기로 고밀도 및 고기능화한 전자제품을 제조할 수 있게 된다.Therefore, the electronic product employing the semiconductor package according to the present invention can produce a high density and high functional electronic products in a small size.
Claims (7)
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| US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| KR19980018136A (en) * | 1996-08-20 | 1998-06-05 | 포만 제프리 엘 | Multi-chip system and its manufacturing method |
| US5801072A (en) * | 1996-03-14 | 1998-09-01 | Lsi Logic Corporation | Method of packaging integrated circuits |
| JPH10294423A (en) * | 1997-04-17 | 1998-11-04 | Nec Corp | Semiconductor device |
| KR19990024255U (en) * | 1997-12-12 | 1999-07-05 | 김영환 | Stacked Ball Grid Array Package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| US5801072A (en) * | 1996-03-14 | 1998-09-01 | Lsi Logic Corporation | Method of packaging integrated circuits |
| KR19980018136A (en) * | 1996-08-20 | 1998-06-05 | 포만 제프리 엘 | Multi-chip system and its manufacturing method |
| JPH10294423A (en) * | 1997-04-17 | 1998-11-04 | Nec Corp | Semiconductor device |
| KR19990024255U (en) * | 1997-12-12 | 1999-07-05 | 김영환 | Stacked Ball Grid Array Package |
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