KR100401018B1 - attaching method of wafer for semiconductor package - Google Patents
attaching method of wafer for semiconductor package Download PDFInfo
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- KR100401018B1 KR100401018B1 KR10-1999-0065929A KR19990065929A KR100401018B1 KR 100401018 B1 KR100401018 B1 KR 100401018B1 KR 19990065929 A KR19990065929 A KR 19990065929A KR 100401018 B1 KR100401018 B1 KR 100401018B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
이 발명은 반도체패키지를 위한 웨이퍼의 상호 접착 방법에 관한 것으로, 2장의 웨이퍼 후면을 상호 접착하여 낱개의 적층된 반도체칩을 제공할 수 있도록, 상면에 다수의 반도체칩이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩에는 다수의 입출력패드가 형성된 제1웨이퍼를 제공하는 단계와, 하면에 다수의 반도체칩이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩에는 다수의 입출력패드가 형성되어 있고, 상기 각 입출력패드에는 도전성범프가 융착된 제2웨이퍼를 제공하는 단계와, 상기 제1웨이퍼 또는 제2웨이퍼의 후면을 상호 부착시키는 단계와, 상기 제1웨이퍼와 제2웨이퍼를 고온으로 가열하여, 상기 제1웨이퍼 및 제2웨이퍼의 부착면에 산화실리콘막이 형성되면서 상호 접착되도록 하는 단계로 이루어진 것을 특징으로 함.The present invention relates to a method of bonding wafers for a semiconductor package, wherein a plurality of semiconductor chips are formed in a substantially checkerboard shape on an upper surface thereof so as to provide two stacked semiconductor chips by bonding two wafer back surfaces together. Providing a first wafer having a plurality of input / output pads formed on each of the semiconductor chips, a plurality of semiconductor chips formed on a bottom surface of the semiconductor wafer, and a plurality of input / output pads formed on the semiconductor chips, Providing each of the input / output pads with a second wafer fused with conductive bumps, attaching the back surface of the first wafer or the second wafer to each other, and heating the first wafer and the second wafer to a high temperature, Characterized in that the silicon oxide film is formed on the attachment surface of the first wafer and the second wafer to be bonded to each other. Also.
Description
본 발명은 반도체패키지를 위한 웨이퍼의 상호 접착 방법에 관한 것으로, 보다 상세하게 설명하면 반도체칩이 적층된 채 탑재되고, 또한 2장의 웨이퍼 후면을 상호 접착하여 낱개의 적층된 반도체칩을 얻을 수 있는 반도체패키지를 위한 웨이퍼의 상호 접착 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for adhering wafers for semiconductor packages. More specifically, the present invention relates to semiconductors in which semiconductor chips are stacked and bonded together, and two wafer back surfaces are bonded to each other to obtain a single stacked semiconductor chip. A method of mutual bonding of wafers for packages.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 상기 반도체칩을 패키징한 반도체패키지 및 상기 반도체패키지들이 실장되는 전자기기도 소형화되어 가는 추세에 있다.In recent years, a large number of semiconductor chips are packaged on a motherboard such as a mobile phone, a cellular phone, a notebook computer, and designed to perform multifunction in a minimum time, and at the same time, a semiconductor package packaging the semiconductor chip. In addition, electronic devices on which the semiconductor packages are mounted are also becoming smaller.
이러한 반도체패키지는 통상 인쇄회로기판, 써킷필름(또는 써킷테이프), 리드프레임상에 하나의 반도체칩이 탑재된 채, 와이어 본딩, 몰딩 및 도전성볼 융착 공정(리드프레임을 이용한 반도체패키지에서는 이 공정이 선택 사항임) 등이 수행된 후 마더보드에 실장된다.Such a semiconductor package is usually a wire bonding, molding, and conductive ball fusion process (a semiconductor package using a lead frame) with one semiconductor chip mounted on a printed circuit board, a circuit film (or circuit tape), and a lead frame. (Optional), and then mounted on the motherboard.
그러나 상기한 종래의 반도체패키지는 인쇄회로기판상에 오직 하나의 반도체칩 만이 탑재됨으로써 반도체패키지의 고밀도화 및 고성능화에는 어느 정도의 한계가 있다. 더구나, 최근의 전자기기는 더욱 고기능화, 고용량화되어 가고 있는 추세에서 상기와 같이 단 하나의 반도체칩을 탑재한 반도체패키지 구조로서는 이를 뒷받침해줄 수 없는 문제점이 있다.However, the above-described conventional semiconductor package has a certain limitation in increasing the density and high performance of the semiconductor package because only one semiconductor chip is mounted on the printed circuit board. In addition, in recent years, electronic devices are becoming more functional and higher in capacity, and thus there is a problem that the semiconductor package structure in which only one semiconductor chip is mounted as described above cannot support this.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 다수의 반도체칩이 적층된 반도체패키지를 구비하여 고기능화 및 고용량화된 반도체패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a semiconductor package having a high functionality and a high capacity by providing a semiconductor package in which a plurality of semiconductor chips are stacked.
본 발명의 다른 목적은 상기 적층된 반도체칩을 얻기 위해 2개의 웨이퍼를 접착하여 하나의 적층된 반도체칩을 얻을 수 있는 웨이퍼의 상호 접착 방법을 제공하는데 있다.Another object of the present invention is to provide a method of mutual bonding of wafers in which two wafers are bonded to obtain the stacked semiconductor chips, thereby obtaining one stacked semiconductor chip.
도1a 내지 도1d는 본 발명의 제1,2,3,4 실시예에 의한 반도체패키지를 도시한 것으로,1A to 1D illustrate a semiconductor package according to the first, second, third and fourth embodiments of the present invention.
도1a는 인쇄회로기판을 이용한 반도체패키지를 도시한 단면도이고,Figure 1a is a cross-sectional view showing a semiconductor package using a printed circuit board,
도1b는 써킷필름을 이용한 반도체패키지를 도시한 단면도이고,Figure 1b is a cross-sectional view showing a semiconductor package using a circuit film,
도1c 및 도1d는 리드프레임을 이용한 반도체패키지를 도시한 단면도이다.1C and 1D are cross-sectional views illustrating a semiconductor package using a lead frame.
도2는 본 발명의 제5실시예에 의한 반도체패키지를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package according to a fifth embodiment of the present invention.
도3a 및 도3b는 본 발명에 의한 웨이퍼의 상호 접착 방법을 도시한 사시도이다.3A and 3B are perspective views showing the method of mutual bonding of wafers according to the present invention.
도4a 및 도4b는 본 발명에 의한 웨이퍼의 상호 접착 방법을 도시한 사시도이다.4A and 4B are perspective views showing a method of bonding the wafers according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101,102,103,104,105; 본 발명의 제1~5실시예에 의한 반도체패키지101,102,103,104,105; Semiconductor Packages According to Embodiments 1-5 of the Present Invention
2; 제1반도체칩 2a,4a; 입출력패드2; First semiconductor chips 2a and 4a; I / O pad
4; 제2반도체칩 20; 인쇄회로기판4; Second semiconductor chip 20; Printed circuit board
21; 수지층 22,32,42; 본드핑거21; Resin layers 22,32,42; Bondfinger
23,33,43; 볼랜드 24; 도전성비아홀23,33,43; Borland 24; Conductive Via Hole
25; 커버코트 30; 써킷필름25; Covercoat 30; Circuit Film
31; 필름 40; 리드프레임31; Film 40; Leadframe
41; 리드 50; 도전성와이어41; Lead 50; Conductive Wire
60; 도전성범프 70; 봉지재60; Conductive bump 70; Encapsulant
80; 도전성볼 110; 제1웨이퍼80; Conductive ball 110; 1st wafer
120; 제2웨이퍼 130; 산화실리콘막120; Second wafer 130; Silicon oxide film
140; 접착테이프140; Adhesive tape
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 형성된 제1반도체칩과; 하면에 다수의 입출력패드가 형성되어 있으며, 상기 제1반도체칩의 저면에 부착된 제2반도체칩과; 상기 제2반도체칩의 하면 및 그 외주연으로 연장되어 위치되며, 상면에는 본드핑거 및 하면에는 볼랜드가 형성된 회로패턴이 형성된 회로기판과; 상기 제1반도체칩 및 제2반도체칩의 입출력패드와 상기 회로기판의 본드핑거를 상호 전기적으로 접속시키는 접속수단과; 상기 회로기판상의 제1반도체칩, 제2반도체칩, 접속수단 등을 몰딩하는 봉지재와; 상기 회로기판의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention comprises: a first semiconductor chip having a plurality of input / output pads formed on an upper surface thereof; A second semiconductor chip having a plurality of input / output pads formed on a bottom surface thereof and attached to a bottom surface of the first semiconductor chip; A circuit board having a lower surface and an outer circumference of the second semiconductor chip, the circuit board having a bond finger formed on the upper surface thereof and a ball land formed on the lower surface thereof; Connection means for electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip with the bond fingers of the circuit board; An encapsulant for molding the first semiconductor chip, the second semiconductor chip, the connecting means and the like on the circuit board; It characterized in that it comprises a plurality of conductive balls fused to the ball land of the circuit board.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 형성된 제1반도체칩과; 하면에 다수의 입출력패드가 형성되어 있으며, 상기 제1반도체칩의 저면에 부착된 제2반도체칩과; 상기 제2반도체칩의 하면 및 그 외주연으로 연장되어 위치되며, 상면에는 본드핑거 및 하면에는 랜드가 형성된 리드와; 상기 제1반도체칩 및 제2반도체칩의 입출력패드와 상기 리드의 본드핑거를 상호 전기적으로 접속시키는 접속수단과; 상기 리드상의 제1반도체칩, 제2반도체칩, 접속수단 등을 원사이드 몰딩하는 봉지재를 포함하여 이루어진 것을 특징으로 한다.In addition, the semiconductor package according to the present invention to achieve the above object is a first semiconductor chip formed with a plurality of input and output pads on the upper surface; A second semiconductor chip having a plurality of input / output pads formed on a bottom surface thereof and attached to a bottom surface of the first semiconductor chip; A lead disposed on the lower surface of the second semiconductor chip and extending around the outer circumference thereof, and having a bond finger on the upper surface and a land on the lower surface of the second semiconductor chip; Connection means for electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the bond fingers of the leads; And an encapsulant for one-side molding of the first semiconductor chip, the second semiconductor chip, and the connecting means on the lead.
여기서, 상기 제1반도체칩과 제2반도체칩은 산화실리콘(SiO2)막에 의해 상호 접착될 수 있다.Here, the first semiconductor chip and the second semiconductor chip may be bonded to each other by a silicon oxide (SiO 2 ) film.
또한, 상기 제1반도체칩과 제2반도체칩은 양면접착테이프에 의해 상호 접착될 수도 있다.In addition, the first semiconductor chip and the second semiconductor chip may be bonded to each other by a double-sided adhesive tape.
또한, 상기 제1반도체칩과 회로기판의 본드핑거를 연결하는 접속수단은 도전성와이어이고, 상기 제2반도체칩과 회로기판의 본드핑거를 연결하는 접속수단은 도전성범프가 되도록 함이 바람직하다.In addition, the connection means for connecting the bond finger of the first semiconductor chip and the circuit board is a conductive wire, the connection means for connecting the bond finger of the second semiconductor chip and the circuit board is preferably made to be a conductive bump.
또한, 상기 회로기판은 열경화성 수지층을 중심으로 상면에는 본드핑거가, 하면에는 볼랜드가 형성되며, 상기 본드핑거와 볼랜드는 도전성비아홀에 의해 상호 연결된 인쇄회로기판일 수 있다.In addition, the circuit board may have a bond finger on the upper surface and a borland on the lower surface of the thermosetting resin layer, and the bond finger and the borland may be printed circuit boards interconnected by conductive via holes.
또한, 상기 회로기판은 필름을 중심으로 상면에는 본드핑거가, 하면에는 볼랜드가 오픈되도록 형성된 써킷필름일 수도 있다.The circuit board may be a circuit film formed such that a bond finger is formed on an upper surface of the circuit board and a ball land is opened on a lower surface of the circuit board.
또한, 상기 리드를 이용한 반도체패키지에 있어서 상기 리드는 부분에칭 기술에 의해 상기 랜드 영역의 두께가 다른 리드 두께보다 두껍게 형성되고, 봉지재는 상기 랜드가 하면으로 노출 또는 돌출되도록 봉지됨이 바람직하다.In the semiconductor package using the lead, the lead is preferably formed to have a thickness of the land area thicker than other lead thicknesses by a partial etching technique, and the encapsulant is encapsulated so that the land is exposed or protruded to the lower surface.
또한, 상기 랜드 하면에는 도전성볼이 융착될 수도 있다.In addition, a conductive ball may be fused to the lower surface of the land.
더불어, 상기 목적을 달성하기 위해 본 발명에 의한 웨이퍼의 상호 접착 방법은 상면에 다수의 반도체칩이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩에는 다수의 입출력패드가 형성된 제1웨이퍼를 제공하는 단계와; 하면에 다수의 반도체칩이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩에는 다수의 입출력패드가 형성되어 있고, 상기 각 입출력패드에는 도전성범프가 융착된 제2웨이퍼를 제공하는 단계와; 상기 제1웨이퍼 또는 제2웨이퍼의 후면을 상호 부착하는 단계와; 상기 제1웨이퍼 및 제2웨이퍼를 고온으로 가열하여 상기 부착면 사이의 산소가 실리콘과 결합함으로써 산화실리콘막을 형성하며 제1웨이퍼 및 제2웨이퍼가 상호 접착되도록 하는 단계로 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, the wafer bonding method according to the present invention has a plurality of semiconductor chips formed on the upper surface in a substantially checkered shape, and each semiconductor chip provides a first wafer having a plurality of input / output pads formed thereon. Steps; Providing a second wafer having a plurality of semiconductor chips formed on a bottom surface in a substantially checkerboard shape, each of the semiconductor chips having a plurality of input / output pads formed thereon, and each of the input / output pads fused with conductive bumps; Attaching a rear surface of the first wafer or the second wafer to each other; The first wafer and the second wafer is heated to a high temperature to form a silicon oxide film by bonding oxygen between the attachment surface with silicon to form a first wafer and the second wafer is bonded to each other.
여기서, 상기 제1웨이퍼와 제2웨이퍼의 부착면에는 수분을 개재하여 부착할 수도 있다.Here, the first wafer and the second wafer may be attached to the attachment surface via moisture.
또한, 상기 목적을 달성하기 위해 본 발명에 의한 웨이퍼의 상호 접착 방법은 상면에 다수의 반도체칩이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩에는 다수의 입출력패드가 형성된 제1웨이퍼를 제공하는 단계와; 하면에 다수의 반도체칩이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩에는 다수의 입출력패드가 형성되어 있고, 상기 각 입출력패드에는 도전성범프가 융착된 제2웨이퍼를 제공하는 단계와; 상기 제1웨이퍼 또는 제2웨이퍼의 후면에 양면접착테이프를 접착시키는 단계와; 상기 제1웨이퍼와 제2웨이퍼의 후면을 상호 접착시키는 단계로 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, the wafer bonding method according to the present invention has a plurality of semiconductor chips formed on the upper surface in a substantially checkered shape, and each of the semiconductor chips provides a first wafer having a plurality of input / output pads formed thereon. Steps; Providing a second wafer having a plurality of semiconductor chips formed on a bottom surface in a substantially checkerboard shape, each of the semiconductor chips having a plurality of input / output pads formed thereon, and each of the input / output pads fused with conductive bumps; Adhering a double-sided adhesive tape to a rear surface of the first wafer or the second wafer; And bonding the rear surfaces of the first wafer and the second wafer to each other.
여기서, 상기 양면접착테이프는 UV(Ultra Violet)테이프로 함이 바람직하다.Here, the double-sided adhesive tape is preferably made of UV (Ultra Violet) tape.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 두 개의 반도체칩을 적층한 채 인쇄회로기판, 써킷필름 또는 리드의 상면에 탑재함으로써 고기능화, 고용량화한 반도체패키지를 얻게 된다.According to the semiconductor package according to the present invention as described above, by mounting the two semiconductor chips stacked on the upper surface of the printed circuit board, circuit film or lead to obtain a high functional and high capacity semiconductor package.
또한 상기 반도체패키지에서 각 반도체칩의 접속수단으로 일측 반도체칩은 도전성범프를 이용하고 타측 반도체칩은 도전성와이어를 이용함으로써, 서로 대향되어 위치된 반도체칩의 입출력패드를 써킷패턴에 모두 연결할 수 있는 반도체패키지를 얻게 된다.In the semiconductor package, one semiconductor chip is used as a connection means of each semiconductor chip in the semiconductor package, and the other semiconductor chip is used as a conductive wire, so that the input / output pads of the semiconductor chips located opposite to each other can be connected to the circuit pattern. You get a package.
또한 본 발명에 의한 웨이퍼의 상호 접착 방법에 의하면, 2장의 웨이퍼 후면 사이에 수분(또는 양면접착테이프나 UV테이프)을 제공하고 이를 소정 온도로 가열함으로써 2장의 웨이퍼를 간단히 접착시킬 수 있어, 별도의 복잡한 설비를 필요로 하지 않는다.(여기서, 상기 수분, 테이프 등이 없이, 상기 2장의 웨이퍼의 후면을직접 부착한 후 고온으로 가열하여도 됨)In addition, according to the method of mutual bonding of wafers according to the present invention, two wafers can be easily bonded by providing water (or double-sided adhesive tape or UV tape) between two wafer backsides and heating them to a predetermined temperature. It does not require complicated equipment. (In this case, the back surface of the two wafers may be directly attached and heated to a high temperature without the above moisture or tape.)
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도1a 내지 도1d는 본 발명의 제1,2,3,4 실시예에 의한 반도체패키지(101,102,103,104)를 도시한 것으로, 도1a는 인쇄회로기판(20)을 이용한 반도체패키지(101)를 도시한 단면도이고, 도1b는 써킷필름(30)을 이용한 반도체패키지(102)를 도시한 단면도이고, 도1c 및 도1d는 리드프레임(40)을 이용한 반도체패키지(103,104)를 도시한 단면도이다.1A to 1D show semiconductor packages 101, 102, 103, and 104 according to the first, second, third, and fourth embodiments of the present invention, and FIG. 1A shows a semiconductor package 101 using a printed circuit board 20. FIGS. 1B is a cross-sectional view showing the semiconductor package 102 using the circuit film 30, and FIGS. 1C and 1D are cross-sectional views showing the semiconductor packages 103 and 104 using the lead frame 40. FIG.
먼저 상면을 향하여 다수의 입출력패드(2a)가 구비된 제1반도체칩(2)이 위치되어 있고, 상기 제1반도체칩(2)의 하면에는 역시 하면을 향하여 다수의 입출력패드(4a)가 구비된 제2반도체칩(4)이 위치되어 있다. 여기서, 상기 제1반도체칩(2)과 제2반도체칩(4)은 산화실리콘막(130)에 의해 후면이 접착되어 있는 상태이며, 이에 대한 자세한 설명은 웨이퍼 접착 방법에서 설명하기로 한다.First, the first semiconductor chip 2 having the plurality of input / output pads 2a is positioned toward the upper surface, and the plurality of the input / output pads 4a are provided on the lower surface of the first semiconductor chip 2 toward the lower surface. The second semiconductor chip 4 is located. Here, the first semiconductor chip 2 and the second semiconductor chip 4 are in a state in which the back surface is bonded by the silicon oxide film 130, which will be described in detail in the wafer bonding method.
계속해서, 상기 제2반도체칩(4)의 하면에는 회로기판이 위치되어 있는데 이는, 도1a에 도시된 바와같이 인쇄회로기판(20), 도1b에 도시된 바와 같이 써킷필름(30)을 이용하거나 또는 도1c 및 도1d에 도시된 바와 같이 다수의 리드(41)로 이루어진 리드프레임(40)을 이용할 수 있다.Subsequently, a circuit board is positioned on the bottom surface of the second semiconductor chip 4, which is a printed circuit board 20 as shown in FIG. 1A and a circuit film 30 as shown in FIG. 1B. Alternatively, as shown in FIGS. 1C and 1D, a lead frame 40 including a plurality of leads 41 may be used.
도1a와 같이, 상기 회로기판으로서 인쇄회로기판(20)을 이용했을 경우에는, 주지된 바와 같이 딱딱한 재질의 열경화성 수지층(21)을 중심으로 상면에는 다수의본드핑거(22)가 형성되어 있고, 하면에는 다수의 볼랜드(23)가 어레이되어 있으며, 또한 상기 본드핑거(22)와 볼랜드(23)는 도전성비아홀(24)에 의해 상호 연결되어 이루어져 있다. 물론, 수지층(21)의 상,하면은 커버코트(25)로 코팅되어 있되, 상기 비아홀(24) 및 볼랜드(23)는 외부로 오픈되어 있다.As shown in FIG. 1A, when the printed circuit board 20 is used as the circuit board, as is well known, a plurality of bond fingers 22 are formed on the upper surface of the thermosetting resin layer 21 of a hard material. In the lower surface, a plurality of ball lands 23 are arrayed, and the bond fingers 22 and the ball lands 23 are connected to each other by conductive via holes 24. Of course, the upper and lower surfaces of the resin layer 21 are coated with a cover coat 25, but the via holes 24 and the borland 23 are open to the outside.
다음으로 도1b에 도시된 바와 같이, 가요성 써킷필름(30)(또는 써킷테이프)인 경우에는 필름(31)을 중심으로 상면에는 본드핑거(32)가 형성되어 있고, 하면에는 볼랜드(33)가 형성되어 이루어져 있다. 마찬가지로 상기 본드핑거(32) 및 볼랜드(33)는 모두 오픈되어 있다.Next, as illustrated in FIG. 1B, in the case of the flexible circuit film 30 (or the circuit tape), a bond finger 32 is formed on the upper surface of the film 31, and the borland 33 is disposed on the lower surface of the flexible circuit film 30. Is formed. Likewise, the bond finger 32 and the borland 33 are both open.
한편, 도1c 및 도1d와 같이 리드프레임(40)을 이용했을 경우에는, 다수의 리드(41)를 중심으로 그 상면에는 본드핑거(42)가 형성되어 있고, 하면에는 랜드(43)가 형성되어 이루어져 있다. 상기 리드프레임은 상기 제1,2실시예와 다르게 어떠한 수지층이나 필름 또는 테이프를 포함하지 않으며, 오직 금속성 리드로만 구성되어 있음은 주지의 사실이다.On the other hand, when the lead frame 40 is used as shown in FIGS. 1C and 1D, a bond finger 42 is formed on the upper surface of the lead 41 and a land 43 is formed on the lower surface thereof. It consists of It is well known that the lead frame does not include any resin layer, film or tape unlike the first and second embodiments, and consists only of a metallic lead.
한편, 상기 리드(41)는 부분에칭 기술에 의해 형성된 것이며, 상기 랜드(43) 영역의 두께는 다른 리드(41) 영역 두께보다 두껍게 형성되어 있다. 또한, 상기 부분에칭 기술외에 기계적 스탬핑 기술에 의해 리드(41)를 일정 방향으로 절곡시켜 구성할 수도 있으며, 이를 한정하는 것은 아니다.On the other hand, the lead 41 is formed by a partial etching technique, the thickness of the land 43 region is formed thicker than the thickness of the other lead 41 region. In addition, the lead 41 may be bent in a predetermined direction by a mechanical stamping technique in addition to the partial etching technique, but is not limited thereto.
계속해서, 상기 제1반도체칩(2) 및 제2반도체칩(4)의 각 입출력패드(2a,4a)는 접속수단에 의해 인쇄회로기판(20), 써킷필름(30) 또는 리드프레임(40)의 본드핑거(22,32,42)에 상호 전기적으로 접속되어 있다.Subsequently, each of the input / output pads 2a and 4a of the first semiconductor chip 2 and the second semiconductor chip 4 is connected to the printed circuit board 20, the circuit film 30, or the lead frame 40 by connecting means. Are electrically connected to the bond fingers 22, 32, and 42.
상기 제1반도체칩(2)과 본드핑거(22,32,42)를 접속하는 수단은 골드와이어나 알루미늄와이어와 같은 도전성와이어(50)를 이용함이 바람직하며, 상기 제2반도체칩(4)과 본드핑거(22,32,42)를 접속하는 수단은 골드 또는 솔더등과 같은 도전성범프(60)를 이용함이 바람직하다.As the means for connecting the first semiconductor chip 2 and the bond fingers 22, 32, and 42, a conductive wire 50 such as a gold wire or an aluminum wire is preferably used, and the second semiconductor chip 4 The means for connecting the bond fingers 22, 32, 42 preferably uses a conductive bump 60 such as gold or solder.
이어서, 상기 인쇄회로기판(20), 써킷필름(30) 상의 제1반도체칩(2), 제2반도체칩(4), 접속수단 등은 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재(70)로 원사이드 몰딩되어 외부 환경으로부터 보호될 수 있도록 되어 있다.Subsequently, the first semiconductor chip 2, the second semiconductor chip 4, and the connecting means on the printed circuit board 20, the circuit film 30, and the like are encapsulated materials 70, such as an epoxy molding compound or a liquid encapsulant. It is molded in one side to protect from the external environment.
여기서, 다수의 리드(41)로 이루어진 리드프레임(40)을 이용했을 경우에는 도1c 및 도1d에 도시된 바와 같이, 상기 봉지재(70)가 리드(41)의 랜드(43)가 외부로 노출 또는 돌출되도록 봉지되어 있음으로써, 상기 랜드(43)를 마더보드와 직접 접촉하는 입출력 단자로 이용할 수도 있다.In this case, when the lead frame 40 including the plurality of leads 41 is used, as shown in FIGS. 1C and 1D, the encapsulant 70 moves the land 43 of the lead 41 to the outside. By being sealed so as to be exposed or protruding, the land 43 can also be used as an input / output terminal in direct contact with the motherboard.
계속해서, 인쇄회로기판(20)이나 써킷필름(30)인 경우에는 그 볼랜드(23,33)에 솔더볼과 같은 도전성볼(80)을 융착하여 마더보드에 표면 실장이 가능한 형태로 함이 바람직하다.Subsequently, in the case of the printed circuit board 20 or the circuit film 30, it is preferable that the conductive lands 80 such as solder balls are fused to the ball lands 23 and 33 to form a surface mountable on the motherboard. .
또한, 도1d에 도시된 바와 같이 리드(41)의 랜드(43) 저면에도 솔더볼과 같은 도전성볼(80)을 융착하여 사용할 수 있지만 이것으로 한정하는 것은 아니며, 상기 랜드(43)의 표면에는 단순히 솔더를 플레이팅(도시되지 않음)하여 입출력 단자로 사용할 수도 있다.Also, as shown in FIG. 1D, conductive balls 80 such as solder balls may be fused to the bottom of the land 43 of the lead 41, but the present invention is not limited thereto. The solder may be plated (not shown) and used as an input / output terminal.
한편, 도2는 본 발명의 제5실시예에 의한 반도체패키지(105)를 도시한 단면도이며, 이는 본 발명의 제1실시예와 유사하므로 그 차이점만을 설명한다.2 is a cross-sectional view showing a semiconductor package 105 according to a fifth embodiment of the present invention, which is similar to the first embodiment of the present invention, and thus only explains the differences.
도시된 바와 같이 제1반도체칩(2)과 제2반도체칩(4)의 접착 수단으로서는 제1실시예와 달리 양면접착테이프 또는 UV테이프와 같은 접착테이프(140)가 이용되었다. 즉, 제1~4실시예에서는 산화실리콘막(130)이 접착수단으로 사용되었지만, 제5실시예에서는 양면접착테이프(140) 또는 UV테이프(140)가 사용된 것이다. 마찬가지로 이러한 접착테이프(140)를 사용한 구조는 도1a 내지 도1d에 도시된 모든 반도체패키지(101,102,103,104)에 적용 가능하며, 이를 한정하는 것은 아니다.As shown in the drawing, unlike the first embodiment, an adhesive tape 140 such as a double-sided adhesive tape or a UV tape was used as the bonding means of the first semiconductor chip 2 and the second semiconductor chip 4. That is, in the first to fourth embodiments, the silicon oxide film 130 is used as the bonding means, but in the fifth embodiment, the double-sided adhesive tape 140 or the UV tape 140 is used. Likewise, the structure using the adhesive tape 140 may be applied to all the semiconductor packages 101, 102, 103, and 104 shown in FIGS. 1A to 1D, but is not limited thereto.
도3a 및 도3b는 본 발명에 의한 웨이퍼의 상호 접착 방법을 도시한 사시도이다.3A and 3B are perspective views showing the method of mutual bonding of wafers according to the present invention.
도시된 바와 같이 먼저 상면에 다수의 반도체칩(2)이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩 상면에는 다수의 입출력패드(2a,4a)가 구비된 제1웨이퍼(110)를 제공한다.As shown, first, a plurality of semiconductor chips 2 are formed on a top surface in a substantially checkered shape, and a first wafer 110 having a plurality of input / output pads 2a and 4a is provided on each top surface of each semiconductor chip. .
또한, 하면에 다수의 반도체칩(4)이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩(4)의 하면에는 다수의 입출력패드(4a)가 형성되어 있고, 그 입출력패드(4a)에는 골드 또는 솔더와 같은 도전성범프(60)가 형성되어 있는 제2웨이퍼(120)를 제공한다.In addition, a plurality of semiconductor chips 4 are formed in a substantially checkerboard shape on the lower surface, and a plurality of input / output pads 4a are formed on the lower surface of each semiconductor chip 4, and gold is formed on the input / output pads 4a. Alternatively, a second wafer 120 having conductive bumps 60 such as solder formed thereon is provided.
이어서, 상기 제2웨이퍼(120)의 후면(도면상에서는 제2웨이퍼(120) 상면이 됨)에 물(H) 몇 방울을 떨어뜨린 후 상기 제2웨이퍼(120)를 고속으로 회전시키면 상기 물은 매우 얇은 두께로 상기 제2웨이퍼(120)의 후면 전체에 분포된다.Subsequently, a few drops of water (H) are dropped on the rear surface of the second wafer 120 (which is the upper surface of the second wafer 120 in the drawing), and then the water is rotated by rotating the second wafer 120 at high speed. It is distributed in the entire rear surface of the second wafer 120 in a very thin thickness.
이어서, 상기 제2웨이퍼(120)의 후면에 제1웨이퍼(110)의 후면을 상호 부착시킨다. 이 상태에서도 상기 제1웨이퍼(110)와 제2웨이퍼(120)는 물의 표면 장력으로 인해 서로 이탈되지 않는다.Subsequently, the rear surfaces of the first wafers 110 are attached to the rear surfaces of the second wafers 120. Even in this state, the first wafer 110 and the second wafer 120 are not separated from each other due to the surface tension of water.
계속해서, 상기 자재를 대략 50~150℃의 온도로 가열하게 되면, 상기 물 또는 수분이 증발하면서, 상기 수분내의 산소가 웨이퍼의 주재료인 실리콘과 결합함으로써 일정두께(수μm)의 산화실리콘막(130)을 형성하게 된다. 즉, 제1웨이퍼(110) 및 제2웨이퍼(120) 후면에 동시에 산화실리콘막(130)이 형성되면서 결국은 제1웨이퍼(110) 및 제2웨이퍼(120)가 상호 접착되는 것이다. 여기서, 통상의 웨이퍼 취급 공정은 대략 100℃ 내외에서 진행되므로, 상기 50∼150℃의 온도 제공을 별도로 할 필요는 없다.Subsequently, when the material is heated to a temperature of approximately 50 to 150 ° C., the silicon oxide film of a certain thickness (several μm) is formed by combining oxygen in the water with silicon, which is the main material of the wafer, while the water or water evaporates. 130). That is, as the silicon oxide film 130 is simultaneously formed on the back surface of the first wafer 110 and the second wafer 120, the first wafer 110 and the second wafer 120 are eventually bonded to each other. Here, since the normal wafer handling process proceeds at about 100 ° C, it is not necessary to separately provide the temperature of 50 to 150 ° C.
또한, 여기서 상기 제1웨이퍼(110) 및 제2웨이퍼(120) 사이에는 어떠한 물질의 개재없이 그 2장의 웨이퍼를 직접 부착한 후 고온 예를 들면 50~250℃ 범위의 온도를 제공함으로써 2장의 웨이퍼를 직접 접착시킬 수도 있다. 상기와 같은 방법은 2장의 웨이퍼를 부착한 상태에서 고온을 제공하게 되면, 그 사이의 산소(O2)가 실리콘과 결합하면서 자연스럽게 2장의 웨이퍼 사이에 산화실리콘막이 형성되기 때문에 가능하다. 상기 산화실리콘막은 2장의 웨이퍼를 상호 접착시키는 역할을 하며 이러한 방법은 후면을 그라인딩한 웨이퍼들에 특히 유용하다.In addition, the two wafers may be directly attached between the first wafer 110 and the second wafer 120 without any material, and then provided with a high temperature, for example, in the range of 50 to 250 ° C. Can also be directly bonded. The above method is possible because the silicon oxide film is naturally formed between the two wafers while oxygen (O 2 ) is bonded to the silicon when the high temperature is provided while the two wafers are attached. The silicon oxide film serves to bond two wafers together, and this method is particularly useful for wafers ground at the back side.
상기와 같이 상호 접착된 제1웨이퍼(110) 및 제2웨이퍼(120)는 블레이드(Blade)에 의해 낱개의 반도체칩(2,4)으로 소잉되고, 이 소잉된 제1반도체칩(2) 및 제2반도체칩(4)이 본 발명의 제1실시예 내지 제4실시예에 의한 반도체패키지에 제공된 것이다.The first and second wafers 110 and 120 bonded to each other as described above are sawed into the individual semiconductor chips 2 and 4 by blades, and the sawed first semiconductor chips 2 and The second semiconductor chip 4 is provided in the semiconductor package according to the first to fourth embodiments of the present invention.
한편, 상기 방법 외에 도4a 및 도4b에 도시된 방법을 이용할 수도 있다.In addition to the above method, the method shown in Figs. 4A and 4B may be used.
상면에 다수의 반도체칩(2)이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩(2) 상면에는 다수의 입출력패드(2a)가 구비된 제1웨이퍼(110)를 제공한다.A plurality of semiconductor chips 2 are formed on a top surface in a substantially checkerboard shape, and a first wafer 110 having a plurality of input / output pads 2a is provided on each top surface of each semiconductor chip 2.
또한, 하면에 다수의 반도체칩(4)이 대략 바둑판 모양으로 형성되어 있으며, 상기 각 반도체칩(4)의 하면에는 다수의 입출력패드(4a)가 형성되어 있고, 그 입출력패드(4a)에는 골드 또는 솔더와 같은 도전성범프(60)가 형성되어 있는 제2웨이퍼(120)를 제공한다.In addition, a plurality of semiconductor chips 4 are formed in a substantially checkerboard shape on the lower surface, and a plurality of input / output pads 4a are formed on the lower surface of each semiconductor chip 4, and gold is formed on the input / output pads 4a. Alternatively, a second wafer 120 having conductive bumps 60 such as solder formed thereon is provided.
이어서, 상기 제1웨이퍼(110) 또는 제2웨이퍼(120)의 후면에 양면접착테이프(140) 또는 UV테이프(140)를 개재하여 상호 접착시킴으로써 2개의 웨이퍼를 상호 접착시킨다. 이때, 약간의 열과 압력을 가하여 상기 접착 작용이 보다 신속하고 효과적으로 진행되도록 함이 바람직하다.Subsequently, the two wafers are bonded to each other by mutually bonding the double-sided adhesive tape 140 or the UV tape 140 to the rear surface of the first wafer 110 or the second wafer 120. At this time, it is preferable to apply a little heat and pressure to allow the adhesion to proceed more quickly and effectively.
여기서, 상기 양면접착테이프는 소잉 공정시 약간의 바운싱(Bouncing)이 발생됨으로써 UV테이프를 이용함이 바람직하지만 이것으로 한정하는 것은 아니다.Here, the double-sided adhesive tape is preferably used in the sawing process a little bouncing (Bouncing) by using a UV tape, but is not limited to this.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
이와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 두 개의 반도체칩을 적층한 채 인쇄회로기판, 써킷필름 또는 리드의 상면에 탑재함으로써 고기능화, 고용량화한 반도체패키지를 얻을 수 있는 효과가 있다.As described above, according to the semiconductor package according to the present invention, the semiconductor package with high functionality and high capacity can be obtained by mounting two semiconductor chips on the upper surface of a printed circuit board, a circuit film or a lead.
또한, 상기 반도체패키지에서 각 반도체칩의 접속수단으로 일측 반도체칩은 도전성범프를 이용하고 타측 반도체칩은 도전성와이어를 이용함으로써, 서로 대향되어 위치된 반도체칩의 입출력패드를 본드핑거에 모두 용이하게 연결할 수 있는 효과가 있다.Further, in the semiconductor package, one semiconductor chip uses conductive bumps and the other semiconductor chip uses conductive wires as a means for connecting each semiconductor chip, thereby easily connecting all of the input / output pads of the semiconductor chips facing each other to the bond fingers. It can be effective.
또한 본 발명에 의한 웨이퍼의 상호 접착 방법에 의하면, 2장의 웨이퍼 후면 사이에 수분(또는 양면접착테이프나 UV테이프)을 제공하고 이를 소정 온도로 가열함으로써 2장의 웨이퍼를 간단히 접착시킬 수 있어, 별도의 복잡한 설비를 필요로 하지 않는 효과가 있다.In addition, according to the method of mutual bonding of wafers according to the present invention, two wafers can be easily bonded by providing water (or double-sided adhesive tape or UV tape) between two wafer backsides and heating them to a predetermined temperature. It does not require complicated equipment.
Claims (13)
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| KR100475313B1 (en) * | 2002-07-04 | 2005-03-10 | 에스티에스반도체통신 주식회사 | Method for manufacturing a stacked double chip semiconductor package using a adhesive tape |
| KR100888335B1 (en) * | 2007-08-14 | 2009-03-12 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and fabricating?method?thereof |
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| JPS61288456A (en) * | 1985-06-17 | 1986-12-18 | Fujitsu Ltd | Manufacture of multilayer semiconductor device |
| JPH0883881A (en) * | 1993-06-21 | 1996-03-26 | Internatl Business Mach Corp <Ibm> | Lamination type semiconductor chip structure and its manufacture |
| US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
| JP2000299432A (en) * | 1999-04-15 | 2000-10-24 | Rohm Co Ltd | Manufacture of semiconductor device |
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