KR100337460B1 - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- KR100337460B1 KR100337460B1 KR1019980046572A KR19980046572A KR100337460B1 KR 100337460 B1 KR100337460 B1 KR 100337460B1 KR 1019980046572 A KR1019980046572 A KR 1019980046572A KR 19980046572 A KR19980046572 A KR 19980046572A KR 100337460 B1 KR100337460 B1 KR 100337460B1
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- South Korea
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- semiconductor chip
- circuit board
- input
- board sheet
- polyimide layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 장치에 관한 것으로, 최종 입출력단자인 솔더볼이 반도체칩상의 외주연에도 위치하는 팬아웃형 반도체 장치에서 반도체칩의 작동중 발생하는 열을 외부로 신속히 방출시키기 위해, 상면에 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 상부에 그 반도체칩의 상면 넓이보다 넓은 폴리이미드층이 접착제로 접착되어 있고, 상기 폴리이미드층 상면에는 구리 재질의 본드핑거, 연결부 및 솔더볼랜드의 회로패턴이 형성되어 있으며, 상기 본드핑거 및 솔더볼랜드를 제외한 폴리이미드층 상부에는 커버코오트가 코팅되어 있되, 상기 반도체칩의 입출력패드와 대응되는 영역에는 소정의 관통부가 형성되어 있는 회로기판시트와; 상기 반도체칩의 입출력패드 및 회로기판시트의 본드핑거를 전기적으로 연결하는 도전성와이어와; 상기 반도체칩의 저면에 부착되어 반도체칩의 작동중 발생하는 열을 공기중으로 방출하는 히트스프레더와; 상기 관통부 내측의 도전성와이어 및 반도체칩의 입출력패드를 외부 환경으로부터 보호하기 위해 상기 관통부 내측에 충진되고, 또한 반도체칩 및 히트스프레더의 측부와 회로기판시트의 저면 사이를 감싸는 봉지재와; 상기 회로기판시트의 솔더볼랜드에 융착되어 차후 마더보드에 실장되는 솔더볼을 포함하여 이루어진 반도체 장치.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. In a fan-out semiconductor device in which a solder ball, which is a final input / output terminal, is also located on an outer circumference of a semiconductor chip, an input / output pad is disposed on an upper surface thereof to quickly release heat generated during operation of the semiconductor chip. A formed semiconductor chip; The polyimide layer, which is wider than the upper surface area of the semiconductor chip, is bonded to the upper portion of the semiconductor chip with an adhesive, and the upper surface of the polyimide layer is formed with a copper bond finger, a connection part, and a circuit pattern of solder borland. A circuit board sheet having a cover coat coated on an upper portion of the polyimide layer except for fingers and solder balls, wherein a predetermined through portion is formed in a region corresponding to the input / output pad of the semiconductor chip; Conductive wires electrically connecting the input / output pads of the semiconductor chip and the bond fingers of the circuit board sheets; A heat spreader attached to a bottom surface of the semiconductor chip and dissipating heat generated during operation of the semiconductor chip into air; An encapsulant which is filled inside the through part to protect the conductive wire inside the through part and the input / output pad of the semiconductor chip from the external environment, and surrounds the side of the semiconductor chip and the heat spreader and the bottom of the circuit board sheet; And a solder ball fused to the solder ball lands of the circuit board sheet and subsequently mounted on the motherboard.
Description
본 발명은 반도체 장치에 관한 것으로, 보다 상세하게 설명하면 최종 입출력단자인 솔더볼이 반도체칩상의 외주연에도 위치하는 팬아웃형 반도체 장치에서 반도체칩의 작동중 발생하는 열을 외부로 신속히 방출시킬 수 있는 반도체 장치에 관한 것이다.The present invention relates to a semiconductor device. More specifically, in a fan-out semiconductor device in which a solder ball, which is a final input / output terminal, is also located on an outer circumference of a semiconductor chip, heat generated during operation of the semiconductor chip can be quickly released to the outside. A semiconductor device.
최근의 반도체 장치는 반도체칩의 경박단소화 추세에 따라 그 반도체칩을 마더보드(Mother board)상에 지지시켜 주는 동시에 입출력신호를 매개해주는 반도체 장치의 크기도 반도체칩의 크기와 유사한 칩싸이즈(Chip size) 반도체 장치의 형태로 전환되고 있다.In recent years, semiconductor devices which support the semiconductor chip on the motherboard and mediate input / output signals according to the trend of light and small size of semiconductor chip have similar chip size to that of the semiconductor chip. size) in the form of semiconductor devices.
이러한 칩싸이즈 반도체 장치의 한 예를 도1에 도시하였으며, 이것의 구조를 간단히 설명하면 다음과 같다.An example of such a chip size semiconductor device is shown in FIG. 1, and the structure thereof is briefly described as follows.
도1은 유연성 회로기판시트를 이용한 칩싸이즈반도체 장치(100')로서, 상면의 둘레에 다수의 입출력패드(41')가 구비된 반도체칩(40')과, 상기 반도체칩(40')의 입출력패드(41') 내측면에 접착된 접착제(21')와, 상기 접착제(21') 상면에 폴리이미드층(12')이 접착되고, 상기 폴리이미드층(12')상에는 본드핑거(13'), 연결부(14') 및 솔더볼랜드(15') 등의 도전성 회로패턴이 형성되어 있으며, 상기 본드핑거(13') 및 솔더볼랜드(15')를 제외한 상면에 코팅된 커버코오트(16')로 이루어진 회로기판시트(10')와, 상기 반도체칩(40')의 입출력패드(41')와 회로기판시트(10')의 본드핑거(13')를 연결하는 도전성와이어(50')와, 상기 회로기판시트(10')의 솔더볼랜드(15')에 융착되어 마더보드(도시되지 않음)에 실장되는 솔더볼(70')과, 상기 반도체칩(40')의 입출력패드(41')에 연결된 도전성와이어(50')를 외부의 환경으로부터 보호하기 위해 봉지한 봉지재(60')로 이루어져 있다.Fig. 1 shows a chip size semiconductor device 100 'using a flexible circuit board sheet, comprising a semiconductor chip 40' having a plurality of input / output pads 41 'around an upper surface thereof, and the semiconductor chip 40'. An adhesive 21 'adhered to an inner surface of the input / output pad 41' and a polyimide layer 12 'are adhered to the upper surface of the adhesive 21', and a bond finger 13 is formed on the polyimide layer 12 '. '), The connection portion 14' and the conductive circuit patterns such as the solder borland 15 'is formed, and the cover coat 16 coated on the upper surface except for the bond finger 13' and the solder borland 15 ' A conductive wire 50 'which connects the circuit board sheet 10' formed of the "), the input / output pad 41 'of the semiconductor chip 40' and the bond finger 13 'of the circuit board sheet 10'. ), A solder ball 70 'fused to the solder ball land 15' of the circuit board sheet 10 'and mounted on a motherboard (not shown), and an input / output pad 41 of the semiconductor chip 40'. Conductivity connected to It consists ear (50 ') in the encapsulation material (60 a bag to be protected from the external environment ").
이러한 칩싸이즈 반도체 장치(100')의 제조 방법은 웨이퍼 상태에서 회로기판시트를 웨이퍼 모양과 동일한 상태로 접착제를 개재하여 접착시키는 라미네이션(Lamination) 단계와, 상기 단계를 완료한 웨이퍼에 도전성와이어를 연결시켜 주는 와이어본딩 단계와, 와이어본딩된 부분을 보호하기 위해 봉지재로 봉지하는 봉지 단계와, 입출력패드를 외부로 연결시켜 주기 위하여 웨이퍼에 붙어 있는 회로기판시트의 상면에 솔더볼을 융착하는 솔더볼 융착 단계와, 낱개의 반도체 장치로 분리시켜주는 소잉 단계로 이루어져 있다.In the method for manufacturing the chip size semiconductor device 100 ', a lamination step of adhering the circuit board sheet to the same state as the shape of the wafer through an adhesive in a wafer state, and connecting conductive wires to the wafer having completed the above steps A wire bonding step for encapsulating, an encapsulation step for encapsulating the wire-bonded part, and a solder ball fusion step for fusion of solder balls on the upper surface of the circuit board sheet attached to the wafer to connect the input / output pad to the outside. And a sawing step of separating the semiconductor into individual semiconductor devices.
그러나 최근에는 반도체칩의 집적 기술 발달로 반도체칩 상에 형성되는 입출력패드가 증가하는 추세에 있다. 따라서 반도체 장치에 형성되는 솔더볼의 갯수도 증가 추세에 있으나, 상기와 같은 칩싸이즈 반도체 장치의 회로기판시트에 형성 및 융착될 수 있는 솔더볼의 갯수에는 한계가 있다.Recently, however, input / output pads formed on semiconductor chips have increased due to the development of integrated technology of semiconductor chips. Therefore, although the number of solder balls formed in the semiconductor device is increasing, there is a limit in the number of solder balls that can be formed and fused to the circuit board sheet of the chip size semiconductor device as described above.
한편, 상기 반도체 장치의 회로기판시트 넓이를 반도체칩의 상면 넓이보다 크게 할 경우에는 상기 회로기판시트가 유연하기 때문에 그 외곽면이 쉽게 휘는 단점이 있으며, 또한 반도체칩의 외주연에 위치된 회로기판시트에 솔더볼이 융착될 경우 이 솔더볼을 회로기판시트가 확고하게 지지시켜 주지 못하는 문제점이 있다.On the other hand, when the width of the circuit board sheet of the semiconductor device is larger than the width of the upper surface of the semiconductor chip, the circuit board sheet is flexible, so that its outer surface is easily bent, and the circuit board is located on the outer circumference of the semiconductor chip. When solder balls are fused to the sheet, there is a problem in that the circuit board sheet does not support the solder balls firmly.
또한 최근에는 반도체칩의 집적도 및 동작 주파수가 커짐으로써 반도체칩으로부터 대량의 열이 발생하지만 이와 같은 열을 외부로 흡수하여 방출시킬 수 있는 구조가 개시되어 있지 않음으로써 반도체 장치의 전기적 성능을 저하시킴은 물론 반도체 장치의 오동작을 유발하고 있다.In addition, in recent years, a large amount of heat is generated from a semiconductor chip due to an increase in the degree of integration and operating frequency of the semiconductor chip. Of course, the semiconductor device is malfunctioning.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 발명한 것으로, 반도체칩상의 외주연에도 솔더볼을 위치시켜 종래보다 많은 수의 솔더볼을 확보하는데 있다.The present invention has been invented to solve the above-mentioned conventional problems, and it is possible to secure a larger number of solder balls by placing solder balls on the outer periphery of the semiconductor chip.
본 발명의 다른 목적은 별도의 보강제 부착없이도 회로기판시트의 휨 현상을 방지함은 물론 그 상부에 융착된 솔더볼을 확고하게 지지할 수 있는 반도체 장치를 제공하는데 있다.Another object of the present invention is to provide a semiconductor device capable of firmly supporting a solder ball fused to an upper portion as well as preventing warpage of a circuit board sheet without a separate reinforcing agent.
본 발명의 또다른 목적은 반도체칩의 열을 외부로 신속하게 방출함으로써 반도체칩의 전기적 성능을 전혀 저하시키지 않음은 물론 반도체칩의 오동작을 억제하는데 있다.Another object of the present invention is to quickly release heat of the semiconductor chip to the outside, not to deteriorate the electrical performance of the semiconductor chip at all, and to suppress the malfunction of the semiconductor chip.
도1은 종래의 반도체 장치를 도시한 부분 절개 사시도이다.1 is a partially cutaway perspective view showing a conventional semiconductor device.
도2a 및 도2b는 본 발명에 의한 반도체 장치의 한 실시예를 도시한 단면도이다.2A and 2B are cross-sectional views showing one embodiment of a semiconductor device according to the present invention.
도3a 및 도3b는 본 발명에 의한 반도체 장치의 다른 실시예를 도시한 단면도이다.3A and 3B are sectional views showing another embodiment of the semiconductor device according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100,101,102,103 ; 본 발명에 의한 반도체 장치100,101,102,103; Semiconductor device according to the present invention
100' ; 종래의 반도체 장치 10 ; 회로기판시트100 '; A conventional semiconductor device 10; Circuit board sheet
12 ; 폴리이미드층(Polyimide layer) 13 ; 본드핑거(Bond finger)12; Polyimide layer 13; Bond finger
14 ; 연결부14; Connection
15 ; 솔더볼랜드(Solder ball land)15; Solder ball land
16 ; 커버코오트(Cover coat) 17 ; 관통부16; Cover coat 17; Penetration
21 ; 접착제21; glue
30 ; 히트스프레더(Heat spreader) 40 ; 반도체칩30; Heat spreader 40; Semiconductor chip
41 ; 입출력패드(Pad)41; I / O Pad
50 ; 도전성와이어(Conductive wire) 60 ; 봉지재50; Conductive wire 60; Encapsulant
70 ; 솔더볼70; Solder ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체 장치는 상면에 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 상부에 그 반도체칩의 상면 넓이보다 넓은 폴리이미드층이 접착제로 접착되어 있고, 상기 폴리이미드층 상면에는 구리 재질의 본드핑거, 연결부 및 솔더볼랜드의 회로패턴이 형성되어 있으며, 상기 본드핑거 및 솔더볼랜드를 제외한 폴리이미드층 상부에는 커버코오트가 코팅되어 있되, 상기 반도체칩의 입출력패드와 대응되는 영역에는 소정의 관통부가 형성되어 있는 회로기판시트와; 상기 반도체칩의 입출력패드 및 회로기판시트의 본드핑거를 전기적으로 연결하는 도전성와이어와; 상기 반도체칩의 저면에 부착되어 반도체칩의 작동중 발생하는 열을 공기중으로 방출하는 히트스프레더와; 상기 관통부 내측의 도전성와이어 및 반도체칩의 입출력패드를 외부 환경으로부터 보호하기 위해 상기 관통부 내측에 충진되고, 또한 반도체칩 및 히트스프레더의 측부와 회로기판시트의 저면 사이를 감싸는 봉지재와; 상기 회로기판시트의 솔더볼랜드에 융착되어 차후 마더보드에 실장되는 솔더볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor chip having an input / output pad formed on an upper surface thereof; The polyimide layer, which is wider than the upper surface area of the semiconductor chip, is bonded to the upper portion of the semiconductor chip with an adhesive, and the upper surface of the polyimide layer is formed with a copper bond finger, a connection part, and a circuit pattern of solder borland. A circuit board sheet having a cover coat coated on an upper portion of the polyimide layer except for fingers and solder balls, wherein a predetermined through portion is formed in a region corresponding to the input / output pad of the semiconductor chip; Conductive wires electrically connecting the input / output pads of the semiconductor chip and the bond fingers of the circuit board sheets; A heat spreader attached to a bottom surface of the semiconductor chip and dissipating heat generated during operation of the semiconductor chip into air; An encapsulant which is filled inside the through part to protect the conductive wire inside the through part and the input / output pad of the semiconductor chip from the external environment, and surrounds the side of the semiconductor chip and the heat spreader and the bottom of the circuit board sheet; It is characterized in that it comprises a solder ball fused to the solder ball land of the circuit board sheet is mounted on the motherboard later.
이와 같이 하여 본 발명에 의한 반도체 장치는 별도의 보강제없이 반도체칩 및 히트스프레더 측부와 회로기판시트의 저면을 봉지재가 감싸고 있음으로써 회로기판시트를 상기 봉지재가 지지하여 회로기판시트의 휨 현상을 방지함은 물론 그 상면에 융착된 솔더볼을 확고하게 지지하게 된다.In this way, the semiconductor device according to the present invention encapsulates the semiconductor chip and the heat spreader side and the bottom surface of the circuit board sheet without any reinforcing agent so that the encapsulant supports the circuit board sheet to prevent bending of the circuit board sheet. Of course, the solder ball fused to the upper surface is firmly supported.
또한 최근의 반도체칩은 집적도 및 동작 주파수가 커짐으로써 대량의 열이 발생하여도 상기 반도체칩의 저면에 부착된 히트스프레더로 인해 그 열이 외부로 신속히 방출되어 반도체칩의 전기적 성능을 저하시키지 않게 되고, 더불어 그 반도체칩의 오동작을 억제하게 된다.In addition, the recent increase in the degree of integration and operating frequency of the semiconductor chip, even if a large amount of heat is generated by the heat spreader attached to the bottom of the semiconductor chip is quickly released to the outside does not degrade the electrical performance of the semiconductor chip In addition, malfunction of the semiconductor chip is suppressed.
이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부 도면을 참조하여 상세하게 설명하면 다음과 같다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.
도2a 및 도2b는 본 발명에 의한 반도체 장치(100,101)의 한 실시예를 도시한 단면도이고, 도3a 및 도3b는 본 발명에 의한 반도체 장치(102,103)의 다른 실시예를 도시한 단면도로서 도2a 및 도2b를 중심으로 본 발명에 의한 반도체 장치의 구성 및 작용을 설명한다.2A and 2B are cross-sectional views showing one embodiment of semiconductor devices 100 and 101 according to the present invention, and FIGS. 3A and 3B are cross-sectional views showing another embodiment of semiconductor devices 102 and 103 according to the present invention. The structure and operation of the semiconductor device according to the present invention will be described with reference to 2a and 2b.
도시된 바와 같이 상면의 가장자리에 입출력패드(41)가 형성된 반도체칩(40)이 위치되어 있다. 상기 반도체칩(40)의 상면에는 접착제(21)가 개재된채 회로기판시트(10)가 접착되어 있으며 이를 좀더 상세히 설명하면 다음과 같다.As shown in the drawing, the semiconductor chip 40 having the input / output pad 41 formed on the top edge thereof is positioned. The circuit board sheet 10 is bonded to the top surface of the semiconductor chip 40 with the adhesive 21 interposed therebetween.
상기 회로기판시트(10)는 상기 반도체칩(40)의 상면 넓이보다 넓게 상기 접착제(21)와 접착되는 폴리이미드층(12)이 위치되어 있고, 상기 폴리이미드층(12)상에는 구리(Cu) 재질의 본드핑거(13), 연결부(14) 및 솔더볼랜드(15) 등의 회로패턴이 형성되어 있다. 물론 상기 본드핑거(13)에는 차후 도전성와이어(50)와의 양호한 본딩을 위해 은(Ag)이 도금되어 있고, 상기 솔더볼랜드(15)에는 차후 솔더볼(70)의 양호한 융착을 위해 금(Au) 및 니켈(Ni)이 도금되어 있다. 또한 상기 폴리이미드층(12)상의 본드핑거(13) 및 솔더볼랜드(15)를 제외한 상면 전체는 절연성의 커버코오트(16)로 코팅되어 회로기판시트(10)가 외부의 먼지, 습기 및 기계적 접촉 등으로부터 보호될 수 있도록 되어 있다. 한편, 상기 회로기판시트(10)에는 반도체칩(40)의 입출력패드(41)와 대응되는 영역에 소정의 관통부(17)가 펀칭(Punching), 에칭(Etching), 레이저(Laser) 등의 수단에 의해 형성되어 있다.The circuit board sheet 10 has a polyimide layer 12 bonded to the adhesive 21 wider than the top surface of the semiconductor chip 40, and copper (Cu) on the polyimide layer 12 Circuit patterns such as a bond finger 13, a connecting portion 14, and a solder ball land 15 are formed of a material. Of course, the bond finger 13 is plated with silver (Ag) for good bonding with the conductive wire 50 later, and the solder ball 15 has gold (Au) and for good fusion of the solder ball 70 later. Nickel (Ni) is plated. In addition, the entire upper surface of the polyimide layer 12 except for the bond finger 13 and the solder borland 15 is coated with an insulating cover coat 16 so that the circuit board sheet 10 is free of dust, moisture, and mechanical properties. It can be protected from contact. In the circuit board sheet 10, a predetermined through portion 17 is formed in a region corresponding to the input / output pad 41 of the semiconductor chip 40 such as punching, etching, and laser. It is formed by a means.
다음으로 상기 반도체칩(40)의 입출력패드(41)와 회로기판시트(10)의 본드핑거(13)는 도전성와이어(50) 즉, 골드와이어(Au wire)나 알루미늄와이어(Al wire)에 의해 전기적으로 연결되어 있다.Next, the input / output pad 41 of the semiconductor chip 40 and the bond finger 13 of the circuit board sheet 10 may be formed of a conductive wire 50, that is, a gold wire or an aluminum wire. It is electrically connected.
또한, 상기 반도체칩(40)의 저면에는 반도체칩(40)의 작동중 발생하는 열을 외부의 공기중으로 신속히 방출하기 위해 열도전성이 우수한, 예를 들면 구리(Cu)나 알루미늄(Al)으로 제조된 히트스프레더(30)가 부착되어 있다. 상기 히트스프레더(30)는 적어도 반도체칩(40)의 저면 넓이보다 넓게 형성하는 것이 바람직하며 이후 설명할 봉지재(60) 영역보다 하부로 더 돌출되도록 하는 것이 열방출 측면에서 바람직하다.In addition, the bottom surface of the semiconductor chip 40 is made of, for example, copper (Cu) or aluminum (Al) having excellent thermal conductivity in order to quickly release heat generated during operation of the semiconductor chip 40 to the outside air. The attached heat spreader 30 is attached. The heat spreader 30 is preferably formed to be at least wider than the bottom surface of the semiconductor chip 40, and it is preferable in terms of heat dissipation to protrude further below the area of the encapsulant 60 to be described later.
다음으로 상기 관통부(17) 내측의 도전성와이어(50) 및 반도체칩(40)의 입출력패드(41)를 외부 환경으로부터 보호하기 위해 상기 관통부(17) 내측에 봉지재(60) 바람직하기로는 액상 봉지재(Glop top)가 충진되어 있다. 또한 상기 반도체칩(40) 및 히트스프레더(30)의 측부와 회로기판시트(10)의 저면을 봉지재(60) 바람직하기로는 에폭시 몰딩 컴파운드(Epoxy molding compound)가 감싸고 있음으로써 회로기판시트(10)를 지지하여 회로기판시트(10)의 휨 현상을 억제한다.Next, in order to protect the conductive wire 50 inside the through part 17 and the input / output pad 41 of the semiconductor chip 40 from the external environment, the encapsulant 60 inside the through part 17 is preferable. The liquid top (Glop top) is filled. In addition, the side surface of the semiconductor chip 40 and the heat spreader 30 and the bottom surface of the circuit board sheet 10 are encapsulated by the encapsulant 60, preferably an epoxy molding compound, so that the circuit board sheet 10 may be covered. ) To suppress warpage of the circuit board sheet 10.
마지막으로 상기 회로기판시트(10)의 솔더볼랜드(15)에는 차후 마더보드(Mother board, 도시되지 않음)에 실장되어 반도체칩(40)의 신호 또는 마더보드의 신호를 매개하는 솔더볼(70)이 융착되어 있다. 상기 솔더볼(70)은 바람직하기로 회로기판(10)의 솔더볼랜드(15)에 안착시킨 후 고온의 퍼니스(Furnace)에서 재용융시킴으로써 융착 작업을 진행한다.Lastly, the solder ball land 15 of the circuit board sheet 10 is mounted on a mother board (not shown) to be solder ball 70 which mediates a signal of the semiconductor chip 40 or a signal of the motherboard. It is fused. Preferably, the solder ball 70 is seated on the solder ball land 15 of the circuit board 10 and then fusion is performed by remelting in a high temperature furnace.
여기서 도2b에 도시된 반도체 장치는 스트립(Strip) 단위로 반도체칩(40)의 측부 및 회로기판시트(10)의 저면에 봉지재(60)를 봉지한 후 회로기판시트(10) 및 봉지재(60)를 동시에 소잉(Sawing)함으로써 제조된 반도체 장치이다.In the semiconductor device illustrated in FIG. 2B, the encapsulant 60 is encapsulated on the side of the semiconductor chip 40 and the bottom surface of the circuit board sheet 10 in units of strips, and then the circuit board sheet 10 and the encapsulant are encapsulated. A semiconductor device manufactured by sawing 60 at the same time.
또한 도3a 및 도3b에 도시된 반도체 장치(102,103)는 반도체칩(40)의 입출력패드(41)가 중앙부근에 형성된 경우의 실시예이며, 대부분의 구조는 도2a 및 도2b와 유사함으로 그 설명을 생략한다.The semiconductor devices 102 and 103 shown in FIGS. 3A and 3B are embodiments in which the input / output pad 41 of the semiconductor chip 40 is formed near the center, and most of the structures are similar to those of FIGS. 2A and 2B. Omit the description.
이와 같이 본 발명에 의한 반도체 장치(100,101,102,103)는 반도체칩(40)상의 외주연에도 회로기판시트(10)가 위치하고, 그 상면에는 솔더볼(70)이 융착됨으로써 종래보다 많은 수의 솔더볼을 확보할 수 있게 된다.As described above, in the semiconductor devices 100, 101, 102, and 103 according to the present invention, the circuit board sheet 10 is positioned on the outer periphery of the semiconductor chip 40, and the solder balls 70 are fused to the upper surface thereof, thereby securing a larger number of solder balls than before. Will be.
또한 반도체칩(40) 및 히트스프레더(30)의 측부와 회로기판시트(10) 저면에 봉지재(60)가 봉지되어 있음으로써 별도의 보강제가 필요없게 되는 동시에, 상기 봉지재(60)는 회로기판시트(10)를 지지함으로써 회로기판시트(10)의 휨 현상을 억제하고, 상기 회로기판시트(10)에 융착된 솔더볼(70)을 확고하게 지지할 수 있게 된다.In addition, since the encapsulant 60 is encapsulated on the sides of the semiconductor chip 40 and the heat spreader 30 and the bottom surface of the circuit board sheet 10, a separate reinforcing agent is not necessary, and the encapsulant 60 is a circuit. By supporting the substrate sheet 10, the warpage phenomenon of the circuit board sheet 10 can be suppressed, and the solder ball 70 fused to the circuit board sheet 10 can be firmly supported.
또한 상기 반도체칩(40)의 저면에는 히트스프레더(30)가 부착된 채 외부로 노출되어 있음으로써 반도체칩(40)의 작동중 발생되는 열을 상기 히트스프레더(30)가 외부의 공기중으로 신속히 방출하여 반도체칩(40)의 전기적 성능 저하를 억제하게 됨과 동시에 반도체칩(40)의 오동작을 방지하게 된다.In addition, the heat spreader 30 is exposed to the outside with the heat spreader 30 attached to the bottom surface of the semiconductor chip 40 so that the heat spreader 30 quickly releases heat generated during operation of the semiconductor chip 40 to the outside air. As a result, a decrease in electrical performance of the semiconductor chip 40 can be suppressed and a malfunction of the semiconductor chip 40 can be prevented.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 당업자에 의해 여러가지로 변형된 실시예가 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, various modifications may be made by those skilled in the art without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 반도체 장치는 반도체칩상의 외주연에도 솔더볼이 위치함으로써 종래보다 많은 수의 솔더볼을 확보할 수 있는 효과가 있다.Therefore, in the semiconductor device according to the present invention, solder balls are also positioned on the outer circumference of the semiconductor chip, so that a larger number of solder balls can be obtained than in the prior art.
또한 별도의 보강제없이 반도체칩 및 히트스프레더 측부와 회로기판시트의 저면을 봉지재가 감싸고 있음으로써 회로기판시트를 상기 봉지재가 지지하여 회로기판시트의 휨 현상을 방지함은 물론 그 상면에 융착된 솔더볼을 확고하게 지지하는 효과가 있다.In addition, since the encapsulant surrounds the semiconductor chip and heat spreader side and the bottom of the circuit board sheet without any reinforcing agent, the encapsulant supports the circuit board sheet to prevent warpage of the circuit board sheet and the solder ball fused to the upper surface thereof. There is a firm supportive effect.
또한 최근의 반도체칩 집적도 및 동작 주파수가 커짐으로서 대량의 열이 발생하여도 상기 반도체칩의 저면에 부착된 히트스프레더로 인해 그 열이 외부로 신속히 방출됨으로써 반도체칩의 전기적 성능을 저하시키지 않고, 그 반도체칩의 오동작을 억제하는 효과가 있다.In addition, the recent increase in the degree of integration and the operating frequency of the semiconductor chip, even if a large amount of heat generated by the heat spreader attached to the bottom of the semiconductor chip is quickly released to the outside without degrading the electrical performance of the semiconductor chip, There is an effect of suppressing malfunction of the semiconductor chip.
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980046572A KR100337460B1 (en) | 1998-10-31 | 1998-10-31 | Semiconductor devices |
| JP11157963A JP2000138317A (en) | 1998-10-31 | 1999-06-04 | Semiconductor device and its manufacture |
| US09/422,115 US6489667B1 (en) | 1998-10-31 | 1999-10-20 | Semiconductor device and method of manufacturing such device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980046572A KR100337460B1 (en) | 1998-10-31 | 1998-10-31 | Semiconductor devices |
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| KR20000028367A KR20000028367A (en) | 2000-05-25 |
| KR100337460B1 true KR100337460B1 (en) | 2002-07-18 |
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