KR100421777B1 - semiconductor package - Google Patents
semiconductor package Download PDFInfo
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- KR100421777B1 KR100421777B1 KR10-1999-0065927A KR19990065927A KR100421777B1 KR 100421777 B1 KR100421777 B1 KR 100421777B1 KR 19990065927 A KR19990065927 A KR 19990065927A KR 100421777 B1 KR100421777 B1 KR 100421777B1
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- semiconductor chip
- circuit board
- heat sink
- semiconductor
- encapsulant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
이 발명은 반도체패키지에 관한 것으로, 반도체칩의 방열능력을 향상시키고, 봉지재와의 결합력을 향상시키며, 입출력 단자수를 증가시키고 또한 봉지시 공기를 외부로 용이하게 배출시킬 수 있도록, 일면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면으로부터 외부를 향해 연장된 채 부착되어 있으며, 상기 반도체칩의 둘레 영역과 대응하는 부분에는 다수의 슬롯이 형성되어 있는 히트싱크와; 상기 히트싱크의 저면에 부착되어 있으며, 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성된 회로기판과; 상기 반도체칩의 입출력패드와 회로기판의 본드핑거를 전기적으로 접속시키는 도전성와이어와; 상기 반도체칩, 도전성와이어 및 히트싱크의 슬롯 영역에 충진된 봉지재와; 상기 회로기판의 각 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, which improves the heat dissipation capability of a semiconductor chip, improves the bonding force with an encapsulant, increases the number of input / output terminals, and easily discharges air to the outside during encapsulation. A semiconductor chip having an input / output pad formed thereon; A heat sink attached to the semiconductor chip and extending outward from the bottom of the semiconductor chip, wherein a plurality of slots are formed in a portion corresponding to the peripheral area of the semiconductor chip; A circuit board attached to a bottom surface of the heat sink and having a circuit pattern including a bond finger and a ball land; Conductive wires electrically connecting the input / output pads of the semiconductor chip to the bond fingers of the circuit board; An encapsulant filled in the slot region of the semiconductor chip, the conductive wire and the heat sink; It characterized in that it comprises a plurality of conductive balls fused to each borland of the circuit board.
Description
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 반도체칩의 방열능력을 향상시키고, 봉지재와의 결합력을 향상시키며, 입출력 단자수를 증가시키고 또한 봉지시 공기를 외부로 용이하게 배출시킬 수 있는 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and in more detail, improves the heat dissipation capability of a semiconductor chip, improves the bonding force with an encapsulant, increases the number of input / output terminals, and can easily discharge air to the outside during encapsulation. The present invention relates to a semiconductor package.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 상기 반도체칩을 패키징한 반도체패키지 및 상기 반도체패키지들이 실장되는 전자기기도 소형화되어 가는 추세에 있다. 더불어 최근의 반도체패키지는 그 두께를 초박형화하기 위해 회로기판에 관통된 윈도우를 형성하고 상기 윈도우 내측에 반도체칩을 탑재한 반도체패키지도 제조되고 있다.In recent years, a large number of semiconductor chips are packaged on a motherboard such as a mobile phone, a cellular phone, a notebook computer, and designed to perform multifunction in a minimum time, and at the same time, a semiconductor package packaging the semiconductor chip. In addition, electronic devices on which the semiconductor packages are mounted are also becoming smaller. In addition, in recent years, in order to reduce the thickness of the semiconductor package, a semiconductor package in which a window penetrated through a circuit board is formed and a semiconductor chip is mounted inside the window has also been manufactured.
이러한 반도체패키지(100')로서 도1을 참조하여 그 구조를 설명하면 다음과 같다.The structure of the semiconductor package 100 'will be described with reference to FIG.
도시된 바와 같이 상면에 다수의 입출력패드(4')가 형성되어 있는 반도체칩(2')이 구비되어 있고, 상기 반도체칩(2')의 외주연으로는 그 반도체칩(2')이 위치할 수 있도록 윈도우(27')가 형성된 회로기판(20')이 위치되어있다. 상기 회로기판(20')은 수지층(21')을 기본층으로 하여 그 상면에 다수의 본드핑거(22') 및 볼랜드(23')로 이루어진 회로패턴이 형성되어 있고, 상기 회로패턴의 표면은 본드핑거(22') 및 볼랜드(23')가 상부 방향으로 오픈되도록 커버커트(24')가 코팅되어 있다. 상기 반도체칩(2')의 입출력패드(4')와 상기 회로기판(20')의 본드핑거(22')는 전기적으로 접속되도록 도전성와이어(30')에 의해 상호 접속되어 있다. 상기 반도체칩(2')의 저면 즉, 회로기판(20')의 윈도우(27') 저면에는 상기 반도체칩(2')의 방열성능을 향상시키기 위해 히트싱크(10')가 부착되어 있다. 또한, 상기 회로기판(20')의 윈도우(27') 내측에 위치된 반도체칩(2'), 도전성와이어(30') 등을 외부 환경으로부터 보호할 수 있도록 봉지재(40')가 충진되어 있으며, 마지막으로 상기 회로기판(20')의 볼랜드(23')에는 각각 도전성볼(50')이 융착되어 차후 마더보드에 실장 가능한 형태로 되어 있다.As shown in the drawing, a semiconductor chip 2 'having a plurality of input / output pads 4' is formed on an upper surface thereof, and the semiconductor chip 2 'is positioned at an outer circumference of the semiconductor chip 2'. The circuit board 20 'is formed with a window 27'. The circuit board 20 'is formed of a resin layer 21' as a base layer, and a circuit pattern formed of a plurality of bond fingers 22 'and borland 23' is formed on an upper surface thereof, and the surface of the circuit pattern is formed. The cover cut 24 'is coated such that the silver bond finger 22' and the ball land 23 'are opened upward. The input / output pads 4 'of the semiconductor chip 2' and the bond fingers 22 'of the circuit board 20' are connected to each other by conductive wires 30 'so as to be electrically connected. A heat sink 10 'is attached to the bottom surface of the semiconductor chip 2', that is, the bottom surface of the window 27 'of the circuit board 20' to improve heat dissipation performance of the semiconductor chip 2 '. In addition, the encapsulant 40 'is filled to protect the semiconductor chip 2', the conductive wire 30 ', and the like located inside the window 27' of the circuit board 20 'from the external environment. Finally, the conductive balls 50 'are fused to the ball lands 23' of the circuit board 20 'to be mounted on the motherboard later.
그러나 이러한 종래의 반도체패키지는 반도체칩, 회로기판, 히트싱크와 봉지재와의 열팽창 계수차에 의해 상부 또는 하부 방향으로 쉽게 휘는 단점이 있다.However, such a conventional semiconductor package has a disadvantage that it easily bends upward or downward by a thermal expansion coefficient difference between a semiconductor chip, a circuit board, a heat sink, and an encapsulant.
또한, 봉지재와 반도체칩, 회로기판 및 히트싱크와의 접착 면적이 작음으로써 그 결합력이 작아 봉지재가 반도체패키지로부터 쉽게 이탈되는 문제점이 있다.In addition, since the bonding area between the encapsulant and the semiconductor chip, the circuit board, and the heat sink is small, there is a problem in that the encapsulant is easily detached from the semiconductor package.
또한, 상기 반도체칩의 열은 회로기판의 본드핑거, 볼랜드를 포함하는 회로패턴 및 도전성볼을 통해서도 전달되지만 상기의 것들은 두꺼운 수지층을 통하여 히트싱크에 도달됨으로써 전체적인 반도체패키지의 방열성능이 저하되는 문제점이 있다.In addition, the heat of the semiconductor chip is also transmitted through the bond finger of the circuit board, the circuit pattern including the ball land and the conductive ball, but the above are reached by the heat sink through the thick resin layer, the heat dissipation performance of the overall semiconductor package is deteriorated There is this.
또한, 볼랜드가 회로기판의 상면 둘레 근처에만 형성됨으로써 파인피치화하여 대량의 입출력패드를 갖는 반도체칩을 수용할 수 없는 문제점이 있다.In addition, since the borland is formed only around the upper circumference of the circuit board, there is a problem in that it is fine pitched to accommodate a semiconductor chip having a large amount of input / output pads.
더불어 봉지재가 회로기판의 일면에서만 제공되거나 또는 반도체패키지의 구조상 몰드의 에어벤트를 상기 봉지재가 제공되는 동일면에서만 형성 가능함으로써 공기가 상기 회로기판의 윈도우 내측에 갇혀 외부로 배출되지 않고, 많은 보이드를 형성하는 문제점이 있다.In addition, the encapsulant is provided only on one side of the circuit board, or the air vent of the mold can be formed only on the same surface on which the encapsulant is provided, so that air is not trapped inside the window of the circuit board and is discharged to the outside, thereby forming many voids. There is a problem.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 반도체칩의 방열능력을 향상시키고, 봉지재와의 결합력을 향상시키며, 입출력 단자수를 증가시키고 또한 봉지시 공기를 외부로 용이하게 배출시킬 수 있는 반도체패키지를 제공하는 데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, improves the heat dissipation capacity of the semiconductor chip, improves the bonding force with the encapsulant, increases the number of input and output terminals, and facilitates air to the outside during encapsulation To provide a semiconductor package that can be easily discharged.
도1은 종래의 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package.
도2a 및 도2b는 본 발명의 제1실시예에 의한 반도체패키지로서,2A and 2B illustrate a semiconductor package according to a first embodiment of the present invention.
도2a는 단면도이고,2a is a sectional view,
도2b는 봉지재로 몰딩되기 전의 상태를 도시한 평면도이다.2B is a plan view showing a state before molding into an encapsulant.
도3a 및 도3b는 본 발명의 제2실시예에 의한 반도체패키지로서,3A and 3B illustrate a semiconductor package according to a second embodiment of the present invention.
도3a는 단면도이고,3a is a sectional view,
도3b는 봉지재로 몰딩되기 전의 상태를 도시한 저면도이다.3B is a bottom view showing a state before molding into an encapsulant.
도4a 및 도4b는 본 발명의 제3실시예에 의한 반도체패키지로서,4A and 4B illustrate a semiconductor package according to a third embodiment of the present invention.
도4a는 단면도이고,4a is a sectional view,
도4b는 봉지재로 몰딩되기 전의 상태를 도시한 저면도이다.4B is a bottom view showing a state before molding into an encapsulant.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101,102,103; 본 발명의 제1,2,3 실시예에 의한 반도체패키지101,102,103; Semiconductor Packages According to Embodiments 1, 2 and 3 of the Invention
2; 반도체칩 4; 입출력패드2; Semiconductor chip 4; I / O pad
10; 히트싱크 14; 히트싱크에 형성된 슬롯10; Heatsink 14; Slot formed in heat sink
20; 회로기판 21; 필름20; Circuit board 21; film
22; 본드핑거 23; 볼랜드22; Bondfinger 23; Borland
24; 회로기판에 형성된 슬롯 30; 도전성와이어24; A slot 30 formed in the circuit board; Conductive Wire
40; 봉지재 50; 도전성볼40; Encapsulant 50; Conductive ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 일면에 다수의 입출력패드가 형성된 반도체칩과; 상기 반도체칩의 저면으로부터 외부를 향해 연장된 채 부착되어 있으며, 상기 반도체칩의 둘레 영역과 대응하는 부분에는 다수의 슬롯이 형성되어 있는 히트싱크와; 상기 히트싱크의 저면에 부착되어 있으며, 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성된 회로기판과; 상기 반도체칩의 입출력패드와 회로기판의 본드핑거를 전기적으로 접속시키는 도전성와이어와; 상기 반도체칩, 도전성와이어 및 히트싱크의 슬롯 영역에 충진된 봉지재와; 상기 회로기판의 각 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention includes a semiconductor chip having a plurality of input / output pads formed on one surface thereof; A heat sink attached to the semiconductor chip and extending outward from the bottom of the semiconductor chip, wherein a plurality of slots are formed in a portion corresponding to the peripheral area of the semiconductor chip; A circuit board attached to a bottom surface of the heat sink and having a circuit pattern including a bond finger and a ball land; Conductive wires electrically connecting the input / output pads of the semiconductor chip to the bond fingers of the circuit board; An encapsulant filled in the slot region of the semiconductor chip, the conductive wire and the heat sink; It characterized in that it comprises a plurality of conductive balls fused to each borland of the circuit board.
여기서, 상기 반도체칩은 입출력패드가 상면에 위치하도록 탑재될 수 있고,이때, 상기 회로기판은 본드핑거가 히트싱크의 슬롯을 통해 상부 방향을 향해 오픈되도록 함이 바람직하다.Here, the semiconductor chip may be mounted such that an input / output pad is positioned on an upper surface thereof. In this case, the circuit board may be such that the bond finger is opened upward through a slot of a heat sink.
또한, 상기 반도체칩은 입출력패드가 하면에 위치되도록 하여 탑재될 수 있다.In addition, the semiconductor chip may be mounted so that the input / output pad is positioned on the bottom surface thereof.
상기 반도체칩 하면에 부착되는 히트싱크 및 회로기판은 상기 반도체칩의 입출력패드와 간섭하지 않토록, 슬롯이 형성됨이 바람직하다.Preferably, the heat sink and the circuit board attached to the lower surface of the semiconductor chip are formed with slots so as not to interfere with the input / output pad of the semiconductor chip.
상기 회로기판의 본드핑거는 반도체칩 하면의 외주연에 위치하는 회로기판 하면에 형성될 수 있다.The bond finger of the circuit board may be formed on the bottom surface of the circuit board positioned at the outer circumference of the bottom surface of the semiconductor chip.
상기 회로기판의 본드핑거는 반도체칩 하면의 내주연에 위치하는 회로기판 하면에 형성될 수 있다.The bond finger of the circuit board may be formed on the bottom surface of the circuit board positioned at the inner circumference of the bottom surface of the semiconductor chip.
상기 봉지재는 히트싱크 및 회로기판의 슬롯 내측에 모두 충진됨이 바람직하다.The encapsulant is preferably filled both inside the heat sink and the slot of the circuit board.
상기 반도체칩은 상면 또는 상면을 포함하는 측면이 봉지재 외측으로 노출될 수도 있다.The semiconductor chip may have an upper surface or a side surface including the upper surface exposed to the outside of the encapsulant.
상기 모든 반도체패키지는 회로기판의 하면 전체에 볼랜드가 형성될 수 있다.All of the semiconductor packages may have a borland formed on the entire lower surface of the circuit board.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 반도체칩과 회로기판 사이에 히트싱크가 위치됨으로써 반도체칩 및 회로기판으로부터의 열을 상기 히트싱크가 방출하게 되어 전체적인 반도체패키지의 방열능력이 향상된다.As described above, according to the semiconductor package according to the present invention, the heat sink is located between the semiconductor chip and the circuit board, so that the heat sink releases heat from the semiconductor chip and the circuit board, thereby improving the heat dissipation capability of the overall semiconductor package. .
또한, 히트싱크 또는 이와 대응하는 회로기판에 슬롯에 형성되고, 상기 슬롯에 봉지재가 충진됨으로써, 봉지재와의 접착 면적이 커져 그 결합력이 향상되고, 또한 봉지재가 반도체패키지의 상,하부에 적절히 분포됨으로써 반도체패키지의 휨 현상이 억제된다.In addition, the heat sink or the corresponding circuit board is formed in the slot, and the sealing material is filled in the slot, thereby increasing the adhesive area with the sealing material, thereby improving the bonding force, and the sealing material is properly distributed on the upper and lower portions of the semiconductor package. As a result, warpage of the semiconductor package is suppressed.
또한, 회로기판의 하면 전체에 볼랜드를 형성할 수 있음으로써, 종래에 비해 증가된 입출력 단자수를 확보할 수 있게 된다.In addition, since the land can be formed on the entire lower surface of the circuit board, it is possible to ensure an increased number of input and output terminals compared to the prior art.
더불어, 봉지시에 히트싱크 또는 회로기판의 상,하면에 적절히 게이트 및 에어벤트 영역을 형성할 수 있음으로써 봉지재 내측의 보이드 형성을 억제할 수 있다.In addition, the gate and air vent regions can be appropriately formed on the upper and lower surfaces of the heat sink or the circuit board during encapsulation, thereby suppressing void formation inside the encapsulant.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 및 도2b는 본 발명의 제1실시예에 의한 반도체패키지(101)로서, 도2a는 그 단면도이고, 도2b는 봉지재로 몰딩되기 전의 상태를 도시한 평면도이다.2A and 2B are a semiconductor package 101 according to a first embodiment of the present invention, where FIG. 2A is a sectional view thereof, and FIG. 2B is a plan view showing a state before molding into an encapsulant.
먼저 상면을 향하여 입출력패드(4)가 구비된 반도체칩(2)이 위치되어 있고, 그 하면에는 상기 반도체칩(2)의 면적보다 큰 히트싱크(10)가 부착되어 있다. 상기 히트싱크(10)는 통상적인 구리(Cu), 알루미늄(Al) 등과 같이 열도전성이 우수한 물질로 제조된 것이며, 상기 반도체칩(2)의 하면 외주연과 대응되는 부분에는 다수의 슬롯(14)이 형성되어 있다. 즉, 도2b에 도시된 바와 같이 반도체칩(2)의 네변의 외주연과 대응하는 영역에 일정크기의 슬롯(14)이 다수 형성되어 있다.First, a semiconductor chip 2 having an input / output pad 4 is positioned toward an upper surface thereof, and a heat sink 10 larger than an area of the semiconductor chip 2 is attached to the lower surface thereof. The heat sink 10 is made of a material having excellent thermal conductivity, such as conventional copper (Cu) and aluminum (Al), and a plurality of slots 14 are formed at portions corresponding to the outer circumference of the bottom surface of the semiconductor chip 2. ) Is formed. That is, as shown in FIG. 2B, a plurality of slots 14 having a predetermined size are formed in a region corresponding to the outer periphery of the four sides of the semiconductor chip 2.
상기 히트싱크(10)의 저면에는 상기 히트싱크(10)의 면적과 유사한회로기판(20)이 부착되어 있다. 상기 회로기판(20)은 표면에 본드핑거(22) 및 볼랜드(23)를 갖는 회로패턴이 포함되어 있으며, 또한 상기 회로패턴은 가요성 필름이나 테이프(이하, '필름(21)'으로 통칭함)에 형성되어 있다. 또한 상기 회로패턴중 본드핑거(22)는 필름(21)의 상부 방향 즉, 히트싱크(10)의 슬롯(14) 내측을 향하도록 오픈되어 있고, 회로패턴중 볼랜드(23)는 하부 방향을 향해 오픈되어 있다.The bottom surface of the heat sink 10 is attached with a circuit board 20 similar to the area of the heat sink 10. The circuit board 20 includes a circuit pattern having a bond finger 22 and a ball land 23 on a surface thereof, and the circuit pattern is referred to as a flexible film or a tape (hereinafter, referred to as a 'film 21'). ) Is formed. In addition, the bond finger 22 of the circuit pattern is opened to face the upper direction of the film 21, that is, the inside of the slot 14 of the heat sink 10, the ball land 23 of the circuit pattern toward the lower direction It is open.
여기서, 상기 회로기판(20)은 비록 가요성 필름이나 테이프 등을 이용한 것을 예로 하여 설명하지만, 이것으로만 한정되지 않으며 통상적인 인쇄회로기판 등도 이용할 수 있다.Here, although the circuit board 20 will be described by using a flexible film or tape as an example, the present invention is not limited thereto, and a conventional printed circuit board may also be used.
계속해서, 상기 반도체칩(2)의 입출력패드(4)와 회로기판(20)의 본드핑거(22)는 골드와이어 및 알루미늄와이어와 같은 도전성와이어(30)에 의해 상호 전기적으로 접속되어 있다.Subsequently, the input / output pads 4 of the semiconductor chip 2 and the bond fingers 22 of the circuit board 20 are electrically connected to each other by conductive wires 30 such as gold wires and aluminum wires.
상기 반도체칩(2), 도전성와이어(30) 및 히트싱크(10)의 슬롯(14) 내측 및 그 부근에는 봉지재(40)가 충진되어 있음으로써 상기 반도체칩(2) 및 도전성와이어(30) 등이 외부환경으로부터 보호될 수 있도록 되어 있다. 이때, 상기 봉지재(40)는 통상적인 에폭시몰딩컴파운드 또는 액상봉지재 등일 수 있다.The semiconductor chip 2 and the conductive wire 30 are filled with an encapsulant 40 in and around the slot 14 of the semiconductor chip 2, the conductive wire 30, and the heat sink 10. The back is protected from the external environment. At this time, the encapsulant 40 may be a conventional epoxy molding compound or a liquid encapsulant.
상기 회로기판(20)의 각 볼랜드(23)에는 솔더볼과 같은 도전성볼(50)이 융착되어 있음으로써 상기 반도체패키지(101)가 마더보드 등에 실장 가능하게 되어 있다.Conductive balls 50 such as solder balls are welded to each ball land 23 of the circuit board 20 so that the semiconductor package 101 can be mounted on a motherboard or the like.
도3a 및 도3b는 본 발명의 제2실시예에 대한 반도체패키지(102)로서, 도3a는 그 단면도이고, 도3b는 봉지재로 몰딩되기 전의 상태를 도시한 저면도이다.3A and 3B show a semiconductor package 102 according to a second embodiment of the present invention. FIG. 3A is a cross-sectional view thereof, and FIG. 3B is a bottom view showing a state before molding into an encapsulant.
또한, 도4a 및 도4b는 본 발명의 제3실시예에 의한 반도체패키지(103)로서, 도4a는 그 단면도이고, 도4b는 봉지재로 몰딩되기 전의 상태를 도시한 저면도이다.4A and 4B show a semiconductor package 103 according to a third embodiment of the present invention, FIG. 4A is a cross-sectional view thereof, and FIG. 4B is a bottom view showing a state before molding into an encapsulant.
여기서 상기 제2실시예 및 제3실시예에 의한 반도체패키지(102,103)는 그 구조가 유사하므로 동시에 설명하기로 한다.Here, the semiconductor packages 102 and 103 according to the second and third embodiments are similar in structure and will be described at the same time.
도시된 바와 같이 먼저 입출력패드(4)가 하면을 향하도록 반도체칩(2)이 위치되어 있고, 상기 반도체칩(2)의 하면에는 히트싱크(10) 및 회로기판(20)이 부착되어 있다. 물론, 상기 히트싱크(10) 및 회로기판(20)은 제1실시예에와 같이 상기 반도체칩(2)의 면적보다 크게 형성되어 있다.As shown, first, the semiconductor chip 2 is positioned so that the input / output pad 4 faces the lower surface, and the heat sink 10 and the circuit board 20 are attached to the lower surface of the semiconductor chip 2. Of course, the heat sink 10 and the circuit board 20 are formed larger than the area of the semiconductor chip 2 as in the first embodiment.
또한, 상기 반도체칩(2) 하면에 부착된 히트싱크(10) 및 회로기판(20)은 상기 반도체칩(2)의 입출력패드(4)와 서로 간섭하지 않토록 일정 크기로 관통된 다수의 슬롯(14,24)이 형성되어 있다. 즉, 도3b 및 도4b에 도시된 바와 같이 반도체칩(2)의 내주연 및 외주연 일정 영역과 대응하는 히트싱크(10) 및 회로기판(20)에 다수의 슬롯이 형성되어 있다.In addition, the heat sink 10 and the circuit board 20 attached to the lower surface of the semiconductor chip 2 have a plurality of slots penetrated to a predetermined size so as not to interfere with the input / output pad 4 of the semiconductor chip 2. (14,24) are formed. That is, as illustrated in FIGS. 3B and 4B, a plurality of slots are formed in the heat sink 10 and the circuit board 20 corresponding to the inner and outer peripheral regions of the semiconductor chip 2.
계속해서, 상기 회로기판(20)에 형성되는 본드핑거(22)는 회로기판(20)의 하면을 향하여 오픈되어 있으며, 이는 도3a 및 도3b에 도시된 바와 같이 반도체칩(2) 하면의 외주연에 위치하는 회로기판(20) 영역에 형성되거나 또는 도4a 및 도4b에 도시된 바와 같이 반도체칩(2) 하면의 내주연에 위치하는 회로기판(20) 영역에 형성될 수 있다.Subsequently, the bond fingers 22 formed on the circuit board 20 are open toward the lower surface of the circuit board 20, which is outside the lower surface of the semiconductor chip 2 as shown in FIGS. 3A and 3B. It may be formed in the area of the circuit board 20 located at the periphery or in the area of the circuit board 20 located at the inner periphery of the lower surface of the semiconductor chip 2 as shown in FIGS. 4A and 4B.
또한, 상기 반도체칩(2), 도전성와이어(30) 및 히트싱크(10)와 회로기판(20)의 슬롯(14,24) 내측에는 모두 봉지재(40)가 충진됨으로써 상기 반도체칩(2) 등이외부 환경으로부터 보호될 수 있도록 되어 있다. 물론, 상기 봉지재(40)는 히트싱크(10)를 중심으로 상기 슬롯(14,24)을 통해 상,하부 방향으로 위치됨으로써, 상기 히트싱크(10)의 상,하면을 연결하여 동시에 인터락킹하는 역할을 한다. 따라서 상기 봉지재(40), 반도체칩(2), 히트싱크(10) 및 회로기판(20) 사이의 열팽창 계수차에 의한 반도체패키지(102,103)의 휨 현상을 억제함은 물론, 접착면적이 커지고 상기 인터락킹 효과에 의해 상기 봉지재(40)가 반도체패키지(102,103)에서 이탈되지 않게 된다.In addition, the semiconductor chip 2 is filled with the sealing material 40 inside the semiconductor chip 2, the conductive wire 30, the heat sink 10, and the slots 14 and 24 of the circuit board 20. It is designed to be protected from the outside environment. Of course, the encapsulant 40 is positioned upward and downward through the slots 14 and 24 about the heat sink 10, thereby interlocking the upper and lower surfaces of the heat sink 10 simultaneously. It plays a role. As a result, the bending area of the semiconductor packages 102 and 103 due to the difference in thermal expansion coefficient between the encapsulant 40, the semiconductor chip 2, the heat sink 10, and the circuit board 20 is suppressed, and the adhesion area is increased. The encapsulant 40 is not separated from the semiconductor packages 102 and 103 by the interlocking effect.
더불어, 반도체패키지(102,103)의 제조 공정중 몰드 등에 형성되는 게이트 및 에어벤트를 상기 반도체패키지(102,103)의 상면 및 하면에 대응하도록 형성할 수 있음으로써(예를 들면, 게이트를 반도체패키지(102,103)의 상면에, 에어벤트를 반도체패키지(102,103)의 하면에 대응하도록 형성함), 봉지 공정중 봉지재 가스 등이 외부로 용이하게 방출되고 결국 봉지재(40) 또는 히트싱크(10) 및 회로기판(20)의 슬롯(14,24) 내측에 보이드가 형성되지 않게 된다.In addition, the gates and air vents formed in the mold and the like during the manufacturing process of the semiconductor packages 102 and 103 can be formed so as to correspond to the top and bottom surfaces of the semiconductor packages 102 and 103 (for example, the gates to the semiconductor packages 102 and 103). On the upper surface of the air vent to correspond to the lower surfaces of the semiconductor packages 102 and 103), the encapsulant gas and the like are easily released to the outside during the encapsulation process, and eventually the encapsulant 40 or the heat sink 10 and the circuit board The voids are not formed inside the slots 14 and 24 of the (20).
한편, 상기 반도체패키지(101,102)는 반도체칩(2)의 상면 또는 상면을 포함하는 측면이 외부로 노출되도록 봉지할 수도 있다. 상기와 같이 하면, 반도체칩(2)의 열은 히트싱크(10) 뿐만 아니라 상기 반도체칩(2)의 상면을 통해 직접 외부로 방출됨으로써 방열 성능이 월등히 향상된다.Meanwhile, the semiconductor packages 101 and 102 may be sealed such that the top surface or the side surface including the top surface of the semiconductor chip 2 is exposed to the outside. In this manner, the heat of the semiconductor chip 2 is directly discharged to the outside through the upper surface of the semiconductor chip 2 as well as the heat sink 10, thereby improving heat dissipation performance.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 반도체칩과 회로기판 사이에 히트싱크가 위치됨으로써 반도체칩 및 회로기판으로부터의 열을 상기 히트싱크가 방출하게 되어 전체적인 반도체패키지의 방열능력이 향상되는 효과가 있다.As described above, according to the semiconductor package according to the present invention, the heat sink is positioned between the semiconductor chip and the circuit board so that the heat sink emits heat from the semiconductor chip and the circuit board, thereby improving the heat dissipation capability of the overall semiconductor package. It works.
또한, 히트싱크 또는 이와 대응하는 회로기판에 슬롯에 형성되고, 상기 슬롯에 봉지재가 충진되어 인터락킹됨으로써, 봉지재와의 결합력이 향상됨은 물론, 반도체패키지의 휨 현상이 억제되는 효과가 있다.In addition, a heat sink or a circuit board corresponding thereto is formed in a slot, and the slot is filled with an encapsulant to be interlocked, so that the bonding force with the encapsulant is improved and the bending of the semiconductor package is suppressed.
또한, 회로기판의 하면 전체에 볼랜드를 형성할 수 있음으로써, 종래에 비해 증가된 입출력 단자수를 확보할 수 있는 효과가 있다.In addition, since the land can be formed on the entire lower surface of the circuit board, there is an effect that it is possible to ensure an increased number of input and output terminals compared to the prior art.
더불어, 봉지시에 히트싱크 또는 회로기판의 상,하면에 적절히 게이트 및 에어벤트 영역을 형성할 수 있음으로써 봉지재 내측의 보이드 형성을 억제할 수 있는 효과가 있다.In addition, since the gate and air vent regions can be appropriately formed on the upper and lower surfaces of the heat sink or the circuit board during sealing, there is an effect of suppressing void formation inside the sealing material.
Claims (10)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697307A (en) * | 1992-09-16 | 1994-04-08 | Hitachi Ltd | Semiconductor integrated circuit |
| KR19980047800A (en) * | 1996-12-16 | 1998-09-15 | 김광호 | High heat dissipation semiconductor package having a double layered lead structure and a method of manufacturing the same |
| KR19990000383A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | High power package structure and manufacturing method |
| KR19990015823A (en) * | 1997-08-11 | 1999-03-05 | 윤종용 | BG package and manufacturing method thereof |
| KR19990052643A (en) * | 1997-12-23 | 1999-07-15 | 구본준 | Semiconductor package and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697307A (en) * | 1992-09-16 | 1994-04-08 | Hitachi Ltd | Semiconductor integrated circuit |
| KR19980047800A (en) * | 1996-12-16 | 1998-09-15 | 김광호 | High heat dissipation semiconductor package having a double layered lead structure and a method of manufacturing the same |
| KR19990000383A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | High power package structure and manufacturing method |
| KR19990015823A (en) * | 1997-08-11 | 1999-03-05 | 윤종용 | BG package and manufacturing method thereof |
| KR19990052643A (en) * | 1997-12-23 | 1999-07-15 | 구본준 | Semiconductor package and manufacturing method |
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