KR100381838B1 - Semiconductor package - Google Patents
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- KR100381838B1 KR100381838B1 KR10-2000-0053084A KR20000053084A KR100381838B1 KR 100381838 B1 KR100381838 B1 KR 100381838B1 KR 20000053084 A KR20000053084 A KR 20000053084A KR 100381838 B1 KR100381838 B1 KR 100381838B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
이 발명은 반도체패키지에 관한 것으로, 다양한 크기의 반도체칩을 적층할 수 있도록, 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 제2면에 수지층을 기본층으로 그 표면에는 회로패턴이 형성되어 있으며, 상기 회로패턴의 일단은 상기 제1반도체칩의 입출력패드에 접속된 신호전달부재와; 상기 신호전달부재의 일면에, 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제2반도체칩과; 상기 제1반도체칩의 제1면에 접착되어 있으며, 상기 신호전달부재의 회로패턴 및 제2반도체칩의 입출력패드가 전기적 도전성와이어에 의해 연결되고, 마더보드에 실장 가능한 섭스트레이트와; 상기 제1반도체칩, 제2반도체칩, 신호전달부재, 전기적 도전성와이어 및 섭스트레이트의 일면을 봉지하는 봉지재를 포함하여 이루어진 것을 특징으로 함.The present invention relates to a semiconductor package, comprising: a first semiconductor chip having a first plane and a second plane that are substantially planar, and having a plurality of input / output pads formed thereon so as to stack semiconductor chips of various sizes; A circuit pattern is formed on a surface of the first surface of the first semiconductor chip, the resin layer being a base layer, and one end of the circuit pattern is connected to an input / output pad of the first semiconductor chip; A second semiconductor chip on one surface of the signal transmission member, having a first plane and a second surface being substantially planar, and having a plurality of input / output pads formed thereon; A substrate that is bonded to the first surface of the first semiconductor chip, the circuit pattern of the signal transmission member and the input / output pad of the second semiconductor chip are connected by an electrically conductive wire, and is mounted on the motherboard; And an encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the signal transmission member, the electrically conductive wire, and one side of the substrate.
Description
본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 적층형 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a stacked semiconductor package.
통상 반도체패키지는 반도체칩을 외부 환경으로부터 안전하게 보호함은 물론, 그 반도체칩과 마더보드(Mother Board)와의 전기적 신호가 용이하게 교환되도록 한 것을 말한다.In general, the semiconductor package not only protects the semiconductor chip from the external environment, but also means that the electrical signal between the semiconductor chip and the motherboard is easily exchanged.
최근에는 상기한 반도체패키지 내부에 다수의 반도체칩을 적층함으로써 고기능화를 구현한 적층형 반도체패키지가 출시되고 있으며, 이러한 종래의 통상적인 적층형 반도체패키지(100')를 도1에 도시하였다.Recently, a multilayer semiconductor package having high functionality by stacking a plurality of semiconductor chips inside the semiconductor package has been released. Such a conventional multilayer semiconductor package 100 'is shown in FIG.
도시된 바와 같이 통상 수지층(18')을 중심으로 상,하면에 본드핑거(20a') 및 볼랜드(20b')를 갖는 회로패턴(20')이 형성되어 있고, 상기 회로패턴(20')의 표면은 커버코트(23')로 코팅된 회로기판(16')이 구비되어 있다. 또한, 상기 회로기판(16')의 상면 중앙부에는 제1반도체칩(2')이 접착층에 의해 접착되어 있고, 상기 제1반도체칩(2')의 상면에는 제2반도체칩(6')이 접착층으로 접착되어 있다. 물론, 상기 제1반도체칩(2') 및 제2반도체칩(6')의 상면에는 다수의 입출력패드(4',8')가 형성되어 있다. 상기 제1반도체칩(2') 및 제2반도체칩(6')의 입출력패드(4',8')는각각 회로기판(16')에 형성된 회로패턴(20')중 본드핑거(20a')에 도전성와이어(60')로 본딩되어 있다. 또한, 제1반도체칩(2'), 제2반도체칩(6'), 도전성와이어(60') 및 회로기판(16')의 상면은 봉지재(40')로 봉지되어 있다. 상기 회로기판(16')의 하면에 형성된 회로패턴(20')중 볼랜드(20b')에는 다수의 도전성볼(50')이 융착되어 있으며, 이 도전성볼(50')이 차후 마더보드의 소정 패턴에 본딩된다. 도면중 미설명 부호 20c'는 도전성 비아홀이다.As shown, a circuit pattern 20 'having a bond finger 20a' and a borland 20b 'is formed on the upper and lower surfaces of the resin layer 18', and the circuit pattern 20 'is formed. The surface of the circuit board 16 'is coated with a cover coat 23'. In addition, the first semiconductor chip 2 'is bonded to the center of the upper surface of the circuit board 16' by an adhesive layer, and the second semiconductor chip 6 'is attached to the upper surface of the first semiconductor chip 2'. It is bonded by an adhesive layer. Of course, a plurality of input / output pads 4 'and 8' are formed on the upper surfaces of the first semiconductor chip 2 'and the second semiconductor chip 6'. I / O pads 4 'and 8' of the first semiconductor chip 2 'and the second semiconductor chip 6' are bonded fingers 20a 'of the circuit patterns 20' formed on the circuit board 16 ', respectively. Is bonded to the conductive wire 60 '. In addition, the upper surface of the first semiconductor chip 2 ', the second semiconductor chip 6', the conductive wire 60 ', and the circuit board 16' is sealed with an encapsulant 40 '. A plurality of conductive balls 50 'are fused to the ball lands 20b' among the circuit patterns 20 'formed on the bottom surface of the circuit board 16', and the conductive balls 50 'are subsequently fixed on the motherboard. Bonded to the pattern. In the figure, reference numeral 20c 'denotes a conductive via hole.
이러한 반도체패키지(100')는 제1반도체칩(2') 및 제2반도체칩(6')의 전기적 신호가 도전성와이어(60'), 회로기판(16')의 본드핑거(20a'), 도전성 비아홀(20c'), 볼랜드 (20b') 및 도전성볼(50')을 통해서 마더보드와 교환되며, 두개의 반도체칩이 적층된 상태이므로 반도체패키지가 고용량, 고기능화되고 또한 실장밀도를 높일 수 있는 장점이 있다.In the semiconductor package 100 ', the electrical signals of the first semiconductor chip 2' and the second semiconductor chip 6 'are transmitted to the conductive wire 60', the bond finger 20a 'of the circuit board 16', It is exchanged with the motherboard through the conductive via hole 20c ', the borland 20b', and the conductive ball 50 ', and since the two semiconductor chips are stacked, the semiconductor package can have high capacity, high functionality, and high mounting density. There is an advantage.
그러나, 상기 제1반도체칩의 입출력패드에 본딩되는 도전성와이어와의 접촉을 피하기 위해, 상기 제2반도체칩의 넓이 또는 부피가 상기 제1반도체칩의 넓이 또는 부피보다 반듯이 작아야 하는 단점이 있다. 즉, 상기 제2반도체칩의 부피가 제1반도체칩의 부피와 같거나 클 경우에는 그 제2반도체칩의 저면과 도전성와이어가 상호 쇼트됨으로써 제1반도체칩의 전기적 기능이 마비되는 문제가 있어, 반듯이 그 제2반도체칩의 크기가 제1반도체칩의 크기보다 작아야 한다.However, in order to avoid contact with conductive wires bonded to the input / output pads of the first semiconductor chip, an area or volume of the second semiconductor chip must be smaller than the width or volume of the first semiconductor chip. That is, when the volume of the second semiconductor chip is equal to or larger than the volume of the first semiconductor chip, the bottom surface of the second semiconductor chip and the conductive wire are shorted to each other, thereby causing paralysis of the electrical function of the first semiconductor chip. On the contrary, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip.
이러한 문제는 동일한 크기의 반도체칩을 다수 적층하여야 하는 메모리 반도체패키지(예를 들면 다수의 DRAM을 적층한 반도체패키지)에 적용할 수 없어, 패키징할 수 있는 반도체칩의 종류를 극히 제한시키고 있다.Such a problem cannot be applied to a memory semiconductor package (for example, a semiconductor package in which a plurality of DRAMs are stacked) in which a plurality of semiconductor chips of the same size must be stacked, thereby limiting the types of semiconductor chips that can be packaged.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 다양한 크기의 반도체칩을 적층할 수 있는 반도체패키지의 제공에 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and to provide a semiconductor package capable of stacking semiconductor chips of various sizes.
도1은 종래의 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package.
도2는 본 발명에 의한 반도체패키지를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package according to the present invention.
도3a는 본 발명에 의한 반도체패키지를 도시한 단면도이고, 도3b는 도3a에서 제2반도체칩 및 봉지재 등이 제거된 상태의 평면도이다.FIG. 3A is a cross-sectional view illustrating a semiconductor package according to the present invention, and FIG. 3B is a plan view of a state in which the second semiconductor chip and the encapsulant are removed in FIG. 3A.
도4는 본 발명에 의한 다른 반도체패키지를 도시한 단면도이다.4 is a cross-sectional view showing another semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101,102,103; 본 발명에 의한 반도체패키지101,102,103; Semiconductor package according to the present invention
1; 제1반도체칩 1a,2a,11a,70a; 제1면One; First semiconductor chips 1a, 2a, 11a, 70a; Front page
1b,2b,11b,70b; 제2면 1c,2c; 입출력패드1b, 2b, 11b, 70b; Second page 1c, 2c; I / O pad
2; 제2반도체칩2; Second semiconductor chip
10; 인쇄회로기판 11,21; 수지층10; Printed circuit boards 11,21; Resin layer
12,22; 회로패턴 12a; 본드핑거12,22; Circuit pattern 12a; Bondfinger
12b; 볼랜드 13; 비아홀12b; Borland 13; Via Hole
14; 커버코트14; Cover coat
20; 신호전달부재 23; 관통공20; A signal transmitting member 23; Through hole
40; 도전성와이어 50; 봉지재40; Conductive wire 50; Encapsulant
60; 도전성볼 70; 리드60; Conductive ball 70; lead
71a; 랜드 71b; 본드핑거71a; Land 71b; Bondfinger
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 제2면에 수지층을 기본층으로 그 표면에는 회로패턴이 형성되어 있으며, 상기 회로패턴의 일단은 상기 제1반도체칩의 입출력패드에 접속된 신호전달부재와; 상기 신호전달부재의 일면에, 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제2반도체칩과; 상기 제1반도체칩의 제1면에 접착되어 있으며, 상기 신호전달부재의 회로패턴 및 제2반도체칩의 입출력패드가 전기적 도전성와이어에 의해 연결되고, 마더보드에 실장 가능한 섭스트레이트와; 상기 제1반도체칩, 제2반도체칩, 신호전달부재, 전기적 도전성와이어 및 섭스트레이트의 일면을 봉지하는 봉지재를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention has a first plane and a second surface which are substantially planar, and the second surface comprises: a first semiconductor chip having a plurality of input / output pads; A circuit pattern is formed on a surface of the first surface of the first semiconductor chip, the resin layer being a base layer, and one end of the circuit pattern is connected to an input / output pad of the first semiconductor chip; A second semiconductor chip on one surface of the signal transmission member, having a first plane and a second surface being substantially planar, and having a plurality of input / output pads formed thereon; A substrate that is bonded to the first surface of the first semiconductor chip, the circuit pattern of the signal transmission member and the input / output pad of the second semiconductor chip are connected by an electrically conductive wire, and is mounted on the motherboard; And an encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the signal transmission member, the electrically conductive wire, and one side of the substrate.
상기 신호전달부재는 일정크기의 관통공이 형성된 수지층과, 상기 수지층의 일면에 상기 관통공을 지나서 상기 수지층의 외주연까지 일정길이로 연장된 회로패턴을 포함하여 이루어질 수 있다.The signal transmission member may include a resin layer in which a through hole of a predetermined size is formed, and a circuit pattern extending in a predetermined length from one surface of the resin layer to an outer circumference of the resin layer through the through hole.
상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖는 수지층을 중심으로, 상기 제1면에는 볼랜드를 갖고 상기 제2면에는 본드핑거를 갖는 회로패턴을 포함하여 이루어진 인쇄회로기판, 써킷필름 또는 서킷테이프중 어느 하나일 수 있다.The substrate includes a circuit pattern including a circuit pattern having a first surface and a second surface that are substantially planar, and having a borland on the first surface and a bond finger on the second surface. It can be either film or circuit tape.
여기서, 상기 볼랜드에는 도전성볼이 더 융착됨이 바람직하다.Here, it is preferable that the conductive ball is further fused to the ball land.
상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖고, 상기 제1면에는 봉지재 외부로 노출된 랜드가 형성되고, 상기 제2면에는 상기 신호전달부재의 회로패턴 및 제2반도체칩의 입출력패드가 전기적 도전성와이어에 의해 연결되는 본드핑거를 갖는 다수의 리드일 수 있다.The substrate has a first plane and a second plane which are substantially planar, and lands are exposed to the outside of the encapsulant on the first surface, and the circuit pattern and the second semiconductor chip of the signal transmission member are formed on the second surface. The input and output pads may be a plurality of leads having bond fingers connected by electrically conductive wires.
상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 제1반도체칩의 제2면에 수지층에 의해 보호되는 신호전달부재가 위치되고, 그 신호전달부재에 제2반도체칩이 접착됨으로써, 상기 제2반도체칩과 상기 신호전달부재(회로패턴) 사이의 상호 간섭이나, 쇼트 등이 발생할 여지가 없게 된다.According to the semiconductor package according to the present invention as described above, the signal transmission member protected by the resin layer is located on the second surface of the first semiconductor chip, and the second semiconductor chip is adhered to the signal transmission member, whereby There is no room for mutual interference or short between the semiconductor chip and the signal transmission member (circuit pattern).
더불어, 제1반도체칩의 크기에 대하여 상대적으로 다양한 크기의 제2반도체칩을 적층할 수 있음으로써, 고용량 고기능의 반도체패키지를 제공하게 되고, 또한 섭스트레이트의 패턴 설계 자유도도 높아진다.In addition, by stacking the second semiconductor chips of various sizes relatively to the size of the first semiconductor chip, it is possible to provide a high-capacity, high-functional semiconductor package, and also to increase the degree of freedom of pattern design of the substrate.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2는 본 발명에 의한 반도체패키지(101)를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package 101 according to the present invention.
도시된 바와 같이 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)이 구비되어 있다.As shown, the first semiconductor chip 1 has a first surface 1a and a second surface 1b which are substantially planar, and the second surface 1b is provided with a plurality of input / output pads 1c. have.
상기 제1반도체칩(1)의 제2면(1b)에 수지층(21)을 기본층으로 그 표면에는 회로패턴(22)이 형성되어 있으며, 상기 회로패턴(22)의 일단은 상기제1반도체칩(1)의 입출력패드(1c)에 접속된 신호전달부재(20)가 구비되어 있다.The resin layer 21 is formed on the second surface 1b of the first semiconductor chip 1, and a circuit pattern 22 is formed on the surface thereof, and one end of the circuit pattern 22 is formed on the first layer. The signal transmission member 20 connected to the input / output pad 1c of the semiconductor chip 1 is provided.
상기 신호전달부재(20)의 일면에, 대략 평면인 제1면(2a)과 제2면(2b)을 가지고, 상기 제2면(2b)에는 다수의 입출력패드(2c)가 형성된 제2반도체칩(2)이 구비되어 있다.A second semiconductor having one surface 2a and a second surface 2b which are substantially planar on one surface of the signal transmission member 20, and a plurality of input / output pads 2c formed on the second surface 2b. The chip 2 is provided.
또한, 상기 제1반도체칩(1)의 제1면(1a)에 접착되어 있으며, 상기 신호전달부재(20)의 회로패턴(22) 및 제2반도체칩(2)의 입출력패드(2c)가 전기적 도전성와이어(40)에 의해 연결되고, 마더보드에 실장 가능한 섭스트레이트(10)가 구비되어 있다.In addition, the circuit pattern 22 of the signal transmission member 20 and the input / output pad 2c of the second semiconductor chip 2 are bonded to the first surface 1a of the first semiconductor chip 1. Substrates 10 connected by the electrically conductive wires 40 and mountable on the motherboard are provided.
마지막으로, 상기 제1반도체칩(1), 제2반도체칩(2), 신호전달부재(20), 전기적 도전성와이어(40) 및 섭스트레이트(10)의 일면을 봉지하는 봉지재(50)를 포함하여 일정 형태의 반도체패키지(101)를 이루고 있다.Finally, the encapsulant 50 encapsulating one surface of the first semiconductor chip 1, the second semiconductor chip 2, the signal transmission member 20, the electrically conductive wire 40, and the substrate 10. To form a semiconductor package 101.
도3a는 본 발명에 의한 다른 반도체패키지(102)를 도시한 단면도이고, 도3b는 도3a에서 제2반도체칩(2) 및 봉지재(50) 등이 제거된 상태의 평면도이다.3A is a cross-sectional view showing another semiconductor package 102 according to the present invention, and FIG. 3B is a plan view of the second semiconductor chip 2, the encapsulant 50, and the like removed from FIG. 3A.
먼저, 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)의 주연 근처에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)이 구비되어 있다.First, a first semiconductor chip 1 having a first plane 1a and a second plane 1b, which are substantially planar, and formed with a plurality of input / output pads 1c near the periphery of the second surface 1b. It is.
상기 제1반도체칩(1)의 제2면(1b)에는 하기 설명할 섭스트레이트에 일정한 전기적 신호를 전달하거나 또는 전달받을 수 있게 하는 신호전달부재(20)가 부착되어 있다. 즉, 상기 신호전달부재(20)는 일정크기의 관통공(23)이 형성된 수지층(21)을 기본층으로 하여, 상기 수지층(21)의 하면에는 상기 관통공(23)을 지나서 그 수지층(21)의 외주연까지 더 연장된 회로패턴(22)이 형성되어 있다. 물론,상기 수지층(21)의 관통공(23)은 상기 제1반도체칩(1)에 형성된 입출력패드(1c)의 위치와 대응되는 위치에 형성되어 있으며, 상기 관통공(23)에 위치된 회로패턴(22)은 상기 입출력패드(1c)와 접속되어 있다. 이때, 상기 회로패턴(22)과 입출력패드(1c) 사이의 본딩은 통상적인 탭본딩(TAP Bonding) 또는 갱본딩(Gang Bonding) 방법 등이 이용될 수 있다.The second surface 1b of the first semiconductor chip 1 is attached with a signal transmission member 20 for transmitting or receiving a predetermined electrical signal to the substrate to be described below. That is, the signal transmission member 20 has a resin layer 21 having a predetermined size of the through hole 23 as a base layer, and the number of the signal passing member 20 passes through the through hole 23 on the bottom surface of the resin layer 21. The circuit pattern 22 further extended to the outer periphery of the ground layer 21 is formed. Of course, the through hole 23 of the resin layer 21 is formed at a position corresponding to the position of the input / output pad 1c formed in the first semiconductor chip 1, and is located in the through hole 23. The circuit pattern 22 is connected to the input / output pad 1c. At this time, the bonding between the circuit pattern 22 and the input / output pad 1c may be a conventional tap bonding or gang bonding method.
계속해서, 대략 평면인 제1면(2a)과 제2면(2b)을 가지고, 상기 제2면(2b)의 주연 근처에는 다수의 입출력패드(2c)가 형성되어 있으며, 상기 제1면(2a)이 상기 신호전달부재(20)에 접착된 제2반도체칩(2)이 구비되어 있다.Subsequently, the first surface 2a and the second surface 2b are substantially planar, and a plurality of input / output pads 2c are formed near the periphery of the second surface 2b, and the first surface ( 2a) is provided with a second semiconductor chip (2) bonded to the signal transmission member (20).
이때 상기 신호전달부재(20)는 상부에 수지층(21)이 위치되고, 상기 수지층(21)의 하부에 회로패턴(22)이 형성되어 있음으로써, 상기 제2반도체칩(2)과 상기 신호전달부재(20)의 회로패턴(22)은 상호 간섭하거나, 쇼트되지 않게 된다.In this case, since the resin layer 21 is positioned above the signal transmission member 20 and the circuit pattern 22 is formed below the resin layer 21, the second semiconductor chip 2 and the The circuit patterns 22 of the signal transmission member 20 do not interfere with each other or short.
따라서, 상기 제2반도체칩(2)의 크기 또는 부피는 상기 제1반도체칩(1)의 크기 또는 부피와 같거나, 크거나 또는 작을 수 있다. 즉, 어떠한 크기의 제2반도체칩(2)도 상기 신호전달부재(20) 상에 위치될 수 있게 된다.Therefore, the size or volume of the second semiconductor chip 2 may be equal to, greater than or less than, the size or volume of the first semiconductor chip 1. That is, the second semiconductor chip 2 of any size may be located on the signal transmission member 20.
계속해서, 상기 제1반도체칩(1)의 제1면(1a)에는 접착층으로 섭스트레이트가 접착되어 있는데, 도면에서는 상기 섭스트레이트의 한 예로서 인쇄회로기판(10)이 도시되어 있다.Subsequently, the substrate is bonded to the first surface 1a of the first semiconductor chip 1 by an adhesive layer. In the drawing, the printed circuit board 10 is shown as an example of the substrate.
상기 섭스트레이트는 대략 평면인 제1면(11a)과 제2면(11b)을 갖는 수지층(11)을 중심으로, 상기 제1면(11a)에는 볼랜드(12b)를 갖고 상기 제2면(11b)에는 본드핑거(12a)를 갖는 회로패턴(12)이 형성되어 있다. 상기 회로패턴(12)은주지된 바와 같이 구리박막(Cu Foil)이며, 이러한 구조는 인쇄회로기판(10)뿐만 아니라, 써킷필름 또는 써킷테이프도 가능하다. 여기서, 상기 섭스트레이트로서 인쇄회로기판, 써킷필름, 또는 써킷테이프 모두 가능하며, 어느 하나로 한정하는 것은 아니다.The substrate has a resin layer 11 having a first plane 11a and a second plane 11b that are substantially planar, and has a ball land 12b on the first plane 11a and the second plane ( 11b), a circuit pattern 12 having a bond finger 12a is formed. The circuit pattern 12 is a copper foil (Cu Foil), as is known, this structure may be not only a printed circuit board 10, but also a circuit film or a circuit tape. Here, the substrate may be a printed circuit board, a circuit film, or a circuit tape, but is not limited thereto.
또한, 상기 인쇄회로기판(10)은 상기 수지층(11)의 제1면(11a)과 제2면(11b)에 형성된 회로패턴(12)이 도전성 비아홀(13)에 의해 상호 연결되어 있으며, 상기 볼랜드(12b) 및 본드핑거(12a)를 제외한 회로패턴(12) 및 수지층(11) 표면은 커버코트(14)로 코팅되어 있다. 상기 커버코트(14)는 통상적인 절연성 고분자 수지이다.In addition, the printed circuit board 10 has circuit patterns 12 formed on the first and second surfaces 11a and 11b of the resin layer 11 connected to each other by conductive via holes 13. The surface of the circuit pattern 12 and the resin layer 11 except for the borland 12b and the bond finger 12a is coated with a cover coat 14. The cover coat 14 is a conventional insulating polymer resin.
또한, 상기 제1반도체칩(1)의 입출력패드(1c)는 상기한 신호전달부재(20)의 회로패턴을 통하여, 상기 제2반도체칩(2)의 입출력패드(2c)는 도전성와이어(40)를 통하여 상기 인쇄회로기판의 (10)의 본드핑거(12a)에 접속되어 있다. 물론, 상기 도전성와이어(40)는 통상적인 골드와이어(Au Wire) 또는 알루미늄와이어(Al Wire)이다.In addition, the input / output pad 1c of the first semiconductor chip 1 is connected to the input / output pad 2c of the second semiconductor chip 2 through the circuit pattern of the signal transmission member 20. Is connected to the bond finger 12a of (10) of the printed circuit board. Of course, the conductive wire 40 is a conventional gold wire (Au Wire) or aluminum wire (Al Wire).
또한, 상기 제1반도체칩(1), 제2반도체칩(2), 신호전달부재, 도전성와이어(40)와 상기 인쇄회로기판(10)의 일면은 에폭시 몰딩 컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top)과 같은 봉지재(50)로 봉지되어 상기의 것들이 외부환경으로부터 보호되도록 되어 있다.In addition, one surface of the first semiconductor chip 1, the second semiconductor chip 2, the signal transmission member, the conductive wire 40, and the printed circuit board 10 may be formed of an epoxy molding compound or a globtop. It is encapsulated with an encapsulant 50 such as (Glop Top) so that the above are protected from the external environment.
마지막으로, 상기 인쇄회로기판(10)의 볼랜드(12b)에는 솔더볼과 같은 도전성볼(60)이 융착되어 차후 마더보드(Mother Board)에 실장 가능하게 되어 있다.Finally, conductive balls 60, such as solder balls, are fused to the ball lands 12b of the printed circuit board 10 to be mounted on a motherboard later.
계속해서, 도4의 반도체패키지(103)에서와 같이 섭스트레이트로서 다수의 리드(70)가 이용될 수도 있다. 즉, 대략 평면인 상면과 하면을 갖고, 상기 상면에는 봉지재(50) 외부로 노출된 랜드(71a)가 형성되고, 상기 하면에는 제1반도체칩(1) 및 제2반도체칩(2)과 전기적으로 접속되는 본드핑거(71b)를 갖는 구리(Cu) 또는 철(Fe) 계열의 리드(70)일 수도 있다.Subsequently, as in the semiconductor package 103 of FIG. 4, a plurality of leads 70 may be used as the substrate. That is, the land 71a has an upper surface and a lower surface that are substantially planar, and the land 71a exposed to the outside of the encapsulant 50 is formed on the upper surface, and the first semiconductor chip 1 and the second semiconductor chip 2 are formed on the lower surface. It may be a copper (Cu) or iron (Fe) series lead 70 having a bond finger 71b electrically connected thereto.
여기서, 상기 랜드(71a)를 제외한 리드(70)의 하면은 화학용액에 의한 부분 에칭 또는 할프 에칭(Half Etching)에 의해 그 두께가 더 얇게 되어 있음으로써 상기 랜드(71a)만이 봉지재(50) 외측으로 노출되고, 나머지 부분은 봉지재(50) 내측에 위치하게 된다. 따라서 상기 리드(70)는 봉지재(50)로부터 쉽게 이탈되거나 빠지지 않게 된다.Here, the thickness of the lower surface of the lead 70 except for the land 71a is thinner by partial etching or half etching with a chemical solution, so that only the land 71a is encapsulant 50. Exposed to the outside, the remaining portion is located inside the encapsulant 50. Therefore, the lead 70 is not easily separated or removed from the encapsulant 50.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 반도체패키지에 의하면, 제1반도체칩의 제2면에 수지층에 의해 보호되는 신호전달부재가 위치되고, 그 신호전달부재에 제2반도체칩이 접착됨으로써, 상기 제2반도체칩과 상기 신호전달부재(회로패턴) 사이의 상호 간섭이나, 쇼트 등이 발생할 여지가 없는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, a signal transmission member protected by a resin layer is positioned on a second surface of the first semiconductor chip, and the second semiconductor chip is bonded to the signal transmission member. There is no effect that there is no room for mutual interference or short between the signal transmission member (circuit pattern).
또한, 제1반도체칩의 크기에 대하여 상대적으로 다양한 크기의 제2반도체칩을 적층할 수 있음으로써, 고용량 고기능의 반도체패키지를 제공하게 되고, 또한섭스트레이트의 패턴 설계 자유도도 높아지는 효과가 있다.In addition, by stacking second semiconductor chips of various sizes relative to the size of the first semiconductor chip, it is possible to provide a high-capacity, high-functional semiconductor package, and also to increase the degree of freedom of pattern design of the substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| KR970024122A (en) * | 1995-10-30 | 1997-05-30 | 김광호 | Stacked Chip Packages with Same Bonding Direction |
| JPH11121496A (en) * | 1997-10-14 | 1999-04-30 | Rohm Co Ltd | Mounting structure of semiconductor chip and semiconductor device |
| KR19990069438A (en) * | 1998-02-09 | 1999-09-06 | 김영환 | Chip stack package |
| JPH11340410A (en) * | 1998-05-22 | 1999-12-10 | Sony Corp | Mounting structure for integrated circuit |
| JP2000183275A (en) * | 1998-12-11 | 2000-06-30 | Mitsui High Tec Inc | Semiconductor device |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| KR970024122A (en) * | 1995-10-30 | 1997-05-30 | 김광호 | Stacked Chip Packages with Same Bonding Direction |
| JPH11121496A (en) * | 1997-10-14 | 1999-04-30 | Rohm Co Ltd | Mounting structure of semiconductor chip and semiconductor device |
| KR19990069438A (en) * | 1998-02-09 | 1999-09-06 | 김영환 | Chip stack package |
| JPH11340410A (en) * | 1998-05-22 | 1999-12-10 | Sony Corp | Mounting structure for integrated circuit |
| JP2000183275A (en) * | 1998-12-11 | 2000-06-30 | Mitsui High Tec Inc | Semiconductor device |
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