KR100542673B1 - Semiconductor package - Google Patents

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KR100542673B1
KR100542673B1 KR1020000046957A KR20000046957A KR100542673B1 KR 100542673 B1 KR100542673 B1 KR 100542673B1 KR 1020000046957 A KR1020000046957 A KR 1020000046957A KR 20000046957 A KR20000046957 A KR 20000046957A KR 100542673 B1 KR100542673 B1 KR 100542673B1
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semiconductor chip
semiconductor
input
semiconductor package
encapsulant
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KR1020000046957A
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Korean (ko)
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KR20020013286A (en
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도병태
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 반도체패키지에 관한 것으로, 반도체패키지의 부피 변화없이 복수의 반도체패키지를 적층할 수 있는 동시에 실장밀도를 극대화하고 고기능화를 구현할 수 있도록, 하면에 다수의 입출력 패드가 형성된 제1반도체칩과, 상기 제1반도체칩의 외주연에 대략 방사상으로 형성된 다수의 내부리드와, 상기 내부리드로부터 외측으로 연장된 외부리드와, 상기 제1반도체칩의 입출력패드와 내부리드를 전기적으로 접속시키는 다수의 도전성와이어와, 상기 제1반도체칩, 도전성와이어 및 내부리드 등을 봉지하는 봉지재로 이루어진 반도체패키지에 있어서, 상기 봉지재의 상면에는 일정깊이의 요부(凹部)가 형성되고, 상기 요부 내측에는 상기 제1반도체칩의 상면과 접착제로 접착되며, 상,하면에는 회로패턴이 형성된 회로기판이 위치되고, 상기 회로기판의 상면에는 다수의 입출력패드가 형성된 제2반도체칩이 적어도 하나 이상 위치되어 있으며, 상기 제2반도체칩의 입출력패드는 도전성볼에 의해 상기 회로기판의 회로패턴에 전기적으로 접속된 것을 특징으로 함.The present invention relates to a semiconductor package, comprising: a first semiconductor chip having a plurality of input / output pads formed on a lower surface thereof so as to stack a plurality of semiconductor packages without changing the volume of the semiconductor package, and to maximize mounting density and to realize high functionality; A plurality of inner leads formed substantially radially on an outer circumference of the first semiconductor chip, an outer lead extending outwardly from the inner lead, and a plurality of conductive lines electrically connecting the input / output pad and the inner lead of the first semiconductor chip. A semiconductor package including a wire and an encapsulant for encapsulating the first semiconductor chip, the conductive wire, the inner lead, and the like, wherein a concave portion having a predetermined depth is formed on an upper surface of the encapsulant, and the first portion is formed inside the concave portion. The upper and lower surfaces of the semiconductor chip are bonded with an adhesive, and upper and lower surfaces of the circuit board are provided with circuit patterns. At least one second semiconductor chip having a plurality of input / output pads is positioned on an upper surface of the plate, and the input / output pad of the second semiconductor chip is electrically connected to a circuit pattern of the circuit board by conductive balls. .

Description

반도체패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

도1은 종래의 통상적인 리드프레임을 이용한 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor package using a conventional lead frame.

도2는 본 발명의 제1실시예에 의한 반도체패키지를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package according to a first embodiment of the present invention.

도3은 본 발명의 제2실시예에 의한 반도체패키지를 도시한 단면도이다.3 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention.

도4는 본 발명의 제3실시예에 의한 반도체패키지를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package according to a third embodiment of the present invention.

도5는 본 발명의 제4실시예에 의한 반도체패키지를 도시한 단면도이다.5 is a cross-sectional view showing a semiconductor package according to a fourth embodiment of the present invention.

도6은 본 발명의 제5실시예에 의한 반도체패키지를 도시한 단면도이다.6 is a cross-sectional view showing a semiconductor package according to a fifth embodiment of the present invention.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

100'; 종래의 반도체패키지100 '; Conventional Semiconductor Package

101~105; 본 발명에 의한 반도체패키지101-105; Semiconductor package according to the present invention

1; 제1반도체칩 2; 제2반도체칩One; A first semiconductor chip 2; Second semiconductor chip

3; 제3반도체칩 1a, 2a, 3a; 입출력패드3; Third semiconductor chip 1a, 2a, 3a; I / O pad

4; 내부리드 6; 외부리드4; Internal lead 6; External lead

8; 도전성와이어 10; 회로기판8; Conductive wire 10; Circuit board

11; 수지층 12; 회로패턴11; Resin layer 12; Circuit pattern

13; 비아홀 16; 도전성볼13; Via hole 16; Conductive ball

18,20; 봉지재 18a; 요부18,20; Encapsulant 18a; waist

22; 글래스 24; 렌즈22; Glass 24; lens

본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 반도체패키지의 부피 변화없이 복수의 반도체패키지를 적층할 수 있는 동시에, 실장밀도를 극대화하고 고기능화를 구현할 수 있는 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of stacking a plurality of semiconductor packages without changing the volume of the semiconductor package, maximizing the mounting density and implementing high functionality.

통상 반도체패키지는 반도체칩을 외부 환경으로부터 안전하게 보호함은 물론, 그 반도체칩과 마더보드(Mother Board)와의 전기적 신호가 용이하게 교환되도록 한 장치를 말한다.In general, a semiconductor package refers to a device that not only protects a semiconductor chip from an external environment but also easily exchanges electrical signals between the semiconductor chip and a motherboard.

이러한 반도체패키지로서 종래 리드프레임을 이용한 통상적인 반도체패키지(100')를 도1에 도시하였으며 그 구조를 간단히 설명하면 다음과 같다.As such a semiconductor package, a conventional semiconductor package 100 'using a conventional lead frame is shown in FIG. 1, and the structure thereof will be briefly described as follows.

도시된 바와 같이 상면에 다수의 입출력패드(2a')가 형성된 반도체칩(2')과, 접착제가 개재되어 상기 반도체칩(2')이 탑재되는 칩탑재판(5')과, 상기 칩탑재판(5')의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드(4')와, 상기 내부리드(4')로부터 외측으로 연장된 외부리드(6')와, 상기 반도체칩(2')과 내부리드(4')를 전기적으로 접속시키는 다수의 도전성와이어(8')와, 상기 반도체칩(2'), 도전성와이어(8'), 칩탑재판(5') 및 내부리드(4') 등을 외부 환경으로부터 보호하 는 봉지재(10')로 이루어져 있다.As shown, a semiconductor chip 2 'having a plurality of input / output pads 2a' formed on an upper surface thereof, a chip mounting plate 5 'on which the semiconductor chip 2' is mounted with an adhesive interposed therebetween, and the chip mounting. A plurality of inner leads 4 'formed at a predetermined distance apart from the outer circumference of the plate 5', an outer lead 6 'extending outward from the inner lead 4', and the semiconductor chip 2 '. ) And a plurality of conductive wires 8 'electrically connecting the inner lead 4', the semiconductor chip 2 ', the conductive wire 8', the chip mounting plate 5 'and the inner lead 4'. ') Consists of an encapsulant (10') to protect the environment from the outside.

이러한 반도체패키지(100')는 봉지재(10') 외측으로 연장된 외부리드(6')가 솔더에 의해 마더보드에 실장된다. 또한 반도체칩과 마더보드 사이의 신호 교환은 도전성와이어, 내부리드 및 외부리드를 통해서 이루어진다.In the semiconductor package 100 ', an outer lead 6' extending outside the encapsulant 10 'is mounted on the motherboard by soldering. In addition, signal exchange between the semiconductor chip and the motherboard is performed through conductive wires, inner leads and outer leads.

이상에서와 같은 리드프레임을 이용한 반도체패키지는 최종 입출력수단인 외부리드가 봉지재 외주연으로 연장된 채 마더보드에 실장됨으로써 반도체패키지가 마더보드에서 차지하는 면적이 커지는(실장밀도가 작아지는) 문제가 있다. 상기와 같이 하여, 그 반도체패키지의 실장밀도가 작기 때문에 전자부품의 고기능화를 구현하기 위해서는 그 전자부품의 크기 내지 부피가 커져야 하는 문제도 있다.As described above, the semiconductor package using the lead frame has a problem that the semiconductor package occupies a large area on the motherboard (the mounting density decreases) because the external lead as the final input / output means is mounted on the motherboard with the outer peripheral edge of the encapsulant extending. have. As described above, since the mounting density of the semiconductor package is small, there is also a problem that the size or volume of the electronic component must be large in order to realize high functionalization of the electronic component.

최근에는 마더보드에의 실장밀도를 높이는 동시에 반도체패키지의 고기능화를 위해 적층형 반도체패키지가 제조되고 있다.Recently, laminated semiconductor packages have been manufactured to increase the mounting density on the motherboard and to improve the functionality of the semiconductor packages.

그러나, 이러한 적층형 반도체패키지는 대부분 동일한 형태의 반도체패키지를 적층하는 구조로 되어 있음으로써, 그 부피 즉, 반도체패키지의 높이가 높아지는 단점이 있다. 이렇게 반도체패키지의 높이가 커지게 되면 비록 실장밀도나 전기적 성능을 높일 수는 있지만, 결국 그 반도체패키지가 실장되는 전자부품의 부피 또는 높이가 커지는 문제가 있다.However, such stacked semiconductor packages have a structure in which most of the same type semiconductor packages are stacked, so that the volume, that is, the height of the semiconductor package is increased. As the height of the semiconductor package increases, the mounting density and the electrical performance may be increased, but the volume or height of the electronic component on which the semiconductor package is mounted increases.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 부피 변화없이 복수의 반도체패키지를 적층할 수 있는 동시에, 실장밀도를 극대화하고 고기능화를 구현할 수 있는 반도체패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-described problems, and to provide a semiconductor package that can be stacked a plurality of semiconductor packages without changing the volume, maximizing the mounting density and high functionality.

상기한 목적을 달성하기 위해 본 발명은 하면에 다수의 입출력 패드가 형성된 제1반도체칩과, 상기 제1반도체칩의 외주연에 대략 방사상으로 형성된 다수의 내부리드와, 상기 내부리드로부터 외측으로 연장된 외부리드와, 상기 제1반도체칩의 입출력패드와 내부리드를 전기적으로 접속시키는 다수의 도전성와이어와, 상기 제1반도체칩, 도전성와이어 및 내부리드 등을 봉지하는 봉지재로 이루어진 반도체패키지에 있어서, 상기 봉지재의 상면에는 일정깊이의 요부(凹部)가 형성되고, 상기 요부 내측에는 상기 제1반도체칩의 상면과 접착제로 접착되며, 상,하면에는 회로패턴이 형성된 회로기판이 위치되고, 상기 회로기판의 상면에는 다수의 입출력패드가 형성된 제2반도체칩이 적어도 하나 이상 위치되어 있으며, 상기 제2반도체칩의 입출력패드는 도전성볼에 의해 상기 회로기판의 회로패턴에 전기적으로 접속된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device comprising: a first semiconductor chip having a plurality of input / output pads formed on a bottom surface thereof, a plurality of inner leads formed substantially radially on an outer circumference of the first semiconductor chip, and extending outwardly from the inner lead; A semiconductor package comprising a plurality of conductive wires electrically connecting the external leads, the input / output pads of the first semiconductor chip, and the internal leads, and an encapsulant for encapsulating the first semiconductor chip, the conductive wires, the internal leads, and the like. A recess having a predetermined depth is formed on an upper surface of the encapsulant, and an inner surface of the recess is bonded to the upper surface of the first semiconductor chip by an adhesive, and a circuit board on which a circuit pattern is formed is located on the upper and lower surfaces of the encapsulant. At least one second semiconductor chip having a plurality of input / output pads is positioned on the upper surface of the substrate, and the input / output pad of the second semiconductor chip is By seongbol characterized in that electrically connected to the circuit pattern of the circuit board.

여기서, 상기 제2반도체칩의 외주연은 또다른 봉지재로 봉지될 수도 있다.Here, the outer circumference of the second semiconductor chip may be sealed with another encapsulant.

또한, 상기 제2반도체칩의 상면에는 다수의 입출력패드가 형성된 제3반도체칩이 접착제로 접착되어 있고, 상기 제3반도체칩의 입출력패드는 상기 회로기판의 회로패턴 또는 상기 내부리드의 상면에 도전성와이어로 접속된 것을 특징으로 한다.In addition, a third semiconductor chip having a plurality of input / output pads is adhered to the upper surface of the second semiconductor chip with an adhesive, and the input / output pad of the third semiconductor chip is conductive to the circuit pattern of the circuit board or the upper surface of the inner lead. It is characterized by connecting with a wire.

또한, 상기 요부의 상부에는 그 상부를 덮는 글래스가 더 형성될 수 있고, 상기 글래스의 중앙에는 렌즈가 더 형성될 수도 있다.In addition, a glass covering the upper portion of the recess may be further formed, and a lens may be further formed in the center of the glass.

또한, 상기 요부 전체에도 또다른 봉지재가 충진될 수도 있다.In addition, another encapsulant may be filled in the entire recess.

상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 반도체패키지의 부피 특히 높이를 종래와 같이 유지하면서도 소위 적층된 형태의 반도체패키지를 구현함으로써 실장밀도를 높이는 동시에 반도체패키지의 고기능화를 구현할 수 있게 된다. 결국, 상기 반도체패키지를 사용한 전자 부품은 그 크기를 더욱 소형화하는 동시에, 고기능화할 수 있게 된다.According to the semiconductor package according to the present invention as described above, while maintaining the volume, in particular the height of the semiconductor package as in the prior art, by implementing a so-called stacked semiconductor package it is possible to increase the mounting density and at the same time to realize high functionalization of the semiconductor package. As a result, the electronic component using the semiconductor package can be further downsized and highly functional.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2는 본 발명의 제1실시예에 의한 반도체패키지(101)를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package 101 according to a first embodiment of the present invention.

먼저 하면에 다수의 입출력패드(1a)가 형성된 제1반도체칩(1)이 위치되어 있고, 상기 제1반도체칩(1)을 중심으로 그 외측을 향하는 두방향 또는 네방향으로 다수의 내부리드(4)가 위치되어 있다. 또한 상기 내부리드(4) 각각에는 외측으로 외부리드(6)가 연장되어 있다. 상기 제1반도체칩(1)의 입출력패드(1a)와 내부리드(4)는 골드와이어 또는 알루미늄 와이와 같은 도전성와이어(8)에 의해 서로 접속되어 있다. 또한 상기 제1반도체칩(1), 도전성와이어(8) 및 내부리드(4) 등은 외부환경으로부터 보호되도록 에폭시몰딩컴파운드와 같은 봉지재(18)로 봉지되어 있다.First, a first semiconductor chip 1 having a plurality of input / output pads 1a formed thereon is positioned, and a plurality of internal leads are formed in two or four directions toward the outside of the first semiconductor chip 1. 4) is located. In addition, an outer lead 6 extends outwardly to each of the inner leads 4. The input / output pad 1a and the inner lead 4 of the first semiconductor chip 1 are connected to each other by a conductive wire 8 such as a gold wire or an aluminum wire. In addition, the first semiconductor chip 1, the conductive wire 8, the inner lead 4 and the like are encapsulated with an encapsulant 18 such as an epoxy molding compound so as to be protected from the external environment.

여기서, 상기 내부리드(4) 및 외부리드(6)는 주지된 바와 같이 구리(Cu), 구리 합금 계열 또는 철/니켈(Fe/Ni) 합금 계열로 제조된 통상의 리드프레임을 이용한 것이다.Herein, the inner lead 4 and the outer lead 6 use a conventional lead frame made of copper (Cu), a copper alloy series or an iron / nickel (Fe / Ni) series.

계속해서, 상기 제1반도체칩(1)의 상면인 봉지재(18)의 상부에는 일정크기 및 깊이를 갖는 요부(18a)(凹部)가 형성되어 있으며, 상기 요부(18a) 내측에는 회로기판(10)이 위치되어 있다. 상기 회로기판(10)은 수지층(11) 또는 필름, 테이프 등을 중심으로 그 상,하면에 도전성 회로패턴(12)이 형성되어 있으며, 상기 상,하면의 회로패턴(12)은 도전성 비아홀(13)에 의해 상호 연결되어 있다.Subsequently, recessed portions 18a having a predetermined size and depth are formed on an upper portion of the encapsulant 18, which is an upper surface of the first semiconductor chip 1, and a circuit board is formed inside the recessed portions 18a. 10) is located. The circuit board 10 has a conductive circuit pattern 12 formed on and under the resin layer 11, a film, a tape, and the like, and the circuit patterns 12 on the upper and lower surfaces are formed of conductive via holes ( 13) are interconnected.

또한, 상기 회로기판(10)은 하면이 상기 제1반도체칩(1)의 상면과 접착수단으로 접착되어 있으며, 그 회로기판(10)의 둘레는 봉지재(18) 내측에 위치되어 있다. 물론, 상기 회로기판(10)의 하면에 형성된 회로패턴(12)은 솔더와 같은 도전성 부재(도시되지 않음)에 의해 소정의 내부리드(4) 상면에 접속되어 있다.In addition, a bottom surface of the circuit board 10 is bonded to the top surface of the first semiconductor chip 1 by an adhesive means, and the periphery of the circuit board 10 is located inside the encapsulant 18. Of course, the circuit pattern 12 formed on the lower surface of the circuit board 10 is connected to the upper surface of the predetermined inner lead 4 by a conductive member (not shown) such as solder.

한편, 상기 회로기판(10)의 상면에는 상기 회로기판(10)을 향하여 다수의 입출력패드(2a)가 형성된 제2반도체칩(2)이 위치되어 있으며, 이 제2반도체칩(2)의 입출력패드(2a)는 골드볼 또는 솔더볼과 같은 도전성볼(16)에 의해 상기 회로기판(10)의 회로패턴(12)에 전기적으로 접속되어 있다.On the other hand, a second semiconductor chip 2 having a plurality of input / output pads 2a is positioned on the upper surface of the circuit board 10 and the input / output of the second semiconductor chip 2 is located. The pad 2a is electrically connected to the circuit pattern 12 of the circuit board 10 by conductive balls 16 such as gold balls or solder balls.

또한, 상기 제2반도체칩(2)의 상면에는 접착수단으로 제3반도체칩(3)이 접착되어 있다. 상기 제3반도체칩(3)은 상면에 다수의 입출력패드(3a)가 형성되어 있으며, 이 입출력패드(3a)는 도전성와이어(8)에 의해 상기 회로기판(10)의 회로패턴(12)에 접속되어 있다.In addition, the third semiconductor chip 3 is bonded to the upper surface of the second semiconductor chip 2 by an adhesive means. The third semiconductor chip 3 has a plurality of input / output pads 3a formed on an upper surface thereof, and the input / output pads 3a are formed on the circuit pattern 12 of the circuit board 10 by conductive wires 8. Connected.

마지막으로 상기 요부(18a)의 상부에는 투명한 글래스(22)가 부착되어 있으며, 이와 같이 글래스(22)가 부착된 경우에 상기 제3반도체칩(3)은 CCD(Charge Coupled Device)용 반도체칩이 되도록 함이 바람직하다. 또한, 상기 요부(18a)에는 상기 글래스(22) 대신 도시되지는 않았지만 또다른 봉지재가 충진될 수도 있다. 상 기 요부(18a)에 충진되는 봉지재는 통상적인 에폭시몰딩컴파운드가 될 수도 있으나 액상 봉지재를 이용함이 바람직하다.Finally, the transparent glass 22 is attached to the upper portion of the recessed portion 18a. When the glass 22 is attached, the third semiconductor chip 3 is a CCD (Charge Coupled Device) semiconductor chip. Preferably. In addition, the recessed portion 18a may be filled with another encapsulant although not shown in place of the glass 22. The encapsulant filled in the recess 18a may be a conventional epoxy molding compound, but it is preferable to use a liquid encapsulant.

여기서, 상기 제1반도체칩(1)의 전기적 신호는 도전성와이어(8), 내부리드(4) 및 외부리드(6)를 통하여 마더보드와 교신하게 되며, 제2반도체칩(2)의 전기적 신호는 도전성볼(16), 회로기판(10), 내부리드(4) 및 외부리드(6)를 통하여 마더보드와 교신하게 된다. 또한 제3반도체칩(3) 역시 도전성와이어(8), 회로기판(10), 내부리드(4) 및 외부리드(6)를 통해 마더보드와 교신하게 된다.Here, the electrical signal of the first semiconductor chip 1 is in communication with the motherboard through the conductive wire 8, the inner lead 4 and the outer lead 6, the electrical signal of the second semiconductor chip (2) Is communicated with the motherboard through the conductive ball 16, the circuit board 10, the inner lead (4) and the outer lead (6). In addition, the third semiconductor chip 3 also communicates with the motherboard through the conductive wire 8, the circuit board 10, the inner lead 4, and the outer lead 6.

도3은 본 발명의 제2실시예에 의한 반도체패키지(102)를 도시한 단면도이다. 이는 상기 제1실시예에 의한 반도체패키지(101)와 유사하므로 그 차이점만을 설명하기로 한다.3 is a cross-sectional view showing a semiconductor package 102 according to a second embodiment of the present invention. Since this is similar to the semiconductor package 101 according to the first embodiment, only the differences will be described.

도시된 바와 같이 회로기판(10)은 그 측부가 봉지재(18) 내측에 결합되어 있지 않고 회로기판(10) 전체가 요부(18a)를 통해 상부로 오픈되어 있다. 또한, 상기 요부(18a)를 통해 내부리드(4)의 일부 영역이 상부로 오픈되어 있다. 따라서, 제3반도체칩(3)의 입출력패드(3a)는 도전성와이어(8)에 의해 회로기판(10)의 회로패턴(12)에 접속될 수도 있지만 직접 내부리드(4)의 상면에 접속되는 구조가 가능하다. 따라서, 상기 제3반도체칩(3)에서 마더보드까지의 전기적 경로를 짧게 하는 것이 가능하다.As shown, the side of the circuit board 10 is not coupled to the inside of the encapsulant 18, and the entire circuit board 10 is opened upwardly through the recessed part 18a. In addition, a part of the inner lead 4 is opened upward through the recessed portion 18a. Accordingly, the input / output pad 3a of the third semiconductor chip 3 may be connected to the circuit pattern 12 of the circuit board 10 by the conductive wires 8, but is directly connected to the upper surface of the inner lead 4. The structure is possible. Therefore, it is possible to shorten the electrical path from the third semiconductor chip 3 to the motherboard.

도4는 본 발명의 제3실시예에 의한 반도체패키지(103)를 도시한 단면도이다. 상기 반도체패키지(103)는 제1실시예에 의한 반도체패키지(101)와 다르게 글래스(22) 중앙에 렌즈(24)가 더 형성되어 있다. 따라서 제3반도체칩(3)이 CCD용 반도체칩일 경우 외부의 넓은 영역을 센싱할 수 있게 된다.4 is a cross-sectional view showing a semiconductor package 103 according to a third embodiment of the present invention. Unlike the semiconductor package 101 according to the first embodiment, the semiconductor package 103 further includes a lens 24 formed at the center of the glass 22. Therefore, when the third semiconductor chip 3 is a CCD semiconductor chip, a large external area can be sensed.

도5는 본 발명의 제4실시예에 의한 반도체패키지(104)를 도시한 단면도이다. 이것 역시 제1실시예에 의한 반도체패키지(101)와 유사하므로 그 차이점만을 설명하기로 한다. 도시된 바와 같이 제1반도체칩(1)의 상면에는 회로기판(10)이 위치되어 있고, 그 회로기판(10)의 상부에는 제2반도체칩(2)만이 위치되어 있다. 상기 제2반도체칩(2)은 하면에 입출력패드(2a)가 형성되어 있고, 그 입출력패드(2a)는 도전성볼(16)에 의해 상기 회로기판(10)의 회로패턴(12)에 접속되어 있다. 상기 제2반도체칩(2)은 도전성볼(16) 대신 입출력패드(2a)가 상부에 위치하도록 하여 도전성와이어에 의해 그 회로기판(10)의 회로패턴(12)에 연결시킬 수 도 있다.5 is a cross-sectional view showing a semiconductor package 104 according to a fourth embodiment of the present invention. This is also similar to the semiconductor package 101 according to the first embodiment, so only the differences will be described. As illustrated, a circuit board 10 is positioned on the top surface of the first semiconductor chip 1, and only the second semiconductor chip 2 is positioned on the circuit board 10. The second semiconductor chip 2 has an input / output pad 2a formed on a lower surface thereof, and the input / output pad 2a is connected to the circuit pattern 12 of the circuit board 10 by a conductive ball 16. have. The second semiconductor chip 2 may be connected to the circuit pattern 12 of the circuit board 10 by conductive wires such that the input / output pad 2a is positioned above the conductive ball 16.

또한, 상기 제2반도체칩(2)의 외주연은 봉지재(20) 바람직하기로는 액상 봉지재에 의해 감싸여져 있다. 여기서, 상기 도면에서는 제2반도체칩(2)이 봉지재(20)로 봉지되어 있으나, 그 요부(18a) 내측 전체가 봉지재로 봉지될 수 도 있다.In addition, the outer circumference of the second semiconductor chip 2 is surrounded by the encapsulant 20, preferably a liquid encapsulant. Here, although the second semiconductor chip 2 is encapsulated with the encapsulant 20, the entire inner portion of the recess 18a may be encapsulated with the encapsulant.

도6은 본 발명의 제5실시예에 의한 반도체패키지(105)를 도시한 단면도이다. 여기서는 상기 제2반도체칩(2)이 동일 평면상에 다수개 위치된 것이 특징이다. 즉, 회로기판(10)의 상면에는 다수개의 제2반도체칩(2)이 위치될 수 있으며, 이 제2반도체칩(2)은 모두 도전성볼(16)에 의해 회로기판(10)에 접속되어 있다. 상기 제2반도체칩(2)은 도전성볼(16) 대시 대신 도전성와이어(8)에 의해서도 그 회로기판(10)에 연결되어 있다. 물론, 상기 다수의 제2반도체칩(2)은 모두 봉지재(20)에 의해 감싸여져 있다.6 is a cross-sectional view showing a semiconductor package 105 according to a fifth embodiment of the present invention. In this case, the plurality of second semiconductor chips 2 are located on the same plane. That is, a plurality of second semiconductor chips 2 may be positioned on the upper surface of the circuit board 10, and the second semiconductor chips 2 are all connected to the circuit board 10 by conductive balls 16. have. The second semiconductor chip 2 is also connected to the circuit board 10 by the conductive wire 8 instead of the conductive ball 16 dash. Of course, the plurality of second semiconductor chips 2 are all wrapped by the encapsulant 20.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 반도체패키지에 의하면, 반도체패키지의 부피 특히 높이를 종래와 동일하게 유지하면서도 소위 적층된 형태의 반도체패키지를 구현함으로써 실장밀도를 높이는 동시에 반도체패키지의 고기능화를 구현할 수 있는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, while maintaining the volume, in particular, the height of the semiconductor package as in the prior art, by implementing a so-called stacked semiconductor package there is an effect that it is possible to increase the mounting density and high functionality of the semiconductor package.

또한, 상기 반도체패키지를 사용한 전자 부품은 그 크기를 더욱 소형화하는 동시에, 고기능화할 수 있는 효과도 있다.In addition, the electronic component using the semiconductor package has the effect of further downsizing the size and high functionality.

Claims (7)

하면에 다수의 입출력 패드가 형성된 제1반도체칩과, 상기 제1반도체칩의 외주연에 대략 방사상으로 형성된 다수의 내부리드와, 상기 내부리드로부터 외측으로 연장된 외부리드와, 상기 제1반도체칩의 입출력패드와 내부리드를 전기적으로 접속시키는 다수의 도전성와이어와, 상기 제1반도체칩, 도전성와이어 및 내부리드 등을 봉지하는 봉지재로 이루어진 반도체패키지에 있어서, A first semiconductor chip having a plurality of input / output pads formed on a lower surface thereof, a plurality of inner leads substantially radially formed on an outer circumference of the first semiconductor chip, an outer lead extending outwardly from the inner lead, and the first semiconductor chip A semiconductor package comprising a plurality of conductive wires electrically connecting an input / output pad and an inner lead of the semiconductor device, and an encapsulant for encapsulating the first semiconductor chip, the conductive wire, the inner lead, and the like. 상기 봉지재의 상면에는 일정깊이의 요부(凹部)가 형성되고, 상기 요부 내측에는 상기 제1반도체칩의 상면과 접착제로 접착되며, 상,하면에는 회로패턴이 형성된 회로기판이 위치되고, 상기 회로기판의 상면에는 다수의 입출력패드가 형성된 제2반도체칩이 적어도 하나 이상 위치되어 있으며, 상기 제2반도체칩의 입출력패드는 도전성볼에 의해 상기 회로기판의 회로패턴에 전기적으로 접속된 것을 특징으로 하는 반도체패키지.A recess having a predetermined depth is formed on an upper surface of the encapsulant, and an inner surface of the recess is bonded to the upper surface of the first semiconductor chip by an adhesive, and a circuit board on which a circuit pattern is formed is located on the upper and lower surfaces of the encapsulant. At least one second semiconductor chip having a plurality of input and output pads is located on the upper surface of the semiconductor chip, characterized in that the input and output pads of the second semiconductor chip is electrically connected to the circuit pattern of the circuit board by a conductive ball package. 제1항에 있어서, 상기 제2반도체칩의 상면에는 다수의 입출력패드가 형성된 제3반도체칩이 접착제로 접착되어 있고, 상기 제3반도체칩의 입출력패드는 상기 회로기판의 회로패턴에 도전성와이어로 접속된 것을 특징으로 하는 반도체패키지.The semiconductor device of claim 1, wherein a third semiconductor chip having a plurality of input / output pads is bonded to an upper surface of the second semiconductor chip, and the input / output pad of the third semiconductor chip is formed of conductive wires on a circuit pattern of the circuit board. A semiconductor package, characterized in that connected. 제1항에 있어서, 상기 제2반도체칩의 상면에는 다수의 입출력패드가 형성된 제3반도체칩이 접착제로 접착되어 있고, 상기 제3반도체칩의 입출력패드는 상기 내 부리드의 상면에 도전성와이어로 접속된 것을 특징으로 하는 반도체패키지.The semiconductor device of claim 1, wherein a third semiconductor chip having a plurality of input / output pads is bonded to an upper surface of the second semiconductor chip, and the input / output pad of the third semiconductor chip is formed of a conductive wire on an upper surface of the inner lead. A semiconductor package, characterized in that connected. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 요부의 상부에는 그 상부를 덮는 글래스가 더 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package according to any one of claims 1 to 3, wherein a glass covering the upper portion of the recess is further formed. 제4항에 있어서, 상기 글래스의 중앙에는 렌즈가 더 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 4, wherein a lens is further formed at the center of the glass. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 요부에는 또다른 봉지재가 봉지된 것을 특징으로 하는 반도체패키지.The semiconductor package according to any one of claims 1 to 3, wherein the main portion is sealed with another encapsulant. 제1항에 있어서, 상기 제2반도체칩의 외주연은 또다른 봉지재로 봉지된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein an outer circumference of the second semiconductor chip is sealed with another encapsulant.
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JPS61150251A (en) * 1984-12-24 1986-07-08 Hitachi Ltd Semiconductor device
KR930014846A (en) * 1991-12-17 1993-07-23 문정환 Manufacturing method and structure of multi chip package (MCP)
KR930017152A (en) * 1992-01-24 1993-08-30 김광호 Semiconductor package
KR960019680A (en) * 1994-11-15 1996-06-17 문정환 Semiconductor device package method and device package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61150251A (en) * 1984-12-24 1986-07-08 Hitachi Ltd Semiconductor device
KR930014846A (en) * 1991-12-17 1993-07-23 문정환 Manufacturing method and structure of multi chip package (MCP)
KR930017152A (en) * 1992-01-24 1993-08-30 김광호 Semiconductor package
KR960019680A (en) * 1994-11-15 1996-06-17 문정환 Semiconductor device package method and device package

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