KR930014846A - Manufacturing method and structure of multi chip package (MCP) - Google Patents

Manufacturing method and structure of multi chip package (MCP) Download PDF

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Publication number
KR930014846A
KR930014846A KR1019910023255A KR910023255A KR930014846A KR 930014846 A KR930014846 A KR 930014846A KR 1019910023255 A KR1019910023255 A KR 1019910023255A KR 910023255 A KR910023255 A KR 910023255A KR 930014846 A KR930014846 A KR 930014846A
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KR
South Korea
Prior art keywords
paddle
lead frame
chips
semiconductor chip
attached
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Application number
KR1019910023255A
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Korean (ko)
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KR100239684B1 (en
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박준수
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문정환
금성일렉트론 주식회사
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Priority to KR1019910023255A priority Critical patent/KR100239684B1/en
Publication of KR930014846A publication Critical patent/KR930014846A/en
Application granted granted Critical
Publication of KR100239684B1 publication Critical patent/KR100239684B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 멀티칩패키지 제작방법 및 그 구조에 관한 것으로 멀티칩패키지구조에 있어서 리드프레임의 패들 윗면에 부착된 제1반도체 칩과 패들(11)의 아랫면에 부착된 제2반도체 칩과 그 제1, 제2반도체 칩들을 상기 패들이 상, 하면에 부착고정하기 위한 접착제와, 다이어태치된 상기 각 칩의 본드패드와 리드프레임의 인너리드를 전기적으로 접속연결시키는 복수개의 제1, 제2금속와이어와, 와이어본딩된 상기의 각 칩과, 리드프레임의 아웃리드를 포함하는 일정부위를 밀폐시키기 위한 에폭시몰딩컴파운드로 구성되어 있다. 상기 제1반도체 칩(12)은 패들(11)보다 크기를 작게하고 제2반도체 칩(12′)은 패들(11)보다 크기를 크게함이 바람직하며 상기 각 칩들에 구비된 복수개의 본드패드가 상호 수직이 되게 배열함이 바람직하다.The present invention relates to a method for fabricating a multichip package and a structure thereof. In a multichip package structure, a first semiconductor chip attached to an upper surface of a paddle of a lead frame and a second semiconductor chip attached to a lower surface of a paddle (11) and a first semiconductor chip attached thereto. And a plurality of first and second metal wires for electrically connecting and connecting second semiconductor chips to upper and lower surfaces of the paddle, and to electrically connect the bond pads of the die-attached chips and the inner leads of the lead frames. And an epoxy molding compound for sealing a predetermined portion including the wire lead and each of the above-mentioned chips and an outlead of the lead frame. The first semiconductor chip 12 may have a smaller size than the paddle 11, and the second semiconductor chip 12 ′ may have a larger size than the paddle 11. A plurality of bond pads may be provided in each of the chips. It is preferable to arrange them perpendicular to each other.

Description

멀티칩패키지(MCP) 제작방법 및 그 구조Manufacturing method and structure of multi chip package (MCP)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도 및 제4도는 본 발명에 의한 멀티칩패키지(MCP:Multi Chip Package)의 구성을 보이는 단면도 및 내부 평면도.3 and 4 are cross-sectional views and internal plan views showing the configuration of a multi chip package (MCP) according to the present invention.

Claims (4)

멀티칩패키지구조에 있어서 리드프레임의 패들(11) 윗면에 부착된 제1반도체 칩(12)과 패들(11)의 아랫면에 부착된 제2반도체 칩(12′)과 그 제1, 제2반도체 칩(12)(12′)들을 상기 패들(11)의 상, 하면에 부착고정하기 위한 접착제(13)와, 다이어태치된 상기 각 칩(12)(12′)의 본드패드(12a)(12a′)와 리드프레임의 인너리트(14)를 전기적으로 접속연결시키는 복수개의 제1, 제2금속와이어와(15)(15′), 와이어본딩된 상기의 각 칩(12)(12′)과, 리드프레임의 아웃리드(16)를 포함하는 일정부위를 밀폐시키기 위한 에폭시몰딩컴파운드(17)로 구비하여서 된 멀티칩패키지 구조.In the multi-chip package structure, the first semiconductor chip 12 attached to the upper surface of the paddle 11 of the lead frame and the second semiconductor chip 12 'attached to the lower surface of the paddle 11 and the first and second semiconductors thereof. Adhesive 13 for attaching and fixing the chips 12 and 12 'to the upper and lower surfaces of the paddle 11, and the bond pads 12a and 12a of each of the chips 12 and 12' to be attached. ′) And a plurality of first and second metal wires 15 and 15 ′ for electrically connecting and connecting the inner frame 14 of the lead frame with each of the above-mentioned chips 12 and 12 ′ wire-bonded with each other. And a multi-chip package structure provided with an epoxy molding compound 17 for sealing a predetermined portion including an out lead 16 of the lead frame. 제1항에 있어서 상기 제1반도체 칩(12)은 패들(11)보다 크기가 작고 제2반도체칩(12′)은 패들(11)보다 크기가 큰 것임을 특징으로 하는 멀티칩패키지 구조.The multichip package structure according to claim 1, wherein the first semiconductor chip (12) is smaller than the paddle (11) and the second semiconductor chip (12 ') is larger than the paddle (11). 제1항에 있어서 상기 제1, 제2반도체 칩(12)(12′)은 그에 구비된 복수개의 본드패드(12a)(12′a)가 서로수직이 되게 배열된 것임을 특징으로 하는 멀티칩패키지 구조..The multi-chip package according to claim 1, wherein the first and second semiconductor chips 12 and 12 'are arranged such that a plurality of bond pads 12a and 12'a provided therein are perpendicular to each other. rescue.. 멀티칩패키지 제작방법에 있어서 소잉공정에 의해 개개로 분리된 제1, 제2반도체 칩(12a)(12′a)을 리드프레임의 패들(11) 양쪽면에 접착제(13)를 이용하여 각각 부착고정하는 다이어태치공정과 다이어태치된 각각의 칩(12)(12′)에 구비된 복수개의 본드패드(12a)(12′a)와 상기 리드프레임의 인너리드(14)를 제1, 제2금속와이어(15)(15′)를 이용하여 전기적으로 접속연결시키는 와이어본딩공정과, 와이어본딩된 상기 각 칩(12)(12′)과 리드프레임의 아웃리드(16)를 포함하는 일정부위를 에폭시몰딩컴파운드(17)로 밀폐시키는 몰딩공정과 리드프레임의 타이바(18)(18′)및 댐바를 절단함으로써 각각의 리드들을 분리하는 트리밍공정과, 리드프레임의 아웃리드(16)를 소정의 모양으로 절곡형성하는 포밍공정과, 통상적인 플래팅공정을 포함하여 제작함을 특징으로 하는 멀티칩패키지 제작방법.In the manufacturing method of a multichip package, the first and second semiconductor chips 12a and 12'a, which are separated by a sawing process, are attached to both sides of the paddle 11 of the lead frame by using an adhesive 13, respectively. A die attach process for fixing and a plurality of bond pads 12a, 12'a and the inner lead 14 of the lead frame, which are provided in each of the dies 12 and 12 'that are die-attached, may be used. A wire bonding process for electrically connecting and connecting the metal wires 15 and 15 ', and a predetermined portion including each of the wire-bonded chips 12 and 12' and the outlead 16 of the lead frame. A molding process of sealing the epoxy molding compound 17, a trimming process of separating the leads by cutting the tie bars 18 (18 ') and the dam bar of the lead frame, and an out lead 16 of the lead frame. Forming process including bending and forming a conventional shape, characterized in that the manufacturing including the conventional plating process How to make a multichip package. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910023255A 1991-12-17 1991-12-17 Multi chip package fabrication method and structure thereof KR100239684B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910023255A KR100239684B1 (en) 1991-12-17 1991-12-17 Multi chip package fabrication method and structure thereof

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Application Number Priority Date Filing Date Title
KR1019910023255A KR100239684B1 (en) 1991-12-17 1991-12-17 Multi chip package fabrication method and structure thereof

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KR930014846A true KR930014846A (en) 1993-07-23
KR100239684B1 KR100239684B1 (en) 2000-01-15

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KR1019910023255A KR100239684B1 (en) 1991-12-17 1991-12-17 Multi chip package fabrication method and structure thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542673B1 (en) * 2000-08-14 2006-01-12 앰코 테크놀로지 코리아 주식회사 Semiconductor package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220837A (en) * 1988-02-29 1989-09-04 Nec Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542673B1 (en) * 2000-08-14 2006-01-12 앰코 테크놀로지 코리아 주식회사 Semiconductor package

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