KR100239685B1 - Semiconductor package structure and its manufacturing method - Google Patents
Semiconductor package structure and its manufacturing method Download PDFInfo
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- KR100239685B1 KR100239685B1 KR1019910023314A KR910023314A KR100239685B1 KR 100239685 B1 KR100239685 B1 KR 100239685B1 KR 1019910023314 A KR1019910023314 A KR 1019910023314A KR 910023314 A KR910023314 A KR 910023314A KR 100239685 B1 KR100239685 B1 KR 100239685B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
본 발명은 반도체 패키지 구조 및 그 제작방법에 관한 것으로, 중간부에 수개의 본드패드가 구비된 반도체 칩과, 그 반도체칩이 부착 고정되는 다이패들이 구비된 리드프레임과, 상기 반도체 칩을 다이어태치하기 위한 접착제와, 다이어태치된 칩을 인캡슐레이션하기 위한 겔타입의 절연물질과, 그 겔타입의 절연물질 내부에 입설되며 일단부는 상기 반도에 칩의 본드패드에 인접하게 배치되고, 그 타단부는 상기 겔타입의 절연물질 외부로 돌출되는 수개의 외부연결리드와, 상기 겔타입의 절연물질과는 별도로 외부를 밀폐시키는 에폭시 몰딩 컴파운드로 구성되어 있다. 이와 같이 된 본 발명은 제조공정기술상의 어려움을 완화시킬수 있고 구조 및 제작공정이 간단하여 제조원가를 절감시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure and a manufacturing method thereof, comprising: a semiconductor chip including several bond pads in a middle portion thereof, a lead frame including die pads to which the semiconductor chip is attached and fixed, and die attaching the semiconductor chip A gel-type insulating material for encapsulating the die-attached chip, a gel-type insulating material for encapsulating the die-attached chip, and one end of which is disposed adjacent to the bond pad of the chip on the peninsula and the other end thereof. Is composed of several external connection leads protruding to the outside of the gel-type insulating material, and epoxy molding compound for sealing the outside separately from the gel-type insulating material. The present invention as described above can mitigate the difficulties in the manufacturing process technology and the structure and manufacturing process is simple, there is an effect that can reduce the manufacturing cost.
Description
제1도는 종래의 일반적인 반도체 패키지의 구성을 보인 단면도.1 is a cross-sectional view showing the configuration of a conventional general semiconductor package.
제2도는 본 발명에 사용되는 리드프레임의 구성 및 대량생산을 위한 연속공정의 일예를 보인 평면도.Figure 2 is a plan view showing an example of the configuration of the lead frame used in the present invention and a continuous process for mass production.
제3도는 본 발명에 의한 반도체 패키지의 구성을 보인 단면도.3 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 칩 11a : 본드패드(Bond pad)11 semiconductor chip 11a bond pad
12 : 리드프레임(Lead frame) 12a : 다이패들(Die paddle)12: Lead frame 12a: Die paddle
13 : 접착제(Adhesive) 14 : 겔타입(Gel Type)의 절연물질13: adhesive 14: gel type insulating material
15 : 외부연결리드(Lead) 16 : 에폭시 몰딩 컴파운트(EMC)15: Lead for external connection 16: Epoxy molding compound (EMC)
17,17' : 사이드 레일(Side rail) 18,18' : 서포트 바(Support bar)17,17 ': Side rail 18,18': Support bar
본 발명은 반도체 패키지 구조 및 그 제작방법에 관한 것으로, 특히 패키지의 제작공정을 단순화하고 구조를 간단히 하여 실장을 용이하게 함과 아울러 패키지 제조원가 절감에 적합하도록한 반도체 패키지 구조 및 그 제작방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package structure and a method of manufacturing the same, and more particularly, to a semiconductor package structure and a method of manufacturing the same, which are suitable for simplifying the package manufacturing process and simplifying the package manufacturing cost and reducing package manufacturing cost. .
통상적으로 알려지고 있는 반도체 패키지는 반도체 칩의 패키지후, 이에 대한 신뢰성(Reliability)을 고려하고, 특히 외부와의 연결을 위해 패키지 외부로 외부연결리드들을 노출시키는 것이 일반적인 패키지 제조공정 및 구조로 알려지고 있다.Conventionally known semiconductor package is known as a general package manufacturing process and structure to consider the reliability of the semiconductor chip after the package, and to expose the external connection leads to the outside of the package, in particular for connection to the outside. have.
즉, 종래의 일반적인 반도체 패키지는 제1도에 도시한 바와 같이 복수개의 본드 패드(Bond pad)(1a)가 구비된 반도체 칩(1)과, 그 반도체 칩(1)이 부착 고정되는 패들(2a)이 구비됨과 아울러 상기 반도체 칩(1)에 와이어 본딩되는 복수개의 인너리드(inner lead)(2b) 및 아웃리드(Out lead)(2c)가 구비된 리드프레임(2)과, 그 리드프레임(2)의 패들(2a)에 상기 반도체 칩(1)을 부착 고정하기 위한 접착제(Adhesive)(3)와, 상기 패들(2a)에 부착 고정된 반도체 칩(1)의 본드패드(1a)와 상기 리드프레임(2)의 인너리드(2b)를 전기적으로 접속 연결시키는 복수개의 금속와이어(4)와, 와이어 본딩된 상기 칩(1)과 리드프레임(2)의 아웃리드(2c)를 포함하는 일정부위를 밀폐시키는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)(5)로 구성되어 있다.That is, a conventional general semiconductor package includes a semiconductor chip 1 having a plurality of bond pads 1a as shown in FIG. 1, and a paddle 2a to which the semiconductor chip 1 is attached and fixed. ) And a lead frame (2) having a plurality of inner leads (2b) and out leads (Out leads) 2c wire-bonded to the semiconductor chip (1), and the lead frame ( An adhesive 3 for attaching and fixing the semiconductor chip 1 to the paddle 2a of 2), the bond pad 1a of the semiconductor chip 1 attached and fixed to the paddle 2a, and the A schedule including a plurality of metal wires 4 for electrically connecting and connecting the inner leads 2b of the lead frame 2, and the wire-bonded chip 1 and the out leads 2c of the lead frame 2. It consists of an epoxy molding compound (5) which seals a site | part.
이와 같이 구성된 종래의 반도체 패키지의 제작과정을 살펴보면, 먼저 소잉(Sawing) 공정에 의해 개개로 분리된 칩(1)을 리드프레임(2)의 패들(2a)위에 접착제(3)를 이용하여 부착 고정하는 다이어 태치(Die attach)공정을 수행하는 바, 이는 패들(2a)의 윗면에 디스펜서(Dispenser)(도시되지 않음)를 이용하여 접착제(3)를 도팅(Dotting)한 후 이에 칩(1)을 부착 고정한다.Referring to the manufacturing process of the conventional semiconductor package configured as described above, first, the chip 1 separated by the sawing process is fixed to the paddle 2a of the lead frame 2 using the adhesive 3. The die attach process may be performed. The doping of the adhesive 3 using a dispenser (not shown) on the upper surface of the paddle 2a may be performed after the chip 1 is attached thereto. Secure the attachment.
그런다음 다이어태치된 칩(1)의 본드패드(1a)와 리드프레임(2)의 인너리드(2b)를 금속와이어(4)를 이용하여 전기적으로 접속 연결시키는 와이어 본딩(Wire Bondiig) 공정을 수행하고, 와이어 본딩된 상기의 칩(1)과 상기 리드프레임(2)의 아웃리드(2c)를 포함하는 일정부위를 에폭시 몰딩 컴파운드(5)로 밀폐시키는 몰딩공정을 수행하여 경화시킨다. 이후, 상기 리드프레임(2)의 패들(2a) 및 각 리드(2b)(2c)들을 지지하고 있는 타이바(Tie bar) 및 댐바(Dam bar)(도시되지 않음)를 절단하는 트리밍(Trimming)공정과, 패키지 외부로 돌출된 리드프레임(2)의 아웃리드(2c)를 소정의 모양으로 절곡 형성하는 포밍(forming)공정과, 통상적인 플래팅(plating) 공정을 행함으로써 제1도에 도시한 바와 같은 반도체 패키지가 완성되는 것이다.Then, a wire bonding process is performed in which the bond pad 1a of the die-attached chip 1 and the inner lead 2b of the lead frame 2 are electrically connected to each other using the metal wires 4. In addition, a molding process of sealing a portion including the wire-bonded chip 1 and the outlead 2c of the lead frame 2 with the epoxy molding compound 5 is cured. Afterwards, trimming for cutting tie bars and dam bars (not shown) supporting the paddles 2a and the respective leads 2b and 2c of the leadframe 2. Shown in FIG. 1 by performing a process, a forming process of bending the outlead 2c of the lead frame 2 protruding out of the package into a predetermined shape, and a conventional plating process. The semiconductor package as described above is completed.
그러나, 상기한 바와 같은 종래의 반도체 패키지는 패키지 제조공정이 복잡할 뿐만 아니라, 그 구조가 복잡하여 패키지 제조기술상의 어려움이 있었고, 또한 플라스틱 패키지(plastic package)의 경우 기본적 패키지 타입으로 제조하여도 외부와의 연결을 위한 리드등의 문제로 금형제작등에 소요되는 비용등, 그 패키지 제조원가가 높아지는 결함이 있는 것이었다.However, the conventional semiconductor package as described above not only has a complicated package manufacturing process, but also has a complicated structure of the package manufacturing technology, and in the case of a plastic package, even when manufactured as a basic package type, Due to the problem of lead for connection, the cost of manufacturing the mold is high, and the manufacturing cost of the package increases.
이를 감안하여 창안한 본 발명의 목적은 패키지 제조기술상의 어려움을 완화하고, 그 구조 및 제조공정을 단순화하여 패키지 제조원가를 절감함과 아울러 실장이 용이하도록한 반도체 패키지 구조 및 그 제작방법을 제공함에 있다.In view of the above, an object of the present invention is to provide a semiconductor package structure and a method of fabricating the same, which alleviate difficulties in package manufacturing technology, simplify the structure and manufacturing process, reduce package manufacturing cost, and facilitate mounting. .
상기와 같은 본 발명의 목적은 중간부에 수개의 본드패드가 구비된 반도체 칩을 인, 아웃리드가 제거된 리드프레임의 패들에 부착 고정하고, 다이어태치된 칩을 겔타입(Gel Type)의 절연물질로 인캡슐레이션(Encapsulation)함과 아울러 상기 칩의 본드패드에 인접하게 수개의 리드들을 수직으로 세워 내장한 후, 상기 인캡슐레이션된 부분의 일부를 노출시켜 몰딩하고, 상기 리드프레임의 패들을 지지하는 서포트 바를 절단함으로써 완성된 패키지를 개개로 분리함을 특징으로 하는 반도체 패키지 구조 및 그 제작방법을 제공함으로써 달성되는 것이다.The object of the present invention as described above is to attach and fix the semiconductor chip provided with a plurality of bond pads in the middle portion to the paddle of the lead frame, the in-lead removed, and the die-attached chip insulated from gel type (Gel Type) In addition to encapsulation with the material, several leads are built vertically adjacent to the bond pads of the chip, and then exposed by molding a portion of the encapsulated portion, and the paddles of the leadframe It is achieved by providing a semiconductor package structure and a method of manufacturing the same, characterized in that the completed package is separated individually by cutting the supporting support bar.
이하에서는 이러한 본 발명을 첨부한 도면에 의하여 보다 상세히 설명한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제2도 및 제3도에 도시한 바와 같이 본 발명에 의한 반도체 패키지의 구조는 중간부에 수개의 본드패드(11a)가 구비된 반도체 칩(11)과, 그 반도체 칩(11)이 부착 고정되는 다이패들(12 a)이 구비된 리드프레임(12)과, 상기 반도체 칩(11)을 다이어태치하기 위한 접착제(13)와, 다이어태치된 반도체 칩(11)을 인캡슐레이션하기 위한 겔타입의 절연물질(14)과, 그 겔타입의 절연물질(14) 내부에 입설되며 일단부(15a)는 상기 반도체 칩(11)의 본드패드(11a)와 인접하게 배치되고 그 타단부(15b)는 상기 겔타입의 절연물질(14) 외부로 돌출되는 수개의 외부연결리드(15)와, 상기 겔타입의 절연물질(14)과는 별도로 외부를 밀폐시키는 에폭시 몰딩 컴파운드(16)로 구성되어 있다.As shown in FIG. 2 and FIG. 3, the structure of the semiconductor package according to the present invention is a semiconductor chip 11 having a plurality of bond pads 11a in an intermediate portion thereof, and the semiconductor chip 11 attached and fixed thereto. A lead frame 12 having a die paddle 12 a, an adhesive 13 for die attaching the semiconductor chip 11, and a gel for encapsulating the die attached semiconductor chip 11. A type of insulating material 14 and a gel type insulating material 14, and one end 15a is disposed adjacent to the bond pad 11a of the semiconductor chip 11 and the other end 15b thereof. ) Is composed of several external connection leads 15 protruding to the outside of the gel-type insulating material 14, and the epoxy molding compound 16 to seal the outside separately from the gel-type insulating material (14) have.
이와 같이 구성되는 본 발명에 사용되는 리드프레임(12)은 제2도에 도시한 바와 같이 사이드레일(17)(17')의 내측에 반도체 칩(11)이 부착 고정되는 패들(12a)이 서포트바(18)(18')에 의해 지지된 구성으로 되어 있다.The lead frame 12 used in the present invention configured as described above supports the paddle 12a on which the semiconductor chip 11 is attached and fixed inside the side rails 17 and 17 ', as shown in FIG. The structure is supported by the bars 18 and 18 '.
또한, 에폭시 몰딩 컴파운드(16)로 몰딩함에 있어서는 상기 칩(11)을 인캡슐레이션하는 겔타입의 절연물질(14)의 일부가 외부로 노출되도록 몰딩함으로써 패키지 실장시 상기 겔타입의 절연물질(14)에 입설된 수개의 외부연결리드(15)의 일단부(15a)가 칩(11)의 본드패드(11a)에 접촉되어 전기적인 도통이 이루어지도록 구성되어 있다.In addition, in molding with the epoxy molding compound 16, a part of the gel type insulating material 14 encapsulating the chip 11 is molded to be exposed to the outside, thereby molding the gel type insulating material 14 when the package is mounted. One end portion 15a of the several external connection leads 15 placed in the lateral contact with the bond pad 11a of the chip 11 is configured for electrical conduction.
또한, 상기 반도체 칩(11)의 본드패드(11a)는 칩(11)의 중앙에 배열함이 바람직하며, 본드패드(11a)의 상측에 도전성의 재질로 범프(Bump)를 형성할 수도 있는 바, 이는 외부연결리드(15)와의 접촉을 용이하게 하기 위함이다.In addition, the bond pads 11a of the semiconductor chip 11 may be arranged at the center of the chip 11, and bumps may be formed on the bond pads 11a with a conductive material. This is to facilitate contact with the external connection lead 15.
또한, 상기 칩(11)을 인캡슐레이션하는 겔타입의 절연물질(14)은 외부연결리드(15)들이 통과 가능한 것을 선택하되, 외부의 습기 및 이물질들의 침투를 방지할 수 있는 물질을 선택함이 바람직하다.In addition, the gel type insulating material 14 encapsulating the chip 11 selects the external connection leads 15 to pass through, but selects a material that can prevent external moisture and foreign matter from penetrating. This is preferred.
이와 같이, 구성되는 본 발명에 의한 반도체 패키지는 단순한 기능을 가진 칩의 패키징(packaging)에 적당한 바, 그의 제작과정을 살펴보면 다음과 같다.As described above, the semiconductor package according to the present invention is suitable for packaging a chip having a simple function, and the manufacturing process thereof is as follows.
즉, 본 발명에 의한 반도체 패키지는 소잉공정에 의해 개개로 분리된 칩(11)을 리드프레임(12)의 패들(12a) 위에 접착제(13)를 이용하여 부착 고정하는 제1단계공정과, 다이어태치된 칩(11)을 겔타입의 절연물질(14)로 인캡슐레이션하는 제2단계공정과, 인캡슐레이션된 칩(11)의 각 본드패드(11a)에 인접하게 수개의 외부연결리드(15)들을 수직으로 세워서 설치하는 제3단계공정과, 이와 같이 된 반도체 칩(11)을 에폭시 몰딩 컴파운드(16)로 몰딩하는 제4단계 공정과, 상기 리드프레임(12)의 서포트 바(18)(18')를 절단함으로써 완성된 패키지를 개개로 분리하는 제5단계 공정을 포함하여 제작하는 바, 상기 외부연결리드(15)는 그 일단부(15a)가 반도체 칩(11)의 본드패드(11a)에 인접하게 배치되고, 그 타단부(15b)는 겔타입의 절연물질(14) 외부로 돌출되어 외부에서 상기 외부연결리드(15)의 타단부(15b)를 제3도에 도시한 화살표 방향으로 누르게 되면, 외부연결리드(15)의 일단부(15a)가 반도체 칩(11)의 본드패드(11a)에 각각 접촉되면서 소정의 동작을 하게 되어 있는 것이다.That is, in the semiconductor package according to the present invention, the first step step of attaching and fixing the chips 11 separately separated by the sawing process using the adhesive 13 on the paddle 12a of the lead frame 12, and the diamond A second step of encapsulating the attached chip 11 with a gel type insulating material 14 and several external connection leads adjacent to each bond pad 11a of the encapsulated chip 11 ( A third step of vertically installing the 15), a fourth step of molding the semiconductor chip 11 into the epoxy molding compound 16, and the support bar 18 of the lead frame 12. And a fifth step of separately separating the completed package by cutting the 18 ', and the external connection lead 15 has one end 15a of a bond pad (1) of the semiconductor chip 11. 11a), and the other end 15b protrudes out of the gel-type insulating material 14 so that the outside When the other end 15b of the connection lead 15 is pressed in the direction of the arrow shown in FIG. 3, one end 15a of the external connection lead 15 is attached to the bond pads 11a of the semiconductor chip 11, respectively. The contact is to perform a predetermined operation.
그리고, 상기 제작공정중 몰딩공정을 행함에 있어서는 겔타입의 절연물질(14) 일부분이 노출되도록 몰딩한다.In the molding process, a part of the gel type insulating material 14 is exposed.
상기와 같은 본 발명에 의한 반도체 패키지는 간단한 기능과 단순한 동작을 하는 반도체 칩의 패키징에 적합하며, 향후 도래하게 될지도 모를 1회용 칩 패키징에 유리하게 적용할 수 있는 바, 도시하고 상술한 바와 같이 본 발명에 의한 반도체 패키지는 리드프레임의 구조가 간단하여 리드프레임의 제작이 용이하고, 패키지의 제조공정이 간단하여 제조원가를 절감할 수 있을 뿐만아니라 패키지의 실장이 용이하고 정밀도에 대한 기술적 어려움이 없으므로 제조공정이 단순해지는 효과가 있다.As described above, the semiconductor package according to the present invention is suitable for packaging a semiconductor chip having a simple function and a simple operation, and may be advantageously applied to a disposable chip packaging which may be coming in the future. The semiconductor package according to the invention has a simple lead frame structure, which facilitates the manufacture of the lead frame, and the manufacturing process of the package is simple, thereby reducing the manufacturing cost and making the package easy to mount and having no technical difficulties for precision. There is an effect of simplifying the process.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023314A KR100239685B1 (en) | 1991-12-18 | 1991-12-18 | Semiconductor package structure and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023314A KR100239685B1 (en) | 1991-12-18 | 1991-12-18 | Semiconductor package structure and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930014922A KR930014922A (en) | 1993-07-23 |
| KR100239685B1 true KR100239685B1 (en) | 2000-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910023314A KR100239685B1 (en) | 1991-12-18 | 1991-12-18 | Semiconductor package structure and its manufacturing method |
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| Country | Link |
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| KR (1) | KR100239685B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200454915Y1 (en) * | 2008-04-18 | 2011-08-05 | 오리엔트 세미컨덕터 일렉트로닉스 리미티드 | Electronic storage package |
-
1991
- 1991-12-18 KR KR1019910023314A patent/KR100239685B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200454915Y1 (en) * | 2008-04-18 | 2011-08-05 | 오리엔트 세미컨덕터 일렉트로닉스 리미티드 | Electronic storage package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930014922A (en) | 1993-07-23 |
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