US20030102537A1 - Saw singulated leadless plastic chip carrier - Google Patents

Saw singulated leadless plastic chip carrier Download PDF

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Publication number
US20030102537A1
US20030102537A1 US10/269,327 US26932702A US2003102537A1 US 20030102537 A1 US20030102537 A1 US 20030102537A1 US 26932702 A US26932702 A US 26932702A US 2003102537 A1 US2003102537 A1 US 2003102537A1
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United States
Prior art keywords
die
leads
attach pad
pad
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/269,327
Inventor
Neil McLellan
Nelson Fan
Original Assignee
Mclellan Neil
Fan Nelson Chun Ho
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Filing date
Publication date
Priority to US09/095,803 priority Critical patent/US6229200B1/en
Priority to US09/363,249 priority patent/US6242281B1/en
Priority to US09/793,367 priority patent/US20010030355A1/en
Application filed by Mclellan Neil, Fan Nelson Chun Ho filed Critical Mclellan Neil
Priority to US10/269,327 priority patent/US20030102537A1/en
Publication of US20030102537A1 publication Critical patent/US20030102537A1/en
Application status is Abandoned legal-status Critical

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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to integrated circuit package technology. In particular, the present invention relates to resin-encapsulated integrated circuit packages. [0002]
  • 2. Discussion of the Related Art [0003]
  • Conventional lead frames are typically formed on a metal strip which provides up to ten (10) units. A conventional lead frame includes a “die pad” for accommodating a semiconductor die, and inner leads and outer leads. A lead frame can be incorporated in a variety of integrated circuit packages, such as a quad flat pack (QFP) package and its many variations. In a QFP package, each bond pad provided on the semiconductor die is wire-bonded to an inner lead which, in turn, is electrically coupled to an outer lead. The inner leads are typically provided moldlocking features to allow proper positioning of the lead frame during the molding step which provides a plastic or resin encapsulation of the package. After encapsulation, the outer leads are trimmed and bent using custom trim and form tools to complete the electrical terminals or “leads” used for mounting the package on to a printed circuit board. Precise forming of the leads is necessary to ensure satisfactory board yield. Malformed leads can result in open or shorted solder joints because of aplanarity or skewed leads. In addition, even without such malformed leads, board yield in QFP packages is also diminished by open solder joints resulting from solder wicking up the leads. [0004]
  • The size of a prior art QFP package is limited by the dimensions of the semiconductor die plus about 3 mm on each side. For example, a 7 mm×7 mm QFP package can accommodate up to a 4 mm×4 mm semiconductor die. Clearance requirements on a printed circuit board can add another 2 mm on each side to the final foot print. Thus, a 7 mm×7 mm QFP typically has a footprint of 9 mm×9 mm, thereby providing an effective board density of approximately 20%. [0005]
  • Conventional QFP type packages are encapsulated in resin both at the top and the bottom of the semiconductor die. Consequently, conventional QFP packages cannot be made thinner than 1.4 mm. In addition, external lead “stand-off” requirements add to the height of the final printed circuit board assembly. [0006]
  • One important quality measure for an integrated circuit package is reliability. In a QFP package, a significant failure mode is the delamination of the mold compound from the back of a die pad. Delamination introduces moisture into the package and causes moisture-related failures. [0007]
  • One performance measure in a conventional QFP or any plastic package is thermal performance. Such a package is limited in its thermal performance because of a lack of a thermally conductive path to dissipate heat from the semiconductor die to the exterior. In many applications, a heat sink is included in the package. However, including a heat sink increases the material cost of such a package. Further, even if a heat sink is included, there are still typically multiple layers of epoxy through which heat must flow from the semiconductor die to the exterior. [0008]
  • A conventional QFP package is typically manufactured in an assembly process which requires a custom mold, a custom trim tool and a custom form tool. Thus, the tooling cost for manufacturing a new QFP package is high. For a given integrated circuit, rather than providing a package that is optimized specifically for its size and its number of input/output (I/O) terminals, a designer typically selects a package by matching the size and I/O terminals requirements of his integrated circuit as closely as possible to one of a few available QFP packages for which the tooling investment is already made. Clearly, the resulting QFP package is optimized for neither density nor material cost. [0009]
  • What is desired is a low cost, high density, high reliability integrated circuit package with flexible configuration. [0010]
  • SUMMARY OF THE INVENTION
  • The present invention provides a plastic chip carrier and a method for making the same. A plastic chip carrier of the present invention includes: (a) a semiconductor die with bonding pads formed on its surface; (b) a die-attach pad on which the semiconductor die is attached; (c) leads disposed in close proximity of the die-attach pad; (d) wires bonded to the bonding pads and their corresponding leads to provide electrical connections; and (e) an encapsulation sealing the semiconductor die, the die attach-pad, the wires, and the leads from the environment in such a manner as to expose only the bottom surfaces of the die-attach pad and the leads. [0011]
  • The plastic chip carrier is formed using a process which includes the operations: (a) forming a matrix of lead frames out of a metal strip, with each lead frame having a die-attach pad and leads disposed in close proximity of the die-attach pad; (b) attaching a semiconductor die to each of the die-attach pad of the lead frame; (c) wire-bond the semiconductor die to the leads, so as to allow the leads to serve as electrical terminals to the semiconductor die; and (d) encapsulating the die-attach pad, the semiconductor die, the bond wires and the leads in a resin material to form a package, in such a manner that only the bottom surface of the die-attach pad and the bottom surfaces of the leads are exposed. [0012]
  • In one embodiment, the plastic chip carrier has an interlocking lip around the periphery of the die-attach pad, so as to allow the encapsulation material to securely engage the die-attach pad. In another embodiment, tie bars are provided attached to the die-attach pad. Each tie bar extends from the die-attach pad outwards to form a peripheral heat pad at the other end. Heat from the operating semiconductor die is conducted by the tie bar to the heat pad for dissipation out of the encapsulation. One of the heat pads has an appearance distinctive from the other heat pads of the chip carrier, thereby providing a convenient marker on the chip carrier which can be used to identify an orientation of the chip carrier or the location of a specified pin, such as pin [0013] 1.
  • In one embodiment, the die-attach pad of the plastic chip carrier is pre-plated with palladium to avoid silver migration. In addition, the top surface of the encapsulation is provided a distinctive pattern, which can be conferred to the encapsulation from the molding cavity during the molding process. This pattern, which can be a dimple array, for example, can be used to orient the package after singulation. Alternatively, solder balls can be attached to the exposed portions of the leads to provide some clearance between the printed circuit board on which the package is mounted and the plastic chip carrier. In one embodiment, a soft solder attaches the semiconductor die to the die-attach pad to provide improved thermal performance. [0014]
  • According to another aspect of the present invention, a plastic carrier includes a double-row lead frame having leads arranged as an annular row of inner leads and an annular row of outer leads. The lead frame includes (a) a die-attach pad; (b) an annular row of inner leads; (c) an annular row of outer leads connected to the annular row of inner leads by a connecting portion. The connecting portion has a thickness which is half the thickness of a lead in the annular rows of inner and outer leads. In one implementation, the leads in the annular row of inner leads and the annular row of outer leads are arranged in an alternating fashion, to allow maximum density for wire bonds from the bonding pads of the semiconductor die at the die-attach pad to the inner and outer leads. [0015]
  • The double-row frame can be formed in a matrix of substantially identical lead frames. Further, the matrix of lead frames can be formed as one of multiple matrices of lead frames formed in a metal strip. [0016]
  • The present invention is better understood upon consideration of detailed description below and the accompanying drawings.[0017]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a strip [0018] 100, including six substantially identical sections 101-1 to 101-6, which can be used to fabricate packages of the present invention.
  • FIG. 2[0019] a shows a 3×3 array of lead frames which can be provided in any of the sections of strip 100.
  • FIG. 2[0020] b shows lead frame 201 including die-attach pad 202 suspended by tie bars 204, which are integrally formed with leads 203.
  • FIG. 3 shows FIG. 2[0021] a's 3×3 array 200 of lead frames, after attachment of semiconductor dies to its die attach pads and wire-bonding.
  • FIG. 4[0022] a shows a molded package 400 in a cross section along one dimension of the die-attach pad.
  • FIG. 4[0023] b shows a side view of molded package 400.
  • FIG. 5[0024] a shows a 2×2 array 500 of lead frames, including lead frames 501-1 to 501-4, which can be implemented in a section of strip 100, in accordance with another embodiment of the present invention.
  • FIG. 5[0025] b shows in further detail lead frame 501, which is one of lead frames 501-1 to 501-4 of FIG. 5a.
  • FIG. 5[0026] c shows a cross section, along line A-A, of die-attach pad 502 of FIG. 5b.
  • FIG. 5[0027] d shows a cross section of a lead in lead frame 501 of FIG. 5b.
  • FIG. 6[0028] a shows a lead frame 600 for a “doublerow” SSLPCC, in accordance with another embodiment of the present invention.
  • FIG. 6[0029] b shows a cross-section of lead frame 600 of FIG. 6a, along line A-A of FIG. 6a.
  • FIG. 6[0030] c shows a cross-section of lead frame 600 of FIG. 6a, along line B-B of FIG. 6a.
  • FIG. 7 shows lines [0031] 701, 702 and 703 along which lead frame 600 is cut to sever half-etched portion 606 (thereby severing inner leads 603 from outer leads 602) and for severing the leads in inner leads 603 and outer leads 602 from each other.
  • FIG. 8[0032] a shows a cross-section of a double-row SSLPCC, including lead frame 600 of FIG. 6a, along line A-A of FIG. 6a.
  • FIG. 8[0033] b shows a cross-section of a double-row SSLPCC, including lead frame 600 of FIG. 6a, along line B-B of FIG. 6a
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention provides a saw-singulated leadless plastic chip carrier (SSLPCC) and a method for assembling such a chip carrier. The SSLPCC of the present invention is a low-cost, high density, high reliability integrated circuit package with superb thermal and electrical performances. To facilitate cross-reference between figures, in the figures described below, like elements are provided like reference numerals. [0034]
  • FIG. 1 shows a strip [0035] 100 including six substantially identical sections 101-1 to 101-6, which can be used to fabricate the packages of the present invention. Using such a strip allows the assembly process to be carried out in conventional automated assembly equipment and molds. Within each of sections 101-1 to 101-6 is an area 103 in which lead frames of the present invention can be formed using a conventional process, such as a chemical etching process or a stamping process. A 3×3 array of lead frames, labeled 200 in FIG. 2a, can be formed in area 103, as shown in FIG. 2a. On the periphery of area 103 are placed alignment targets and tooling throughholes and other conventional features (labeled, collectively, by reference numerals 102 a) used in automated assembly equipment.
  • FIG. 2[0036] a shows 3×3 array 200 of lead frames, including lead frames 201-1 to 201-9, which can be formed in a section of strip 100. Thus, in this configuration, 54 lead frames can be formed strip 100. Each lead frame, e.g., lead frame 201-1, includes a die-attach pad (e.g., die-attach pad 202 a of lead frame 201-1) and a group of leads (e.g., leads 203 a of lead frame 201-1) provided in close proximity to the die-attach pad. An exemplary lead frame 201 is shown in further detail in FIG. 2b. As shown in FIG. 2b, lead frame 201 includes die-attach pad 202 suspended by tie bars 204, which are integrally formed with leads 203. In lead frame 201, tie bars 204 each extend towards the periphery of lead frame 201 to form a heat pad (e.g., any one of heat pads 208 and 209) at one corner of the molded package to be formed. Such a heat pad provides a highly thermally conductive path for transferring heat from die-attach pad 202 out of the molded package to be formed. One such heat pad, labeled 208 in FIG. 2b is made slightly different from the other heat pads (each labeled 209) formed in the other tie bars. In this embodiment, die-attach pad 202 is 5 mm on a side, and each of leads 203 is 0.4 mm wide and 0.13 mm thick. Spacing between adjacent leads is also 0.4 mm. Lead frame 201 can be pre-plated with palladium to avoid silver migration.
  • During the assembly process, a singulated semiconductor die is conventionally mounted or attached by epoxy or any suitable adhesive to each of die-attach pads (e.g., die attach pads [0037] 202 a-202 i). The semiconductor die can also be attached using a soft solder to provide thermal conductivity between the semiconductor die and the die-attach pad, thereby improving the thermal performance of the resulting package. After the adhesive is cured, if required, each semiconductor die is wire-bonded to the leads (e.g., leads 203 a) located at the periphery of the die-attach pad, using conventional automated bonding equipment. Gold wires can be used in this wire-bonding operation. FIG. 3 shows 3×3 array 200 of FIG. 2b, after die-attachment (note, for example, semiconductor die 206 a) and wire-bonding. Wire-bonds 205 electrically couple each bonding pad on semiconductor die 206 a to a corresponding one of leads 203 a.
  • Following wire-bonding, strip [0038] 100 is conventionally molded using a mold in which the bottom plate is a flat plate, so that the molding compound exposes the bottom surfaces of the die-attach pads, the heat pads of the tie bars, and the leads. The under side of strip 100 is then deflashed to remove any molding compound residues from the exposed surfaces of the lead frames, so as to allow the leads and the die-attach pad to serve as solder pads for attachment to the printed circuit board at a subsequent time. As mentioned above, one of the heat pads formed on the tie bars is provided a difference appearance from the other heat pads. This different appearance can serve as a built-in marker to indicate a designated pin (e.g., pin 1) of the package, or to help identify an orientation of the package.
  • Optionally, strip [0039] 100 can then be ink-marked and solder-plated to facilitate a subsequent board-attach step. Solder plating is not necessary if strip 100 was pre-plated with palladium. Solder balls can also be attached to the exposed portions of the leads to provide a clearance when mounted on a printed circuit board. Such clearance facilitates cleaning (e.g., cleaning of solder flux).
  • Finally, strip [0040] 100 is mounted to a wafer saw ring by an adhesive tape and saw-singulated using a conventional wafer saw. Singulation can be guided by a pattern formed on the top side of the package during molding. Such a pattern, e.g., a dimple array, which can be easily transferred from the molding cavity of a mold, is also useful for automated orienting or positioning of the resulting singulated package. The singulated component is then ready for mounting onto a printed circuit board. Since no trimming or forming of leads are necessary, in addition to eliminating the costs associated with such steps, the packages manufactured under the present method described above do not suffer yield loss from defective trimming and forming of the external leads.
  • FIG. 4[0041] a shows a molded package 400 in a cross section along one dimension of the die-attach pad. As shown in FIG. 4, semiconductor die 206 is attached to die-attach pad 202 as described above. Conductive wires 205-1 and 205-2 are bonded to bonding pads on semiconductor die 206 and their respective leads 203-1 and 203-2. Molded package 400 is encapsulated in encapsulation material 401. In this embodiment, molded package 400 measures only 1.2 mm thick. A side view of molded package 400 is provided in FIG. 4b. FIG. 4b shows heat pads 208 and 209 at the corners of molded package 400. Since die-attach pad 202, leads 203 and heat pads 208 and 209 are all exposed, the thermal performance of molded package 400 is expected to be much higher than conventional QFP packages. Since die-attach pad 202 is exposed, the delamination problem of a conventional QFP package is avoided. Further, high reliability can be further enhanced in molded package 400 if the coefficient of expansion of molding material 401 is matched to the coefficient of expansion of the printed circuit board to which molded package 400 is to be mounted.
  • Unlike QFP packages of the prior art, because no additional clearance between packages is needed to accommodate the outer leads, a much smaller footprint is achievable in molded package [0042] 400. For example, in this embodiment, molded package 400 can accommodate up to a 5 mm×5 mm semiconductor die on a 7 mm×7 mm footprint, thus providing a effective bond density of 25/49 or almost 50%. Further, since only the top sides of the die-attach pad and the leads are molded, and since the exposed portions of the leads serve as solder pads, thus obviating the need for additional lead stand-off, a package of thickness 1.0 mm or less can easily be achieved. A thin package not only reduces material cost but provides additional thermal performance also. The relatively short leads of molded package 400, as compared to the inner leads-outer leads arrangements of conventional QFP packages, are expected to have lower parasitics than leads of a conventional QFP package. Thus, a package of the present invention provides electrical performance superior to a conventional QFP package. Also, as the manufacturing process described above requires little custom tooling, custom packages optimizing to device size and number of I/O terminals can be accommodated with minimal additional cost. By avoiding the cost of custom tooling and the cost of trimming and forming tools, and since molded package 400 requires less molding compound and lead frame material, molded package 400 is expect to cost only 10% to 20% of a comparable conventional QFP package.
  • FIG. 5[0043] a shows a 2×2 array 500 of lead frames, including lead frames 501-1 to 501-4, which can also be implemented in a section of strip 100, in accordance with another embodiment of the present invention. FIG. 5b shows in further detail lead frame 501, which is one of lead frames 501-1 to 501-4, showing die-attach pad 502, tie bars 503 and leads 504. In this embodiment, an interlocking lip 507 is provided in under side of die-attach pad 502. Interlocking lip 507 is shown in FIG. 5c in the cross section A-A of die-attach pad 502. Interlocking lip 507 allows the molding compound to flow underneath a portion of the die attach pad 502 to securely engage die-attach pad 502 to the encapsulation, thereby preventing moisture introduction into the package. FIG. 5d shows a cross section of a lead 504 in lead frame 501 of FIG. 5b. As shown in FIG. 5d, an interlocking lip 509, similar to interlocking lip 507 of die-attach pad 502, is provided in lead 504. As in interlocking lip 507, interlocking lip 509 allows the molding compound to hold lead 504 in place and to prevent introduction of moisture into the molded package.
  • FIG. 6[0044] a shows another embodiment of the present invention in a lead frame 600 for a “double row” SSLPCC. As shown in FIG. 6a, lead frame 600 includes a downset die-attach pad 601, which is suspended by tie-bars 607 a-607 d at the four corners of die-attach pad 601. At the other ends of tie bars 607 a-607 d are rectangular pads 604 a-604 c and triangular pad 605. Rectangular pads 604 a-604 c provide additional surfaces for heat dissipation. Triangular pad 605 is designed to be used for package orientation, such as indicating the position of pin 1.
  • Lead frame [0045] 600 includes an annular row of outer leads 602 and an annular row of inner leads 603, initially attached by a half-etched portion 606—i.e., the inner leads and the outer leads are connected by portion 606 which has a thickness one-half that of the leads. Half-etched portion 606 can be formed by etching the lead frame from the top using a conventional chemical etching process. In this embodiment, inner leads 603 and outer leads 602 each have a pitch of 0.5 mm, so that, with each lead being 0.25 mm wide, the spacing between adjacent leads is 0.25 mm. In this embodiment, each lead is 0.618 mm long. Annular inner leads 603 and annular outer leads 603 are positioned in a staggered or alternating manner to allow maximum room for wire-bonding from the bonding pads on the surface of a semiconductor die to be placed in die-attach pad 601 to each of the leads. Thus, very high pin density can be achieved.
  • FIGS. 6[0046] b and 6 c shows respectively cross-sections of lead frame 600 along lines A-A and B-B. The cross-section shown in FIG. 6b cuts through outer leads 602, showing half-etched portion 606, and die-attach pad 601. Similarly, the cross section shown in FIG. 6c cuts through inner leads 603, showing half-etched portion 606.
  • The assembly process for a double-row SSLPCC can follow the assembly process described above. However, in addition to the singulation step described above, an additional cut to sever half-etched portion [0047] 606 from the lead frame is provided. FIG. 7 shows lines 701, 702 and 703 along which lead frame 600 is cut to sever half-etched portion 606 (thereby severing inner leads 603 from outer leads 602) and for severing the leads in inner leads 603 and outer leads 602 from each other. Line 703 along the outer periphery is the singulation path for singulating the double-row SSLPCC from the adjacent packages. Line 701 and 702 severs half-etched portion 606. Of course, the cuts along lines 701 and 702 need only be deep enough to cut through half-etched portion 606. Half-etched portion provides clearance to prevent inadvertent damage to wire bonds between the bonding pads of the semiconductor die to outer leads 602.
  • FIGS. 8[0048] a and 8 b show cross sections of a doublerow SSPLCC package (after singulation) along lines A-A (through outer leads 602) and B-B (through inner leads 603). In this embodiment, the loop heights of wire bonds 801 and 802 between the semiconductor die 803 to outer leads 602 (FIG. 8b) and to inner leads 603 (FIG. 8a) are 15 mils and 10 mils, respectively. (A trapezoidal loop profile can be selected for the wire bonds). For a thickness of 6 mils for each lead in outer leads 602 and inner leads 603, a 1 mil die-attach epoxy bondline and a 10 mil thick semiconductor die, a 1.2 mm thick package would provide a 15 mil clearance between the top of each bond wire loop to the top of the package. Half-cut to sever connecting portion 606 can be made to a depth of 5 mils.
  • The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is particularly pointed out and distinctly claimed in the following claims. [0049]

Claims (22)

We claim:
1. A plastic chip carrier, comprising:
a semiconductor die having bonding pads formed thereon;
a die-attach pad having a bottom surface and a top surface on which said semiconductor die is attached;
a plurality of leads, each having a bottom surface and a top surface, said leads disposed in close proximity to said die-attach pad;
a plurality of wires each bonded to a selected one of said bonding pads and a corresponding one of said leads; and
an encapsulation encapsulating said semiconductor die, said top surface of said die attach-pad, said wires, and said top surfaces of said leads, and exposing said bottom surface of said die-attach pad and said bottom surfaces of said leads.
2. A plastic chip carrier as in claim 1, wherein said die-attach pad is provided an interlocking lip at a portion of said die-attach pad, said interlocking lip engaging said die-attach pad to said encapsulation.
3. A plastic chip carrier as in claim 1, further comprising a plurality of tie bars, each tie bar being attached to said die-attach pad and extending from said die-attach pad to form a peripheral heat pad for dissipating heat to the outside of said encapsulation.
4. A plastic chip carrier as in claim 3, wherein one of said heat pads has an appearance distinctive from other heat pads of said chip carrier.
5. A plastic carrier as in claim 1, wherein said die-attach pad and said leads are formed out of an array of lead frames integrally formed on a portion of a metal strip.
6. A plastic carrier as in claim 1, wherein said die-attach pad is plated with palladium.
7. A plastic carrier as in claim 1, wherein a distinctive pattern is formed on said encapsulation.
8. A plastic carrier as in claim 1, further comprising solder balls each attached to a bottom side of a corresponding one of said leads.
9. A plastic carrier as in claim 1, wherein a soft solder attaches said semiconductor die to said die-attach pad.
10. A plastic carrier as in claim 1, wherein said plurality of leads are arranged as an annular row of inner leads and an annular row of outer leads.
11. A process for forming a plastic carrier, comprising:
forming a matrix of lead frames out of a metal strip, each lead frame including a die-attach pad and a plurality of leads disposed in close proximity to said die-attach pad, said die-attach pad and said leads each having a bottom surface and a top surface;
attaching to the top surface of each die-attach pad a semiconductor die, said semiconductor die having a plurality of bonding pads formed thereon;
providing bond wires to electrically connect each of said bonding pads to the top surface of a corresponding lead; and
encapsulating said die-attach pad, said semiconductor die, said bond wires and said leads in a resin material such that said bottom surface of said die-attach pad and said bottom surfaces of said leads are exposed.
12. A process as in claim 11, wherein said die-attach pad is provided an interlocking lip at the periphery such that said resin material engages interlocking lip of said die-attach pad.
13. A process as in claim 11, wherein each of said lead frames includes tie bars, said matrix of lead frames being formed with each tie bar being attached to said die-attach pad and extending from said die-attach pad to form a peripheral heat pad for dissipating heat.
14. A process as in claim 13, wherein one of said heat pads has an appearance distinctive from other heat pads in said lead frame.
15. A process as in claim 11, further comprising the operation of plating said die-attach pad with palladium.
16. A process as in claim 11, wherein a distinctive pattern is formed on said resin material by said encapsulating step.
17. A process as in claim 11, further comprising the operation of attaching solder balls to the bottom sides of corresponding leads.
18. A process as in claim 11, wherein said attaching step provides a soft solder to attach said semiconductor die to said die-attach pad.
19. A lead frame, comprising:
a die-attach pad;
an annular row of inner leads;
an annular row of outer leads connected to said annular row of inner leads by a connecting portion, wherein said die-attach pad is connected is to said annular row of inner leads and said annular row of outer leads by a plurality of tie bars.
20. A lead frame as in claim 19, wherein said connecting portion has a thickness which is half the thickness of a lead in said annular row of inner leads.
21. A lead frame as in claim 19, wherein leads in said annular row of inner leads and said annular row of outer leads are arranged in an alternating fashion.
22. A lead frame as in claim 19, wherein said lead frame is a lead frame within a matrix of substantially identical lead frames, and said matrix being one of multiple matrices of lead frames formed in a metal strip.
US10/269,327 1998-06-10 2002-10-10 Saw singulated leadless plastic chip carrier Abandoned US20030102537A1 (en)

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Application Number Priority Date Filing Date Title
US09/095,803 US6229200B1 (en) 1998-06-10 1998-06-10 Saw-singulated leadless plastic chip carrier
US09/363,249 US6242281B1 (en) 1998-06-10 1999-07-28 Saw-singulated leadless plastic chip carrier
US09/793,367 US20010030355A1 (en) 1998-06-10 2001-02-26 Saw-singulated leadless plastic chip carrier
US10/269,327 US20030102537A1 (en) 1998-06-10 2002-10-10 Saw singulated leadless plastic chip carrier

Applications Claiming Priority (1)

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US10/269,327 US20030102537A1 (en) 1998-06-10 2002-10-10 Saw singulated leadless plastic chip carrier

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US09/793,367 Continuation US20010030355A1 (en) 1998-06-10 2001-02-26 Saw-singulated leadless plastic chip carrier

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US20030102537A1 true US20030102537A1 (en) 2003-06-05

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US09/095,803 Expired - Lifetime US6229200B1 (en) 1998-06-10 1998-06-10 Saw-singulated leadless plastic chip carrier
US09/363,249 Expired - Lifetime US6242281B1 (en) 1998-06-10 1999-07-28 Saw-singulated leadless plastic chip carrier
US09/793,367 Abandoned US20010030355A1 (en) 1998-06-10 2001-02-26 Saw-singulated leadless plastic chip carrier
US10/026,399 Abandoned US20020056856A1 (en) 1998-06-10 2001-12-21 Saw singulated leadless plastic chip carrier
US10/269,327 Abandoned US20030102537A1 (en) 1998-06-10 2002-10-10 Saw singulated leadless plastic chip carrier
US11/071,737 Expired - Lifetime US7482690B1 (en) 1998-06-10 2005-03-03 Electronic components such as thin array plastic packages and process for fabricating same

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US09/363,249 Expired - Lifetime US6242281B1 (en) 1998-06-10 1999-07-28 Saw-singulated leadless plastic chip carrier
US09/793,367 Abandoned US20010030355A1 (en) 1998-06-10 2001-02-26 Saw-singulated leadless plastic chip carrier
US10/026,399 Abandoned US20020056856A1 (en) 1998-06-10 2001-12-21 Saw singulated leadless plastic chip carrier

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Cited By (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040104457A1 (en) * 2002-11-27 2004-06-03 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US7183630B1 (en) * 2002-04-15 2007-02-27 Amkor Technology, Inc. Lead frame with plated end leads
US20090209064A1 (en) * 2006-04-28 2009-08-20 Somchai Nonahasitthichai Lead frame land grid array
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US20100124801A1 (en) * 2007-02-16 2010-05-20 Richtek Technology Corp. Electronic package structure and method
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US20130075885A1 (en) * 2011-09-27 2013-03-28 STMICROELECTRONICS (SHENZHEN) MANUFACTURING Co., Ltd. Lead frame and packaging method
US8441110B1 (en) 2006-06-21 2013-05-14 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8698291B2 (en) 2011-12-15 2014-04-15 Freescale Semiconductor, Inc. Packaged leadless semiconductor device
US8710636B1 (en) * 2013-02-04 2014-04-29 Freescale Semiconductor, Inc. Lead frame array package with flip chip die attach
US8803302B2 (en) * 2012-05-31 2014-08-12 Freescale Semiconductor, Inc. System, method and apparatus for leadless surface mounted semiconductor package
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation

Families Citing this family (261)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130473A (en) * 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US8330270B1 (en) 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
US7271032B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6989294B1 (en) 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6933594B2 (en) * 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US7226811B1 (en) 1998-06-10 2007-06-05 Asat Ltd. Process for fabricating a leadless plastic chip carrier
US7247526B1 (en) 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
US7270867B1 (en) 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier
US7332375B1 (en) * 1998-06-24 2008-02-19 Amkor Technology, Inc. Method of making an integrated circuit package
US7005326B1 (en) * 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
JP2000164788A (en) 1998-11-20 2000-06-16 Anam Semiconductor Inc Lead frame for semiconductor package and semiconductor package using the lead frame and its manufacture
US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
KR100878939B1 (en) * 1999-06-30 2009-01-19 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
KR200309906Y1 (en) * 1999-06-30 2003-04-14 앰코 테크놀로지 코리아 주식회사 lead frame for fabricating semiconductor package
JP3461332B2 (en) * 1999-09-10 2003-10-27 松下電器産業株式会社 Lead frames and the resin package and a photoelectron device using the same
KR20010037252A (en) 1999-10-15 2001-05-07 마이클 디. 오브라이언 Mold for manufacturing semiconductor package
KR100355794B1 (en) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 leadframe and semiconductor package using the same
KR20010037254A (en) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 Semiconductor package
KR100355796B1 (en) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 structure of leadframe for semiconductor package and mold for molding the same
KR100403142B1 (en) 1999-10-15 2003-10-30 앰코 테크놀로지 코리아 주식회사 semiconductor package
KR100355795B1 (en) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 manufacturing method of semiconductor package
KR100364978B1 (en) 1999-10-15 2002-12-16 앰코 테크놀로지 코리아 주식회사 Clamp and Heat Block for Wire Bonding in Semiconductor Package
KR100526844B1 (en) 1999-10-15 2005-11-08 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
US6525406B1 (en) * 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
KR20010037247A (en) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 Semiconductor package
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6476478B1 (en) 1999-11-12 2002-11-05 Amkor Technology, Inc. Cavity semiconductor package with exposed leads and die pad
KR20010056618A (en) 1999-12-16 2001-07-04 프랑크 제이. 마르쿠치 Semiconductor package
KR100421774B1 (en) * 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
US6639308B1 (en) * 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
KR100426494B1 (en) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method
KR20010058583A (en) 1999-12-30 2001-07-06 마이클 디. 오브라이언 Lead End Grid Array Semiconductor package
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
KR100559664B1 (en) 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 Semiconductor package
KR100583494B1 (en) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 Semiconductor package
US6459147B1 (en) * 2000-03-27 2002-10-01 Amkor Technology, Inc. Attaching semiconductor dies to substrates with conductive straps
TW447096B (en) * 2000-04-01 2001-07-21 Siliconware Prec Ind Co Ltd Semiconductor packaging with exposed die
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6518659B1 (en) 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
US6424031B1 (en) 2000-05-08 2002-07-23 Amkor Technology, Inc. Stackable package with heat sink
JP2001320007A (en) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd Frame for resin sealed semiconductor device
JP4349541B2 (en) 2000-05-09 2009-10-21 大日本印刷株式会社 Frame for resin-encapsulated semiconductor device
JP4840893B2 (en) * 2000-05-12 2011-12-21 大日本印刷株式会社 Frame for resin-encapsulated semiconductor device
US6667544B1 (en) 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
US7288833B2 (en) * 2000-09-13 2007-10-30 Carsem (M) Sdn. Bhd. Stress-free lead frame
US6867483B2 (en) * 2000-09-13 2005-03-15 Carsen Semiconductor Sdn. Bhd. Stress-free lead frame
SG112799A1 (en) * 2000-10-09 2005-07-28 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US6454046B1 (en) 2000-10-27 2002-09-24 Po-An Chuang Synchronous dustproof cover structure for sound membrane
US6448107B1 (en) * 2000-11-28 2002-09-10 National Semiconductor Corporation Pin indicator for leadless leadframe packages
KR20020058209A (en) 2000-12-29 2002-07-12 마이클 디. 오브라이언 Semiconductor package
KR100731007B1 (en) * 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 stack-type semiconductor package
KR100394030B1 (en) * 2001-01-15 2003-08-06 앰코 테크놀로지 코리아 주식회사 stack-type semiconductor package
US6424024B1 (en) * 2001-01-23 2002-07-23 Siliconware Precision Industries Co., Ltd. Leadframe of quad flat non-leaded package
US6674156B1 (en) * 2001-02-09 2004-01-06 National Semiconductor Corporation Multiple row fine pitch leadless leadframe package with use of half-etch process
US6661083B2 (en) 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US6545347B2 (en) * 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100393448B1 (en) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6614102B1 (en) 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
DE10124970B4 (en) * 2001-05-21 2007-02-22 Infineon Technologies Ag Electronic component having a semiconductor chip on a semiconductor chip connection board, system unit and methods for their preparation
US6668449B2 (en) * 2001-06-25 2003-12-30 Micron Technology, Inc. Method of making a semiconductor device having an opening in a solder mask
US20040053447A1 (en) * 2001-06-29 2004-03-18 Foster Donald Craig Leadframe having fine pitch bond fingers formed using laser cutting method
DE10132385B4 (en) * 2001-07-06 2006-07-13 Infineon Technologies Ag Electronic component, a benefit and a system carrier for such a component with distributed on their undersides external contacts, and processes for the preparation thereof
US6734552B2 (en) 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US7015072B2 (en) 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
SG120858A1 (en) * 2001-08-06 2006-04-26 Micron Technology Inc Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same
DE10137956A1 (en) * 2001-08-07 2002-10-31 Infineon Technologies Ag Electronic component comprises a semiconductor chip on an island embedded in a flat plastic housing having an exposed surface of the island in the center of its lower side and metallic external edge contacts arranged on its edge sides
US7102216B1 (en) 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US6953992B2 (en) * 2001-09-20 2005-10-11 Infineon Technologies Ag Electronic component with at least one semiconductor chip and method for its manufacture
DE10147376B4 (en) * 2001-09-26 2009-01-15 Infineon Technologies Ag The electronic component and the carrier system as well as methods for producing the same
DE10147375B4 (en) * 2001-09-26 2006-06-08 Infineon Technologies Ag the same electronic component having a semiconductor chip and method for producing
DE10148120B4 (en) * 2001-09-28 2007-02-01 Infineon Technologies Ag Electronic components with semiconductor chip and a system carrier having component positions and to processes for the preparation of a leadframe
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6611047B2 (en) * 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6630726B1 (en) 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
KR100781149B1 (en) 2001-12-21 2007-11-30 삼성테크윈 주식회사 Lead-frame strip and process for manufacturing semiconductor packages using the same
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
TW533566B (en) 2002-01-31 2003-05-21 Siliconware Prec Ind Co Ltd Short-prevented lead frame and method for fabricating semiconductor package with the same
US6790710B2 (en) * 2002-01-31 2004-09-14 Asat Limited Method of manufacturing an integrated circuit package
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6838751B2 (en) * 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe
US20030178719A1 (en) * 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US6667073B1 (en) 2002-05-07 2003-12-23 Quality Platers Limited Leadframe for enhanced downbond registration during automatic wire bond process
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6734044B1 (en) 2002-06-10 2004-05-11 Asat Ltd. Multiple leadframe laminated IC package
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6940154B2 (en) * 2002-06-24 2005-09-06 Asat Limited Integrated circuit package and method of manufacturing the integrated circuit package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
TW560026B (en) * 2002-08-27 2003-11-01 Uni Tek System Inc Singulation method of the array-type work piece to be singulated having metal layer singulation street, and the array-type work piece to be singulated applying the method
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6821817B1 (en) 2002-09-03 2004-11-23 Asat Ltd. Premolded cavity IC package
US7732914B1 (en) 2002-09-03 2010-06-08 Mclellan Neil Cavity-type integrated circuit package
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6794738B2 (en) 2002-09-23 2004-09-21 Texas Instruments Incorporated Leadframe-to-plastic lock for IC package
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6872599B1 (en) * 2002-12-10 2005-03-29 National Semiconductor Corporation Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP)
US7071545B1 (en) 2002-12-20 2006-07-04 Asat Ltd. Shielded integrated circuit package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US7342318B2 (en) * 2003-01-21 2008-03-11 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US20050184368A1 (en) * 2003-01-21 2005-08-25 Huang Chien P. Semiconductor package free of substrate and fabrication method thereof
US20050194665A1 (en) * 2003-01-21 2005-09-08 Huang Chien P. Semiconductor package free of substrate and fabrication method thereof
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Prec Ind Co Ltd Semiconductor package and fabricating method thereof
US7271493B2 (en) 2003-01-21 2007-09-18 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US7002239B1 (en) * 2003-02-14 2006-02-21 National Semiconductor Corporation Leadless leadframe packaging panel featuring peripheral dummy leads
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6927483B1 (en) * 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
TW200418149A (en) * 2003-03-11 2004-09-16 Siliconware Prec Ind Co Ltd Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US20070031996A1 (en) * 2003-04-26 2007-02-08 Chopin Sheila F Packaged integrated circuit having a heat spreader and method therefor
TW200425427A (en) * 2003-05-02 2004-11-16 Siliconware Prec Ind Co Ltd Leadframe-based non-leaded semiconductor package and method of fabricating the same
US6894376B1 (en) 2003-06-09 2005-05-17 National Semiconductor Corporation Leadless microelectronic package and a method to maximize the die size in the package
JP2007528120A (en) * 2003-07-03 2007-10-04 テッセラ テクノロジーズ ハンガリー コルラートルト フェレロェセーギュー タールシャシャーグ How to packaging integrated circuit devices and device
DE10332017A1 (en) * 2003-07-14 2005-03-03 Infineon Technologies Ag Electronic component and leadframe for producing the component
CN1571130B (en) 2003-07-15 2010-04-28 品质有限公 Lead frame for reinforcing lower joint alignment in automatic lead bonding process
US6815806B1 (en) 2003-07-17 2004-11-09 International Business Machines Corp. Asymmetric partially-etched leads for finer pitch semiconductor chip package
US8211753B2 (en) * 2003-08-26 2012-07-03 Stats Chippac Ltd. Leadframe-based mold array package heat spreader and fabrication method therefor
US6903304B1 (en) 2003-09-12 2005-06-07 Asat Ltd. Process for dressing molded array package saw blade
US7033517B1 (en) 2003-09-15 2006-04-25 Asat Ltd. Method of fabricating a leadless plastic chip carrier
US7224056B2 (en) * 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US6936922B1 (en) 2003-09-26 2005-08-30 Amkor Technology, Inc. Semiconductor package structure reducing warpage and manufacturing method thereof
US6977431B1 (en) 2003-11-05 2005-12-20 Amkor Technology, Inc. Stackable semiconductor package and manufacturing method thereof
US20050139984A1 (en) * 2003-12-19 2005-06-30 Tessera, Inc. Package element and packaged chip having severable electrically conductive ties
US20050146057A1 (en) * 2003-12-31 2005-07-07 Khor Ah L. Micro lead frame package having transparent encapsulant
US7009286B1 (en) 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
US7049177B1 (en) 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
TWM253056U (en) * 2004-02-13 2004-12-11 Optimum Care Int Tech Inc Compact chip packaging structure
US7053469B2 (en) * 2004-03-30 2006-05-30 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package and manufacturing method thereof
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
KR101070890B1 (en) * 2004-04-16 2011-10-06 삼성테크윈 주식회사 Method for manufacturing the semiconductor package of multi-row lead type
TWI244169B (en) * 2004-05-12 2005-11-21 Siliconware Prec Ind Co Ltd High electric performance semiconductor package
US7091581B1 (en) 2004-06-14 2006-08-15 Asat Limited Integrated circuit package and process for fabricating the same
US7411289B1 (en) 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US7087986B1 (en) 2004-06-18 2006-08-08 National Semiconductor Corporation Solder pad configuration for use in a micro-array integrated circuit package
US7064419B1 (en) 2004-06-18 2006-06-20 National Semiconductor Corporation Die attach region for use in a micro-array integrated circuit package
US7259460B1 (en) 2004-06-18 2007-08-21 National Semiconductor Corporation Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package
US7186588B1 (en) 2004-06-18 2007-03-06 National Semiconductor Corporation Method of fabricating a micro-array integrated circuit package
US7595225B1 (en) 2004-10-05 2009-09-29 Chun Ho Fan Leadless plastic chip carrier with contact standoff
US7358119B2 (en) * 2005-01-12 2008-04-15 Asat Ltd. Thin array plastic package without die attach pad and process for fabricating the same
EP1856737A1 (en) 2005-02-23 2007-11-21 Nxp B.V. An integrated circuit package device with improved bond pad connections, a leadframe and an electronic device
WO2006090305A1 (en) 2005-02-23 2006-08-31 Nxp B.V. An integrated circuit device package with an additional contact pad, a lead frame and an electronic device
US8143095B2 (en) 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
US7498665B2 (en) * 2005-05-05 2009-03-03 Stats Chippac Ltd. Integrated circuit leadless package system
AT504250A2 (en) * 2005-06-30 2008-04-15 Fairchild Semiconductor Semiconductor chip package and method for manufacturing the same
US7348663B1 (en) 2005-07-15 2008-03-25 Asat Ltd. Integrated circuit package and method for fabricating same
US8786165B2 (en) * 2005-09-16 2014-07-22 Tsmc Solid State Lighting Ltd. QFN/SON compatible package with SMT land pads
US7410830B1 (en) 2005-09-26 2008-08-12 Asat Ltd Leadless plastic chip carrier and method of fabricating same
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
EP1795496A2 (en) * 2005-12-08 2007-06-13 Yamaha Corporation Semiconductor device for detecting pressure variations
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
WO2007067982A2 (en) * 2005-12-08 2007-06-14 Fairchild Semiconductor Corporation Flip chip mlp with conductive ink
US7936062B2 (en) 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
US7981702B2 (en) 2006-03-08 2011-07-19 Stats Chippac Ltd. Integrated circuit package in package system
US8513542B2 (en) * 2006-03-08 2013-08-20 Stats Chippac Ltd. Integrated circuit leaded stacked package system
US7986043B2 (en) * 2006-03-08 2011-07-26 Stats Chippac Ltd. Integrated circuit package on package system
TWI286375B (en) * 2006-03-24 2007-09-01 Chipmos Technologies Inc Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same
DE102006015241A1 (en) * 2006-03-30 2007-06-28 Infineon Technologies Ag Quad flat non-leaded package semiconductor component, has expansion joint arranged in plastic housing and provided between border angle region and outer contact surfaces of outer contact and central region of housing
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US8125077B2 (en) * 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US20080111219A1 (en) * 2006-11-14 2008-05-15 Gem Services, Inc. Package designs for vertical conduction die
US20080135991A1 (en) * 2006-12-12 2008-06-12 Gem Services, Inc. Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9947605B2 (en) * 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US7608482B1 (en) * 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US8207600B2 (en) * 2007-03-30 2012-06-26 Stats Chippac Ltd. Integrated circuit package system with encapsulating features
MY154596A (en) 2007-07-25 2015-06-30 Carsem M Sdn Bhd Thin plastic leadless package with exposed metal die paddle
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US7948066B2 (en) * 2007-12-26 2011-05-24 Stats Chippac Ltd. Integrated circuit package system with lead locking structure
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US7973393B2 (en) * 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
CN102341899B (en) 2009-03-06 2013-05-29 优特香港有限公司 Leadless array plastic package with various IC packaging configurations
JP2011517069A (en) * 2009-03-06 2011-05-26 カイシン インコーポレイテッド Leadless integrated circuit package having a high density contact
US8367476B2 (en) * 2009-03-12 2013-02-05 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
KR101753416B1 (en) 2009-04-03 2017-07-19 카이씬, 인코포레이티드 Leadframe for ic package and method of manufacture
CN101546713B (en) 2009-04-30 2010-12-01 强茂电子(无锡)有限公司 Manufacture method of plastic-packaged inline power rectifier
US7993981B2 (en) * 2009-06-11 2011-08-09 Lsi Corporation Electronic device package and method of manufacture
US20100314728A1 (en) * 2009-06-16 2010-12-16 Tung Lok Li Ic package having an inductor etched into a leadframe thereof
US9449900B2 (en) * 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
CN102576701B (en) 2009-09-02 2016-08-17 凯信公司 Package and method of manufacturing Ic
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8802500B2 (en) * 2009-11-11 2014-08-12 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8368189B2 (en) * 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
TWI392066B (en) * 2009-12-28 2013-04-01 Siliconware Prec Ind Co Ltd Package structure and fabrication method thereof
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
TWI453844B (en) * 2010-03-12 2014-09-21 Siliconware Prec Ind Co Ltd Quad flat no-lead package and method for forming the same
TWI479580B (en) * 2010-03-12 2015-04-01 Siliconware Prec Ind Co Ltd Quad flat no-lead package and method for forming the same
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
JP2011233811A (en) * 2010-04-30 2011-11-17 Renesas Electronics Corp Lead frame and semiconductor device manufacturing method using the same
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8581382B2 (en) * 2010-06-18 2013-11-12 Stats Chippac Ltd. Integrated circuit packaging system with leadframe and method of manufacture thereof
US8389330B2 (en) 2010-06-24 2013-03-05 Stats Chippac Ltd. Integrated circuit package system with package stand-off and method of manufacture thereof
US8390103B2 (en) 2010-07-12 2013-03-05 Analog Devices, Inc. Apparatus for integrated circuit packaging
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof
US8314479B2 (en) 2010-11-02 2012-11-20 Carsem (M) Sdn. Bhd. Leadframe package with recessed cavity for LED
KR20120048875A (en) * 2010-11-08 2012-05-16 삼성전자주식회사 Quad flat package with exposed paddle
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
KR101748334B1 (en) * 2011-01-17 2017-06-16 삼성전자 주식회사 Apparatus and method of fabricating white light emitting device
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US9064781B2 (en) 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
JP5204271B2 (en) * 2011-06-16 2013-06-05 株式会社東芝 The endoscope apparatus and a substrate
KR101297781B1 (en) * 2011-09-30 2013-08-20 에스티에스반도체통신 주식회사 A semiconductor package
MY156107A (en) * 2011-11-01 2016-01-15 Carsem M Sdn Bhd Large panel leadframe
CN102354691B (en) * 2011-11-04 2013-11-06 北京工业大学 Quad flat non-lead (QFN) package with high density and manufacturing method
CN102339809B (en) * 2011-11-04 2013-11-06 北京工业大学 QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US8587099B1 (en) * 2012-05-02 2013-11-19 Texas Instruments Incorporated Leadframe having selective planishing
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US9196504B2 (en) 2012-07-03 2015-11-24 Utac Dongguan Ltd. Thermal leadless array package with die attach pad locking feature
CN103021890B (en) * 2012-12-17 2016-06-29 北京工业大学 A method for manufacturing a device package qfn
CN103050419A (en) * 2012-12-17 2013-04-17 北京工业大学 Method for manufacturing QFN (quad flat non-lead package) with multiple rings of pin configuration
CN103021876B (en) * 2012-12-17 2016-06-01 北京工业大学 A method of manufacturing a high-density packaged device qfn
US9627305B2 (en) * 2013-07-11 2017-04-18 Infineon Technologies Ag Semiconductor module with interlocked connection
US9123735B2 (en) 2013-07-31 2015-09-01 Infineon Technologies Austria Ag Semiconductor device with combined passive device on chip back side
US9263419B2 (en) * 2013-08-30 2016-02-16 Infineon Technologies Ag Lead frame strips with electrical isolation of die paddles
US9935039B2 (en) 2013-12-10 2018-04-03 Carsem (M) Sdn. Bhd. Pre-molded integrated circuit packages
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US9337130B2 (en) * 2014-07-28 2016-05-10 Texas Instruments Incorporated Leadframe strip and leadframes
EP2993323B1 (en) 2014-09-04 2017-07-19 3M Innovative Properties Company Mounting mat for a pollution control element or a chemical reactor
US9659843B2 (en) 2014-11-05 2017-05-23 Infineon Technologies Ag Lead frame strip with molding compound channels
US20160218021A1 (en) * 2015-01-27 2016-07-28 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
JP2016192523A (en) * 2015-03-31 2016-11-10 ルネサスエレクトロニクス株式会社 Method for manufacturing semiconductor device
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9741643B2 (en) * 2016-01-22 2017-08-22 Texas Instruments Incorporated Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157480A (en) * 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier

Family Cites Families (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2524707B1 (en) 1982-04-01 1985-05-31 Cit Alcatel Method for encapsulating semiconductor components, and encapsulated components obtained
JPH0447977B2 (en) 1983-05-12 1992-08-05 Sony Corp
US4685998A (en) 1984-03-22 1987-08-11 Thomson Components - Mostek Corp. Process of forming integrated circuits with contact pads in a standard array
US4812896A (en) 1986-11-13 1989-03-14 Olin Corporation Metal electronic package sealed with thermoplastic having a grafted metal deactivator and antioxidant
US5066831A (en) 1987-10-23 1991-11-19 Honeywell Inc. Universal semiconductor chip package
EP0361975B1 (en) 1988-09-29 1995-05-24 Tomoegawa Paper Co. Ltd. Adhesive tapes
US5277972B1 (en) 1988-09-29 1996-11-05 Tomoegawa Paper Co Ltd Adhesive tapes
US5293072A (en) 1990-06-25 1994-03-08 Fujitsu Limited Semiconductor device having spherical terminals attached to the lead frame embedded within the package body
AT186795T (en) 1990-07-21 1999-12-15 Mitsui Chemicals Inc A semiconductor device having a package
EP0509065A4 (en) 1990-08-01 1994-02-09 Staktek Corporation
US5216278A (en) 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5596231A (en) * 1991-08-05 1997-01-21 Asat, Limited High power dissipation plastic encapsulated package for integrated circuit die
US5221642A (en) 1991-08-15 1993-06-22 Staktek Corporation Lead-on-chip integrated circuit fabrication method
US5200809A (en) 1991-09-27 1993-04-06 Vlsi Technology, Inc. Exposed die-attach heatsink package
EP0537982A3 (en) * 1991-10-14 1994-02-16 Fujitsu Ltd
US5332864A (en) 1991-12-27 1994-07-26 Vlsi Technology, Inc. Integrated circuit package having an interposer
US5214845A (en) 1992-05-11 1993-06-01 Micron Technology, Inc. Method for producing high speed integrated circuits
KR100260347B1 (en) 1992-06-05 2000-07-01 나까니시 히로유끼 Three-dimensional printed circuit board, electronic circuit package using this board, and method for manufacturing
US5608267A (en) 1992-09-17 1997-03-04 Olin Corporation Molded plastic semiconductor package including heat spreader
US5406124A (en) 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
US5457340A (en) 1992-12-07 1995-10-10 Integrated Device Technology, Inc. Leadframe with power and ground planes
US5327008A (en) 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
US5474958A (en) 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
US5430331A (en) 1993-06-23 1995-07-04 Vlsi Technology, Inc. Plastic encapsulated integrated circuit package having an embedded thermal dissipator
KR0152901B1 (en) 1993-06-23 1998-10-01 문정환 Plastic package and method for manufacture thereof
US5641997A (en) 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5976912A (en) 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US5701034A (en) 1994-05-03 1997-12-23 Amkor Electronics, Inc. Packaged semiconductor die including heat sink with locking feature
US5604376A (en) 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
KR0145768B1 (en) 1994-08-16 1998-08-01 김광호 Method for manufacturing a semiconductor package using lead frame
US5483099A (en) 1994-08-31 1996-01-09 Intel Corporation Standardized power and ground design for pin grid array packages
JP3400877B2 (en) * 1994-12-14 2003-04-28 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US5650663A (en) 1995-07-03 1997-07-22 Olin Corporation Electronic package with improved thermal properties
JP3123638B2 (en) 1995-09-25 2001-01-15 株式会社三井ハイテック Semiconductor device
US5696666A (en) 1995-10-11 1997-12-09 Motorola, Inc. Low profile exposed die chip carrier package
US5847455A (en) * 1995-11-07 1998-12-08 Vlsi Technology, Inc. Molded leadframe ball grid array
US5710695A (en) 1995-11-07 1998-01-20 Vlsi Technology, Inc. Leadframe ball grid array package
MY128748A (en) 1995-12-19 2007-02-28 Texas Instruments Inc Plastic packaging for a surface mounted integrated circuit
US5646831A (en) 1995-12-28 1997-07-08 Vlsi Technology, Inc. Electrically enhanced power quad flat pack arrangement
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5859475A (en) 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5726502A (en) 1996-04-26 1998-03-10 Motorola, Inc. Bumped semiconductor device with alignment features and method for making the same
US5847458A (en) 1996-05-21 1998-12-08 Shinko Electric Industries Co., Ltd. Semiconductor package and device having heads coupled with insulating material
KR0185512B1 (en) 1996-08-19 1999-03-20 김광호 Column lead type package and method of making the same
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
TW322613B (en) 1997-03-10 1997-12-11 guang-long Lin Continuous method of implementing solder bump on semiconductor wafer electrode
KR100230515B1 (en) 1997-04-04 1999-11-15 윤종용 Method for producting lead frame with uneven surface
US6025640A (en) 1997-07-16 2000-02-15 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device
EP0903780A3 (en) 1997-09-19 1999-08-25 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits
JP3285815B2 (en) 1998-03-12 2002-05-27 松下電器産業株式会社 Lead frame, a resin-encapsulated semiconductor device and a manufacturing method thereof
US6635957B2 (en) 1998-06-10 2003-10-21 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6585905B1 (en) 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US6989294B1 (en) 1998-06-10 2006-01-24 Asat, Ltd. Leadless plastic chip carrier with etch back pad singulation
US6294100B1 (en) 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6933594B2 (en) 1998-06-10 2005-08-23 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6872661B1 (en) 1998-06-10 2005-03-29 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation and die attach pad array
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6057601A (en) 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
DE19905055A1 (en) 1999-02-08 2000-08-17 Siemens Ag A semiconductor device comprising a chip carrier having openings for contacting
US6208020B1 (en) 1999-02-24 2001-03-27 Matsushita Electronics Corporation Leadframe for use in manufacturing a resin-molded semiconductor device
US6204553B1 (en) 1999-08-10 2001-03-20 Walsin Advanced Electronics Ltd. Lead frame structure
US6489557B2 (en) 1999-08-30 2002-12-03 Intel Corporation Implementing micro BGA™ assembly techniques for small die
JP3062192B1 (en) 1999-09-01 2000-07-10 松下電子工業株式会社 Li - Dofure - beam and method of manufacturing a resin-sealed semiconductor device using the same
US6261864B1 (en) 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6306685B1 (en) 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
US6238952B1 (en) 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6372539B1 (en) 2000-03-20 2002-04-16 National Semiconductor Corporation Leadless packaging process using a conductive substrate
US6762118B2 (en) 2000-10-10 2004-07-13 Walsin Advanced Electronics Ltd. Package having array of metal pegs linked by printed circuit lines
TW458377U (en) 2000-11-23 2001-10-01 Siliconware Prec Ind Co Ltd Sensor structure of quad flat package without external leads
TW488042B (en) 2000-11-30 2002-05-21 Siliconware Prec Ind Co Ltd Quad flat non-leaded package and its leadframe
JP3895570B2 (en) 2000-12-28 2007-03-22 株式会社ルネサステクノロジ Semiconductor device
US6545347B2 (en) 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
TW579581B (en) 2001-03-21 2004-03-11 Ultratera Corp Semiconductor device with chip separated from substrate and its manufacturing method
JP3609737B2 (en) * 2001-03-22 2005-01-12 三洋電機株式会社 Method of manufacturing a circuit device
TW586205B (en) * 2001-06-26 2004-05-01 Intel Corp Electronic assembly with vertically connected capacitors and manufacturing method
US6828661B2 (en) 2001-06-27 2004-12-07 Matsushita Electric Industrial Co., Ltd. Lead frame and a resin-sealed semiconductor device exhibiting improved resin balance, and a method for manufacturing the same
US20030006055A1 (en) 2001-07-05 2003-01-09 Walsin Advanced Electronics Ltd Semiconductor package for fixed surface mounting
KR100445072B1 (en) 2001-07-19 2004-08-21 삼성전자주식회사 Bumped chip carrier package using lead frame and method for manufacturing the same
JP2003031753A (en) 2001-07-19 2003-01-31 Sony Corp Semiconductor device and manufacturing method therefor
JP3879452B2 (en) 2001-07-23 2007-02-14 松下電器産業株式会社 Resin-sealed semiconductor device and a manufacturing method thereof
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2004071899A (en) 2002-08-07 2004-03-04 Kanto Sanyo Semiconductors Co Ltd Circuit device and its producing method
US6777788B1 (en) 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad
US6930377B1 (en) 2002-12-04 2005-08-16 National Semiconductor Corporation Using adhesive materials as insulation coatings for leadless lead frame semiconductor packages
US6879034B1 (en) * 2003-05-01 2005-04-12 Amkor Technology, Inc. Semiconductor package including low temperature co-fired ceramic substrate
JP2005191240A (en) 2003-12-25 2005-07-14 Renesas Technology Corp Semiconductor device and method for manufacturing the same
KR100586699B1 (en) 2004-04-29 2006-06-08 삼성전자주식회사 Semiconductor chip package and manufacturing method therof
TWI265617B (en) 2005-01-11 2006-11-01 Siliconware Prec Ind Co Ltd Lead-frame-based semiconductor package with lead frame and lead frame thereof
US20060170081A1 (en) 2005-02-03 2006-08-03 Gerber Mark A Method and apparatus for packaging an electronic chip
US7405106B2 (en) 2006-05-23 2008-07-29 International Business Machines Corporation Quad flat no-lead chip carrier with stand-off

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5157480A (en) * 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier

Cited By (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9224676B1 (en) 1998-06-24 2015-12-29 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8853836B1 (en) 1998-06-24 2014-10-07 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8963301B1 (en) 1998-06-24 2015-02-24 Amkor Technology, Inc. Integrated circuit package and method of making the same
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US8102037B2 (en) 2001-03-27 2012-01-24 Amkor Technology, Inc. Leadframe for semiconductor package
US7183630B1 (en) * 2002-04-15 2007-02-27 Amkor Technology, Inc. Lead frame with plated end leads
US8129222B2 (en) * 2002-11-27 2012-03-06 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US20040104457A1 (en) * 2002-11-27 2004-06-03 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US9099317B2 (en) * 2006-04-28 2015-08-04 Utac Thai Limited Method for forming lead frame land grid array
US20090209064A1 (en) * 2006-04-28 2009-08-20 Somchai Nonahasitthichai Lead frame land grid array
US8441110B1 (en) 2006-06-21 2013-05-14 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US20100124801A1 (en) * 2007-02-16 2010-05-20 Richtek Technology Corp. Electronic package structure and method
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US8304866B1 (en) 2007-07-10 2012-11-06 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7872343B1 (en) 2007-08-07 2011-01-18 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8283767B1 (en) 2007-08-07 2012-10-09 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8319338B1 (en) 2007-10-01 2012-11-27 Amkor Technology, Inc. Thin stacked interposer package
US8227921B1 (en) 2007-10-03 2012-07-24 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making same
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US8729710B1 (en) 2008-01-16 2014-05-20 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7906855B1 (en) 2008-01-21 2011-03-15 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US8084868B1 (en) 2008-04-17 2011-12-27 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US8299602B1 (en) 2008-09-30 2012-10-30 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US8432023B1 (en) 2008-10-06 2013-04-30 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8823152B1 (en) 2008-10-27 2014-09-02 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8188579B1 (en) 2008-11-21 2012-05-29 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8558365B1 (en) 2009-01-09 2013-10-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8729682B1 (en) 2009-03-04 2014-05-20 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9508631B1 (en) 2011-01-27 2016-11-29 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US9275939B1 (en) 2011-01-27 2016-03-01 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US20130075885A1 (en) * 2011-09-27 2013-03-28 STMICROELECTRONICS (SHENZHEN) MANUFACTURING Co., Ltd. Lead frame and packaging method
CN103021991A (en) * 2011-09-27 2013-04-03 意法半导体制造(深圳)有限公司 Lead frame and encapsulation method
US8736038B2 (en) * 2011-09-27 2014-05-27 Stmicroelectronics S.R.L. Lead frame having increased stability due to reinforced die pads and packaging method using such lead frame
US8698291B2 (en) 2011-12-15 2014-04-15 Freescale Semiconductor, Inc. Packaged leadless semiconductor device
US9159588B2 (en) 2011-12-15 2015-10-13 Freescale Semiconductor, Inc. Packaged leadless semiconductor device
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US8803302B2 (en) * 2012-05-31 2014-08-12 Freescale Semiconductor, Inc. System, method and apparatus for leadless surface mounted semiconductor package
US9263375B2 (en) 2012-05-31 2016-02-16 Freescale Semiconductor, Inc. System, method and apparatus for leadless surface mounted semiconductor package
US8710636B1 (en) * 2013-02-04 2014-04-29 Freescale Semiconductor, Inc. Lead frame array package with flip chip die attach
US8969139B2 (en) 2013-02-04 2015-03-03 Freescale Semiconductor, Inc. Lead frame array package with flip chip die attach
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9543235B2 (en) 2013-10-24 2017-01-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method

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US20020056856A1 (en) 2002-05-16
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US20010030355A1 (en) 2001-10-18
US6242281B1 (en) 2001-06-05

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