US20020100165A1 - Method of forming an integrated circuit device package using a temporary substrate - Google Patents
Method of forming an integrated circuit device package using a temporary substrate Download PDFInfo
- Publication number
- US20020100165A1 US20020100165A1 US09/504,007 US50400700A US2002100165A1 US 20020100165 A1 US20020100165 A1 US 20020100165A1 US 50400700 A US50400700 A US 50400700A US 2002100165 A1 US2002100165 A1 US 2002100165A1
- Authority
- US
- United States
- Prior art keywords
- plastic sheet
- package
- metal layer
- die pad
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 88
- 239000000758 substrate Substances 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 107
- 239000002985 plastic film Substances 0.000 claims abstract description 93
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 46
- 239000000853 adhesive Substances 0.000 claims abstract description 22
- 230000001070 adhesive effect Effects 0.000 claims abstract description 22
- 239000004033 plastic Substances 0.000 claims abstract description 15
- 229920003023 plastic Polymers 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 64
- 229910052802 copper Inorganic materials 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 239000002904 solvent Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 5
- 238000012216 screening Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 35
- 239000011324 bead Substances 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000007788 liquid Substances 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 229920006255 plastic film Polymers 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- -1 polypropylene acetate Polymers 0.000 description 2
- 238000005096 rolling process Methods 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- 229920002799 BoPET Polymers 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 229920002302 Nylon 6,6 Polymers 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
- H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48724—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- Roche et al. begins with a metal temporary substrate. A layer of a low melting-point alloy is applied onto to the metal temporary substrate. Next a plurality of metal die pads and leads are formed on the low-melting point alloy layer. An integrated circuit device is placed on each of the die pads and connected to the leads surrounding the respective die pad. The integrated circuit devices are then encapsulated in a single block of encapsulant material. Individual packages are then cut from the block of hardened encapsulant.
- a package marketed by Toshiba Corporation of Japan under the name "BCC” is believed to be made as follows.
- a copper sheet is partially etched through in certain locations, forming pockets isolated by unetched copper.
- a central pocket is surrounded by several smaller satellite pockets.
- the copper sheet is then masked, leaving the pockets exposed.
- the pockets are plated with layers of gold, nickel, and gold.
- An integrated circuit device is placed in the central pocket. (In some embodiments, there is no central pocket, so the device is simply placed on the copper sheet.)
- Bond wires are connected between the device and the satellite pockets.
- the device and bond wires are encapsulated.
- the remainder of the copper sheet is etched away by acid, forming a completed package. Once the copper is removed, the metal plated into the satellite pockets forms the leads of the package, and the metal plated into the central depression (if any) is the die pad.
- the present invention includes a method of manufacturing a package for housing an integrated circuit device.
- Step 1 provides a plastic sheet having an adhesive first surface.
- the plastic sheet may be plastic tape.
- Step 2 attaches a metal sheet onto the first surface of the plastic sheet, and then forms an array of package sites by selectively removing portions of the metal sheet.
- Each package site includes a die pad and a plurality of satellite leads around the die pad.
- Step 3 attaches an integrated circuit device to each of the die pads.
- Step 4 connects a conductor, such a bond wire, between each of a plurality of conductive pads on the integrated circuit device and one of the leads of the respective package site.
- Step 5 applies an encapsulating material onto the first surface of the plastic sheets, integrated circuit devices, the leads, and the electrical conductors of each package site.
- Step 6 hardens the encapsulating material.
- Step 7 removes the plastic sheet.
- Optional Step 8 applies solder balls to the exposed surfaces of the leads of the package sites.
- Step 9 separates individual packages from the encapsulated array.
- An alternative embodiment in an LCC style package requires no solder balls.
- An embodiment encompassed within the present invention includes forming a reentrant portion (or reentrant portions) and aspirates on the side surfaces of the die pads and leads of the package sites.
- the encapsulant material flows into the reentrant portions and aspirates.
- the reentrant portions and aspirates engage the encapsulant material and lock the die pad and leads to the encapsulant material of the package.
- the present invention overcomes the disadvantages of the prior art by, among other things, the use of an inexpensive plastic sheet as a base for forming the packages, and by the formation of encapsulant locking features on the side surfaces of the die pad and leads.
- Figure 1 is a flow chart of a method of forming a package for an integrated circuit device.
- Figure 2 is cross-sectional side view of a plated metal sheet on a plastic sheet.
- Figure 3 is a cross-sectional side view of an array of package sites each including a die pad and leads.
- Figure 4 is a top plan view of the array of package sites shown in Figure 3.
- Figure 5 is a cross-sectional side view of these integrated circuit devices placed on and wire-bonded to leads of respective package sites.
- Figure 6 is a cross-sectional side view of an array of package sites after encapsulation by either liquid encapsulation or molding techniques.
- Figure 7 is a cross-sectional side view of the array of Figure 5 after removal of the plastic sheet and attachment of solder balls to the leads.
- Figure 8 is a cross-sectional side view an inverted array of packages after the encapsulant material is cut with a saw.
- Figure 9 is a cross-sectional side view of a completed package.
- Figure 10 is a top plan view of an array of package sites with a bead of adhesive material around the array.
- Figure 11 is a cross-sectional side view of a completed package showing a first alternative side surface of a die pad and leads.
- Figure 12 is a cross-sectional side view of an array of individually molded package bodies.
- Figure 13 is a cross-sectional side view of a completed package showing a second alternative side surface of a die pad and leads.
- Fig. 14 is a plan view of a package site having two rows of staggered leads around the die pad.
- FIG. 15 is a flow chart of an alternative method of making a package.
- Fig. 16 is a cross-sectional side view of a plastic sheet having a first metal layer and a second metal layer thereon that serves as a mask for etching the first metal layer.
- Fig. 17 is a cross-sectional side view of the die pad and leads of a package site formed by the method of Fig. 14.
- FIG. 18 is a flow chart of an alternative method of forming a package.
- Fig. 19 is a cross-sectional side view of a plastic sheet with two layers of an electrically-conductive media thereon, where the layers define an array of package sites.
- Figure 1 is a flow chart of an exemplary method 5 in accordance with the present invention for forming a package for an integrated circuit device.
- An example of a completed package 37 that may be formed by method 5 of Figure 1 is shown in Figure 9.
- package 37 of Figure 9 includes a semiconductor integrated circuit device 28 mounted on a metal die pad 20.
- a plurality of metal leads 24 are adjacent to die pad 20 and are connected by bond wires 29 to conductive pads (not shown) on device 28.
- Encapsulant material 32 forms the package body, and covers device 28, bond wires 29, and the upper and side surfaces of die pad 20 and leads 24. The lower surface of die pad 20 is exposed.
- Solder balls 34 are attached to the lower surface of leads 24, although solder balls are optional.
- Figure 1 provides a method 5 of making a package like package 37 of Figure 9.
- Step 1 of Figure 1 provides a plastic sheet formed of a plastic material.
- Plastic sheet 10 has a first surface 11 and an opposite second surface 12.
- An adhesive is present on or applied to first surface 11 of plastic sheet 10.
- Plastic sheet 10 may be a segment having a size of, for example, 5 cm by 20 cm, and a thickness of about 25 to 75 microns. The size and thickness of plastic sheet 10 can vary. Alternatively, plastic sheet 10 may be a plastic tape that is on a roll. As described below, the process of Figure 1 may be performed as a reel to reel process.
- Plastic sheet 10 is formed of a conventional plastic material such as polyvinyl chloride, polyvinyl alcohol acetate, polypropylene acetate, vinyl, polyethylene, mylar, or polyimide.
- a conventional plastic material such as polyvinyl chloride, polyvinyl alcohol acetate, polypropylene acetate, vinyl, polyethylene, mylar, or polyimide.
- An example brand of plastic tape is KAPTON polyimide tape from the Dupont Company.
- Step 2 of Figure 1 provides a patterned metal sheet on the first surface of the plastic sheet.
- Figures 2 and 3 show one embodiment of a method of performing Step 2 of Figure 1.
- a metal sheet 13 is first attached to the adhesive first surface 11 of plastic sheet 10.
- Metal sheet 13 of Figure 2 has a first surface 14 attached to first surface 11 of plastic sheet 10, and an opposite second surface 15.
- an adhesive material is applied to first surface 14 of metal sheet 13 rather than to first surface 11 of plastic sheet 10.
- metal sheet 13 consists of an underlying first metal layer 16 on first surface 11 of plastic sheet 10, and a second metal layer 17 that is plated onto a top surface of first metal layer 16 opposite first surface 11 of plastic sheet 10.
- First metal layer 16 of metal sheet 13 may be formed, for example, of copper, a copper alloy, or Alloy 42. Plated metal layer 17 may be nickel gold, silver, platinum, palladium, or another noble metal. Using nickel/gold plating or silver plating may facilitate bond wire connections. Where copper is used for metal sheet 13, without plating, copper bond wires may be used.
- first surface 14 of metal sheet 13 also may be plated.
- Metal sheet 13 may have a thickness of, for example, 100 to 250 microns.
- metal sheet 13 is etched to form an array of package sites.
- etching is performed by chemical etching using a patterned photoresist mask.
- a layer of photoresist is applied onto second surface 15 of metal sheet 13.
- the photoresist is exposed to light through a patterned reticle or the like, and is subsequently developed to form a mask.
- Chemicals are sprayed or otherwise applied to the masked metal strip, and exposed portions of metal are etched away, leaving the desired pattern.
- acids are used to etch the metal.
- plastic film 10 must not be substantially attacked by the chemical used to etch metal sheet 13.
- a cleaning step may be necessary to remove residue or other undesirable materials after Step 2 (or any of the other steps) of Figure 1.
- Figure 3 is a cross-sectional side view of an array 18 of three identical package sites 19 formed by the above-described chemical etching of metal sheet 13.
- Figure 4 is a top plan view of array 18 of Figure 3.
- each package site 19 includes a metal die pad 20 and metal leads 24.
- Die pad 20 and leads 24 are formed from metal layer 16 and metal layer 17 of metal sheet 13 of Figure 2.
- Figure 4 shows that each die pad 20 has a rectangular perimeter and is surrounded on each of its four sides by four leads 24. Leads 24 also have a rectangular perimeter.
- the perimeter shapes of die pad 20 and leads 24 can vary.
- leads 24 can have a rectangular or circular perimeter.
- the number and positioning of the leads can vary.
- 64 or 128 leads may be selected.
- two or more staggered rows of leads 24 may be provided adjacent to two or all four sides of die pad 20.
- Fig. 14 is a plan view of an exemplary embodiment of a package site 19 where two staggered rows of leads 24 surround die pad 20.
- each die pad 20 has a first surface 21 attached to first surface 11 of plastic sheet 10, an opposite second surface 22, and side surfaces 23 at the periphery of die pad 20 between first surface 21 and second surface 22.
- Each lead 24 has a first surface 25 attached to first surface 11 of plastic sheet 10, an opposite second surface 26, and side surfaces 27 at the periphery of lead 24 between first surface 25 and second surface 26.
- Step 3 of Figure 1 places an integrated circuit device onto each of the die pads.
- Step 4 of Figure 1 connects a conductor, such a bond wire, between each of a plurality of conductive pads on each of the integrated circuit device and one of the leads of that integrated circuit device's respective package site.
- Figure 5 is a cross-sectional side view of three integrated circuit devices 28 placed on second surface 22 of these die pads 20. Each integrated circuit device 28 is placed on a die pad 20 and is adhesively attached to second surface 22 of die pad 20 using conventional die attach equipment and adhesives.
- Each integrated circuit device 28 of Figure 5 includes conductive pads (not shown) that are connected to internal circuitry of the integrated circuit device. Each conductive pad is connected by a conventional metal bond wire 29 to a second surface 26 of a lead 24. Conventional bond wire equipment is used.
- Step 5 of Figure 1 applies an insulative and adhesive encapsulating material onto the array of the package sites in order to encapsulate each of the integrated circuit devices, the leads, and the electrical conductors of each package site.
- Step 6 of Figure 1 hardens the encapsulating material forming the package bodies and the exterior surfaces of the packages.
- Figure 6 is a cross-sectional side view of three package sites 19 of an encapsulated array 18 after Steps 5 and 6.
- the three package sites 19 are covered in a single block of encapsulant material 32.
- first surface 11 of sheet 10 and each integrated circuit device 28, die pad 20, leads 24, and bond wires 29 are covered by encapsulating material 32.
- Second surface 22 and side surfaces 23 of die pad 20, and second surface 26 and side surfaces 27 of leads 24 are covered by encapsulant material 32.
- Encapsulant material 32 does not, however, cover second surface 12 of plastic sheet 10, and plastic sheet 10 prevents encapsulant material from covering first surface 21 of die pad 20 and first surface 26 of leads 24.
- packages sites 19 are encapsulated in a single block of encapsulating material 32
- the package sites may be encapsulated individually in an alternative embodiment of the process.
- individual package sites may be encapsulated by injection or transfer molding, among other possible methods.
- Steps 5 and 6 of Figure 1 may be performed in several alternative ways.
- Peripheral side surface 30 of encapsulated array 18 is orthogonal, to illustrate a liquid encapsulation process.
- Peripheral side surface 31 is sloped to illustrate a molding process for encapsulating array 18.
- Step 5 may be performed using a liquid encapsulant.
- a first step applies a contiguous bead of a conventional hardenable viscous adhesive material onto first surface 11 of plastic sheet 10 around one of more package sites 19.
- An example bead material is HYSOL 4451 epoxy from the Dexter-Hysol Company of City of Industry, California.
- Figure 10 is a top plan view of an array 18 of three package sites 19 with a bead 33 of adhesive material around the array 18. Bead 33 is cross-hatched in Figure 10. Bead 33 encloses each package site 19. Bead 33 forms a cavity with first surface 11 of plastic sheet 10 in which the three package sites 19 and integrated circuit devices 28 are enclosed.
- bead 33 is solidified, such as by heating at 150 degrees C for one hour.
- a conventional, hardenable, adhesive, and insulative liquid encapsulating material suitable for encapsulating packages is poured within bead 33 and fills the cavity formed by bead 33 so that package sites 19, integrated circuit devices 28, leads 24, die pads 20, and bond wires 29 are covered with encapsulant material.
- An example liquid encapsulant material is HYSOL 4450 encapsulant.
- the encapsulant material is hardened, such as by heating at 150 degrees C for one hour. This embodiment of Steps 5 and 6 forms a single solid block of encapsulant material 32 above and on array 18.
- Steps 5 and 6 of Figure 1 may be accomplished using conventional plastic molding techniques and materials, such as injection molding or transfer molding.
- a first step places array 18 in a conventional two-pocket mold. The lower pocket of the mold is blanked out by a bar so that encapsulant material does not enter the lower pocket.
- insulative encapsulant material i.e., molding compound, is provided to the upper pocket of the mold.
- Encapsulant material 32 is molded onto package sites 19 of array 18 above and on first surface 11 of plastic sheet 10.
- Integrated circuit devices 28, leads 24, die pads 20, and bond wires 29 are covered with encapsulant material 32.
- encapsulant material 32 is hardened in a conventional manner.
- example encapsulation materials include styrene, liquid crystal polymer, or nylon 66.
- transfer molding techniques are used, SUMITOMO 8100 molding material from the Sumitomo Company of Japan or Plaskon SMT B1RC molding material may be used.
- Step 7 of Figure 1 removes plastic sheet 10 from encapsulated array 18.
- An example method of performing Step 7 is to dissolve plastic sheet 10 in a solvent, such as acetone.
- the material of plastic sheet 10 should be chosen in view of its ability to be dissolved, and the solvent must be compatible with the encapsulant material 32.
- Another method of performing Step 7 is simply to use a solvent to dissolve the adhesive that was used to attach plastic sheet 10 to metal sheet 13 without dissolving plastic sheet 10. Plastic sheet 10 may then fall away from the encapsulated array or may be peeled away.
- Still another method of performing step 7, where plastic sheet 10 is polyimide, for example, is to soak array 18 in heated water (e.g., 80 degrees C water) for about an hour, then apply ultra violent light to sheet 10 until sheet 10 falls off or may easily be peeled off array 18. For example, ultraviolet light may be applied for about one minute.
- heated water e.g. 80 degrees C water
- Step 7 Another method of performing Step 7 is to heat plastic sheet 10 and then peel plastic sheet 10 from array 18.
- the heating could be to a temperature of 80 degrees C. If Step 5 is done by molding, then plastic sheet 10 could be removed while array 18 is in the mold or after array 18 is removed from the mold.
- Step 8 is an optional step that applies conventional solder balls to the exposed surfaces of the leads of encapsulated package sites 19.
- Figure 7 is a cross-sectional side view of array 18 of packages sites 19 after removal of plastic sheet 10 and attachment of solder balls 34 to the exposed first surfaces 25 of leads 24. Solder balls 34 are used for connection of the package to external circuitry.
- Step 8 may be omitted.
- first surface 25 of leads 24 serve as connectors to external circuitry, as in a leadless chip carrier package style.
- Step 9 of Figure 1 separates individual packages from the encapsulated array.
- Step 9 may be performed, for example, by cutting encapsulated array with a saw. Disposable material, such as bead 33 is cut away.
- Figure 8 is a cross-sectional side view of array 18 of Figure 7 after encapsulant material 32 is cut with a saw.
- Encapsulated array 18 is inverted and orthogonal cuts 35 in encapsulant material 32 are made.
- an adhesive plastic film 36 is applied to the top surface of encapsulated array 18 to immobilize the packages during the cutting step. Such films are used, for example, in conventional wafer cutting processes.
- Adhesive plastic film 36 is placed on the top surface of encapsulated array 18 before Step 7, Step 8, or Step 9.
- the cutting step segments encapsulant material 32 without fully severing plastic film 36.
- the cuts segment the encapsulant material without fully severing the tape.
- Figure 9 shows a completed package 37 having orthogonal side surfaces 38 at the periphery of package 37.
- FIG. 9 Another possible technique for singulating packages 37 (Fig. 9) from the encapsulated array 18 of package sites 19 (Fig. 7) does not require the use of a plastic film 36 (Fig. 8).
- the encapsulated array 18 is placed on a vacuum chuck formed, for example, of fritted metal.
- the chuck has criss-crossing grooves in the X and Y directions.
- the grooves are, for example, 0.05 to 0.08 mm in depth.
- the grooves correspond to where cuts are to be made between package sites 19 of the encapsulated array 18.
- a saw cuts along the grooves without contacting the chuck to singulate the packages.
- a water spray may be used for cooling and/or removal of waste.
- the packages are then removed from the chuck.
- plastic sheet 10 may be a continuous tape on a reel.
- the process of Figure 1 can be a reel to reel process.
- Step 1 of Figure 1 may include unrolling a plastic tape from a first reel, attaching a metal tape to an adhesive surface of the unrolled plastic tape, and then rolling up the joined plastic and metal tapes on a second reel.
- Step 2 may include unrolling the second reel of joined plastic and metal tapes, patterning a selected length of the metal to form package sites 19, and then rolling the etched length of package sites 19 onto a third reel. The second reel is advanced until the entire length of the second reel is etched to form a third reel of package sites 19.
- the third reel of package sites 19 is then unrolled, and segments of selected length, for example, from four to 200 package sites 19, are subjected to die attach, bond wire attach, and encapsulation (i.e., Steps 3-6 of Figure 1).
- Step 6 encapsulant hardening
- the selected length of encapsulated package sites 18 can be cut from the third reel, and processed as an individual encapsulated array 18 through the remaining steps of Figure 1.
- Step 5 of Figure 1 is performed by molding
- a mold having multiple two-pocket cavities can be used which molds individual package housings on a selected number of package sites 19.
- the lower pocket is blocked with a bar so encapsulant material only is applied above first surface 11 of plastic sheet 10.
- This is shown in Figure 12, where three package sites 19 are molded into individual package bodies 39. Molded webbing 40 is between the individual package.
- Step 6 the reel of molded package sites is advanced onto a fourth reel, and a second segment of packages is molded.
- the third reel of package sites is then advanced until all of the package sites are subjected to die attach, wire bond, and molding.
- the fourth roll of molded packages is unrolled, and Steps 7-9 of Figure 1 are performed as discussed above.
- side surfaces 23 of die pad 20 and side surfaces 27 of leads 24 are shown as having an orthogonal orientation.
- side surfaces 23 and 27 are formed with a reentrant portion for enhancing the connection between encapsulant material 32 and die pad 20 and leads 24.
- Such reentrant surfaces may be formed, for example, by a controlled chemical etch process, or by a standard chemical etch process followed by coining of the patterned metal sheet.
- Figure 11 shows an enlarged cross-sectional side view of a completed package 50 having alternative side surfaces 23 of a die pad 20 and side surfaces 27 of leads.
- the reentrant portions of side surfaces 23 and 27 are formed during Step 2 of Figure 1, when patterned array 18 is formed from plated metal sheet 13.
- Package 50 is the same as package 37 of Figure 9, except for the side surfaces of the die pad and leads.
- the reentrant portion of side surfaces 23 of die pad 20 and side surfaces 27 of leads 24 includes a central depression 42.
- side surfaces 23 and 27 have a roughly-textured surface that includes numerous aspirates on the reentrant surface.
- Encapsulant material flows into central depression 42 and into the areas of the aspirates during Step 5 of Figure 1. The reentrant portion and the aspirates engage encapsulant material 32 and lock die pad 20 and leads 24 to encapsulant material 32.
- reentrant side surfaces 23 of die pad 20 and side surfaces 27 of leads 24 can be formed during step 2 by etching metal sheet 13 with a conventional liquid etchant using a controlled etch process.
- the etch process is continued beyond the time that would be required to form orthogonal side surfaces for the die pad and leads. This is usually accomplished by using an oversized mask on upper second surface 15 of metal sheet 13 ( Figure 2) and using a slight overetch.
- the size and shape of depression 42 of Figure 11 is controlled by the amount of over-etching.
- Figure 13 shows a second alternative package 60 that may be formed by the method of Figure 1.
- Package 60 is identical to package 50 of Figure 11, except that the side surfaces of die pad 20 and leads 24 have a different reentrant profile.
- side surfaces 23 of die pad 20 have a projecting lip 61 adjacent to upper second surface 22. Lip 61 includes a roughly textured surface with aspirates.
- Side surface 23 of die pad 20 has a reentrant orthogonal portion 62 beneath lip 61, i.e., between lip 61 and lower first surface 21.
- Leads 24 also have a similar projecting lip 64 with aspirates.
- Side surfaces 27 of leads 24 also have a reentrant orthogonal portion 65 beneath lip 64, i.e., between lip 64 and lower first surface 25.
- encapsulant material 32 covers lips 61 and 64, and flows beneath lips 61 and 64 to contact reentrant orthogonal portions 62 and 65.
- the encapsulant material beneath lips 61 and 64 lock die pad 20 and leads 24 to encapsulant material 32.
- the reentrant side surfaces of die pad 20 and leads 24 of Figure 13 are formed during Step 2 of the process of Figure 1.
- a first step provides a patterned metal sheet having orthogonal side surfaces on die pad 20 and leads 24, as would be produced in a standard chemical etching process.
- a second step coins upper second surface 22 of die pad 20 and upper second surface 26 of leads 24. Coining involves applying a high pressure impact to upper second surfaces 22 and 26. This high pressure impact deforms the side surfaces of die pad 20 and leads 24 to form lips 61 and 64 ( Figure 13).
- FIG. 15 is a flow chart of another method 70 within the present invention of forming a package.
- Step 1 of method 70 provides a plastic sheet 10.
- Step 2 applies a metal layer 16 to a first surface 11 of plastic sheet 10.
- Metal layer 16 may be applied in a variety of ways.
- metal layer 16 may be applied by sputtering or chemical vapor deposition.
- metal layer 16 may be a metal sheet that is attached to first surface 11 using an adhesive present either on the metal sheet or on first surface 11.
- metal layer 16 is copper plated with nickel, although other types of metal may be used.
- Step 3 applies a photoresist pattern to the exposed second surface 15 of metal layer 16.
- the photoresist pattern is used to define a plurality of package sites 19, each including a die pad 20 and adjacent leads 24.
- Step 4 applies a second metal layer 17 on the exposed areas of metal layer 16.
- second metal layer 17 is gold and that the gold is plated on the nickel layer, which in turn is plated on the copper layer.
- the photoresist pattern is stripped away, leaving gold areas where die pads 20 and leads 24 will be formed, as shown in Fig. 16.
- Step 5 selectively etches the first metal layer 16 using second metal layer 17 as an etching mask.
- the chemical selected as the etchant typically an acid, must etch copper and nickel without etching or substantially etching the gold.
- An array of package sites 19 is thus formed, as shown in Fig. 3.
- Figure 17 is a cross-sectional side view of a die pad 20 and two leads 24 of a package site 19 produced by Step 5 of method 70 using the exemplary metals discussed above.
- Die pad 20 and leads 24 include a first layer of copper 14, an intermediate layer of nickel 14a and a top layer of gold 17.
- the side surfaces 23 and 27 of die pad 20 and leads 24, respectively, have reentrant portions in copper layer 14 and nickel layer 14a. The reentrant portions of side surfaces 23 and 27 fill with encapsulant during a subsequent encapsulation step, and thereby lock die pad 20 and leads 24 to the encapsulant.
- Steps 6-12 of method 70 are similar to Steps 3-9 of method 5 of Fig. 1, and thus do not require further discussion. As with method 5, method 70 may be performed as a reel-to-reel process.
- Figure 18 is a flow chart of an alternative method 80 within the present invention of making a package.
- Step 1 of method 80 provides a plastic sheet 10, which may be, for example, polyimide.
- plastic sheet 10 may be polyester or polyethermide.
- Plastic sheet 10 may have an adhesive layer on first surface 11 thereof, but an adhesive layer is not necessary.
- Step 2 applies an electrically conductive, metal-containing first media 81 onto first surface 11 of plastic sheet 10 in a pattern using a silk screening method.
- the pattern defines an array 18 of package sites 19, each having a die pad 20 and leads 24.
- Step 3 applies an optional second electrically conductive, metal-containing second media 82 onto first media 81 using a silk screening method.
- second media 82 is applied so as to overhang all of the peripheral edges of media 81 so as to form die pads 20 and leads 24 with side surfaces 23 and 27 having a reentrant profile that can lock die pads 20 and leads 24 to the encapsulant.
- the silk screening may be performed through a 1000 mesh stainless steel screen.
- First media 81 and second media 82 of Fig. 19 may be low temperature, adhesive, metal-containing materials.
- epoxy-based media or ink-based media may be used.
- the metals contained therein may vary.
- first media 81 and second media 82 may contain copper and silver, respectively.
- Gold or aluminum containing media also may be used.
- a low temperature media is used to avoid melting plastic sheet 10.
- Aluminum bond wires may be used.
- a stencil method is used instead of a silk screening method to form package sites 19.
- Steps 4-10 of method 80 are similar to the steps 3-9 of method 5 of Fig. 1, and thus do not require detailed discussion.
- plastic sheet 10 may be removed from array 18 by any of the methods discussed above.
- plastic sheet 10 may be heated and peeled from array 17.
- array 18 may be placed in a solvent that either dissolves an adhesive connection between array 18 and plastic sheet 10, or dissolves plastic sheet 10 itself.
- method 80 of Fig. 18 may be performed as a reel-to-reel process.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
- This application is a continuation-in-part of U.S. patent application No. 09/383,022 (attorney docket M-5311 US), which is entitled "Method of Forming an Integrated Circuit Package Using Plastic Tape as a Base" and was filed on August 25, 1999.
- A problem with conventional plastic packages is that their internal leadframes limit reduction of the size of the packages. Practitioners have attempted to reduce the size of packages by eliminating internal leadframes, as is shown in U.S. Patent No. 4,530,142 to Roche et al.
- Roche et al. begins with a metal temporary substrate. A layer of a low melting-point alloy is applied onto to the metal temporary substrate. Next a plurality of metal die pads and leads are formed on the low-melting point alloy layer. An integrated circuit device is placed on each of the die pads and connected to the leads surrounding the respective die pad. The integrated circuit devices are then encapsulated in a single block of encapsulant material. Individual packages are then cut from the block of hardened encapsulant.
- The methods and package of Roche et al. have foreseeable disadvantages. For example, the use of the metal temporary substrate and low-melting point alloy layer increase costs and manufacturing difficulty. Further, the packages are believed to be unreliable because the contacts could easily be pulled from the encapsulant material.
- A package marketed by Toshiba Corporation of Japan under the name "BCC" is believed to be made as follows. A copper sheet is partially etched through in certain locations, forming pockets isolated by unetched copper. A central pocket is surrounded by several smaller satellite pockets. The copper sheet is then masked, leaving the pockets exposed. Next, the pockets are plated with layers of gold, nickel, and gold. An integrated circuit device is placed in the central pocket. (In some embodiments, there is no central pocket, so the device is simply placed on the copper sheet.) Bond wires are connected between the device and the satellite pockets. Next, the device and bond wires are encapsulated. Finally, the remainder of the copper sheet is etched away by acid, forming a completed package. Once the copper is removed, the metal plated into the satellite pockets forms the leads of the package, and the metal plated into the central depression (if any) is the die pad.
- This process is believed to have several disadvantages. First, the use of acid to dissolve the remainder of the copper plate after encapsulation creates a significant possibility of contamination, since such acids are generally regarded as dirty. Second, the package is subject to failure, because the leads are attached to the package only by the bond wire and by the adhesiveness of the encapsulant to the inner surface of the plated pocket. Thus, the leads could easily be detached from the bond wire and package body. Third, epoxy encapsulant material sometimes does not adhere well to gold.
- Accordingly, there is a need for a small and reliable package that is easier and less expensive to manufacture than prior art packages.
- The present invention includes a method of manufacturing a package for housing an integrated circuit device. In one exemplary embodiment,
Step 1 provides a plastic sheet having an adhesive first surface. The plastic sheet may be plastic tape.Step 2 attaches a metal sheet onto the first surface of the plastic sheet, and then forms an array of package sites by selectively removing portions of the metal sheet. Each package site includes a die pad and a plurality of satellite leads around the die pad.Step 3 attaches an integrated circuit device to each of the die pads.Step 4 connects a conductor, such a bond wire, between each of a plurality of conductive pads on the integrated circuit device and one of the leads of the respective package site.Step 5 applies an encapsulating material onto the first surface of the plastic sheets, integrated circuit devices, the leads, and the electrical conductors of each package site.Step 6 hardens the encapsulating material.Step 7 removes the plastic sheet.Optional Step 8 applies solder balls to the exposed surfaces of the leads of the package sites. Finally,Step 9 separates individual packages from the encapsulated array. An alternative embodiment in an LCC style package requires no solder balls. - An embodiment encompassed within the present invention includes forming a reentrant portion (or reentrant portions) and aspirates on the side surfaces of the die pads and leads of the package sites. During the encapsulation step, the encapsulant material flows into the reentrant portions and aspirates. The reentrant portions and aspirates engage the encapsulant material and lock the die pad and leads to the encapsulant material of the package.
- The present invention overcomes the disadvantages of the prior art by, among other things, the use of an inexpensive plastic sheet as a base for forming the packages, and by the formation of encapsulant locking features on the side surfaces of the die pad and leads. These and other advantages will become clear through the following detailed description.
- Figure 1 is a flow chart of a method of forming a package for an integrated circuit device.
- Figure 2 is cross-sectional side view of a plated metal sheet on a plastic sheet.
- Figure 3 is a cross-sectional side view of an array of package sites each including a die pad and leads.
- Figure 4 is a top plan view of the array of package sites shown in Figure 3.
- Figure 5 is a cross-sectional side view of these integrated circuit devices placed on and wire-bonded to leads of respective package sites.
- Figure 6 is a cross-sectional side view of an array of package sites after encapsulation by either liquid encapsulation or molding techniques.
- Figure 7 is a cross-sectional side view of the array of Figure 5 after removal of the plastic sheet and attachment of solder balls to the leads.
- Figure 8 is a cross-sectional side view an inverted array of packages after the encapsulant material is cut with a saw.
- Figure 9 is a cross-sectional side view of a completed package.
- Figure 10 is a top plan view of an array of package sites with a bead of adhesive material around the array.
- Figure 11 is a cross-sectional side view of a completed package showing a first alternative side surface of a die pad and leads.
- Figure 12 is a cross-sectional side view of an array of individually molded package bodies.
- Figure 13 is a cross-sectional side view of a completed package showing a second alternative side surface of a die pad and leads.
- Fig. 14 is a plan view of a package site having two rows of staggered leads around the die pad.
- Fig. 15 is a flow chart of an alternative method of making a package.
- Fig. 16 is a cross-sectional side view of a plastic sheet having a first metal layer and a second metal layer thereon that serves as a mask for etching the first metal layer.
- Fig. 17 is a cross-sectional side view of the die pad and leads of a package site formed by the method of Fig. 14.
- Fig. 18 is a flow chart of an alternative method of forming a package.
- Fig. 19 is a cross-sectional side view of a plastic sheet with two layers of an electrically-conductive media thereon, where the layers define an array of package sites.
- Figure 1 is a flow chart of an
exemplary method 5 in accordance with the present invention for forming a package for an integrated circuit device. An example of a completedpackage 37 that may be formed bymethod 5 of Figure 1 is shown in Figure 9. - As will become clear from the discussion the assembly method of Figure 1,
package 37 of Figure 9 includes a semiconductor integratedcircuit device 28 mounted on ametal die pad 20. A plurality of metal leads 24 are adjacent to diepad 20 and are connected bybond wires 29 to conductive pads (not shown) ondevice 28.Encapsulant material 32 forms the package body, and coversdevice 28,bond wires 29, and the upper and side surfaces ofdie pad 20 and leads 24. The lower surface ofdie pad 20 is exposed.Solder balls 34 are attached to the lower surface ofleads 24, although solder balls are optional. - Again, Figure 1 provides a
method 5 of making a package likepackage 37 of Figure 9. Referring to Figures 1 and 2,Step 1 of Figure 1 provides a plastic sheet formed of a plastic material.Plastic sheet 10 has afirst surface 11 and an oppositesecond surface 12. An adhesive is present on or applied tofirst surface 11 ofplastic sheet 10. -
Plastic sheet 10 may be a segment having a size of, for example, 5 cm by 20 cm, and a thickness of about 25 to 75 microns. The size and thickness ofplastic sheet 10 can vary. Alternatively,plastic sheet 10 may be a plastic tape that is on a roll. As described below, the process of Figure 1 may be performed as a reel to reel process. -
Plastic sheet 10 is formed of a conventional plastic material such as polyvinyl chloride, polyvinyl alcohol acetate, polypropylene acetate, vinyl, polyethylene, mylar, or polyimide. An example brand of plastic tape is KAPTON polyimide tape from the Dupont Company. -
Step 2 of Figure 1 provides a patterned metal sheet on the first surface of the plastic sheet. Figures 2 and 3 show one embodiment of a method of performingStep 2 of Figure 1. - Referring to Figure 2, a
metal sheet 13 is first attached to the adhesivefirst surface 11 ofplastic sheet 10.Metal sheet 13 of Figure 2 has afirst surface 14 attached tofirst surface 11 ofplastic sheet 10, and an oppositesecond surface 15. In an alternative embodiment, an adhesive material is applied tofirst surface 14 ofmetal sheet 13 rather than tofirst surface 11 ofplastic sheet 10. - In Figure 2,
metal sheet 13 consists of an underlyingfirst metal layer 16 onfirst surface 11 ofplastic sheet 10, and asecond metal layer 17 that is plated onto a top surface offirst metal layer 16 oppositefirst surface 11 ofplastic sheet 10.First metal layer 16 ofmetal sheet 13 may be formed, for example, of copper, a copper alloy, orAlloy 42. Platedmetal layer 17 may be nickel gold, silver, platinum, palladium, or another noble metal. Using nickel/gold plating or silver plating may facilitate bond wire connections. Where copper is used formetal sheet 13, without plating, copper bond wires may be used. Although not shown in Figure 2,first surface 14 ofmetal sheet 13 also may be plated.Metal sheet 13 may have a thickness of, for example, 100 to 250 microns. - Next,
metal sheet 13 is etched to form an array of package sites. For example, such etching is performed by chemical etching using a patterned photoresist mask. In such a process, a layer of photoresist is applied ontosecond surface 15 ofmetal sheet 13. Next, the photoresist is exposed to light through a patterned reticle or the like, and is subsequently developed to form a mask. Chemicals are sprayed or otherwise applied to the masked metal strip, and exposed portions of metal are etched away, leaving the desired pattern. Typically, acids are used to etch the metal. Obviously,plastic film 10 must not be substantially attacked by the chemical used to etchmetal sheet 13. A cleaning step may be necessary to remove residue or other undesirable materials after Step 2 (or any of the other steps) of Figure 1. - Figure 3 is a cross-sectional side view of an
array 18 of threeidentical package sites 19 formed by the above-described chemical etching ofmetal sheet 13. Figure 4 is a top plan view ofarray 18 of Figure 3. - Referring to Figures 3 and 4, each
package site 19 includes ametal die pad 20 and metal leads 24.Die pad 20 and leads 24 are formed frommetal layer 16 andmetal layer 17 ofmetal sheet 13 of Figure 2. Figure 4 shows that each diepad 20 has a rectangular perimeter and is surrounded on each of its four sides by four leads 24. Leads 24 also have a rectangular perimeter. - The perimeter shapes of
die pad 20 and leads 24 can vary. For example, leads 24 can have a rectangular or circular perimeter. Also, the number and positioning of the leads can vary. For example, 64 or 128 leads may be selected. As another example, instead of having single rows ofleads 24 around diepad 20, two or more staggered rows ofleads 24 may be provided adjacent to two or all four sides ofdie pad 20. Fig. 14 is a plan view of an exemplary embodiment of apackage site 19 where two staggered rows ofleads 24 surround diepad 20. - In Figure 3, each die
pad 20 has afirst surface 21 attached tofirst surface 11 ofplastic sheet 10, an oppositesecond surface 22, and side surfaces 23 at the periphery ofdie pad 20 betweenfirst surface 21 andsecond surface 22. Eachlead 24 has afirst surface 25 attached tofirst surface 11 ofplastic sheet 10, an oppositesecond surface 26, and side surfaces 27 at the periphery oflead 24 betweenfirst surface 25 andsecond surface 26. -
Step 3 of Figure 1 places an integrated circuit device onto each of the die pads.Step 4 of Figure 1 connects a conductor, such a bond wire, between each of a plurality of conductive pads on each of the integrated circuit device and one of the leads of that integrated circuit device's respective package site. - Figure 5 is a cross-sectional side view of three
integrated circuit devices 28 placed onsecond surface 22 of these diepads 20. Eachintegrated circuit device 28 is placed on adie pad 20 and is adhesively attached tosecond surface 22 ofdie pad 20 using conventional die attach equipment and adhesives. - Each integrated
circuit device 28 of Figure 5 includes conductive pads (not shown) that are connected to internal circuitry of the integrated circuit device. Each conductive pad is connected by a conventionalmetal bond wire 29 to asecond surface 26 of alead 24. Conventional bond wire equipment is used. -
Step 5 of Figure 1 applies an insulative and adhesive encapsulating material onto the array of the package sites in order to encapsulate each of the integrated circuit devices, the leads, and the electrical conductors of each package site.Step 6 of Figure 1 hardens the encapsulating material forming the package bodies and the exterior surfaces of the packages. - Figure 6 is a cross-sectional side view of three
package sites 19 of an encapsulatedarray 18 afterSteps package sites 19 are covered in a single block ofencapsulant material 32. In particular,first surface 11 ofsheet 10 and eachintegrated circuit device 28, diepad 20, leads 24, andbond wires 29 are covered by encapsulatingmaterial 32.Second surface 22 and side surfaces 23 ofdie pad 20, andsecond surface 26 and side surfaces 27 ofleads 24 are covered byencapsulant material 32.Encapsulant material 32 does not, however, coversecond surface 12 ofplastic sheet 10, andplastic sheet 10 prevents encapsulant material from coveringfirst surface 21 ofdie pad 20 andfirst surface 26 of leads 24. - Although in this embodiment three
packages sites 19 are encapsulated in a single block of encapsulatingmaterial 32, the package sites may be encapsulated individually in an alternative embodiment of the process. In such an alternative embodiment, individual package sites may be encapsulated by injection or transfer molding, among other possible methods. - Steps 5 and 6 of Figure 1 may be performed in several alternative ways.
Peripheral side surface 30 of encapsulatedarray 18 is orthogonal, to illustrate a liquid encapsulation process.Peripheral side surface 31 is sloped to illustrate a molding process for encapsulatingarray 18. - For example,
Step 5 may be performed using a liquid encapsulant. In such a method, a first step applies a contiguous bead of a conventional hardenable viscous adhesive material ontofirst surface 11 ofplastic sheet 10 around one ofmore package sites 19. An example bead material is HYSOL 4451 epoxy from the Dexter-Hysol Company of City of Industry, California. Figure 10 is a top plan view of anarray 18 of threepackage sites 19 with abead 33 of adhesive material around thearray 18.Bead 33 is cross-hatched in Figure 10.Bead 33 encloses eachpackage site 19.Bead 33 forms a cavity withfirst surface 11 ofplastic sheet 10 in which the threepackage sites 19 andintegrated circuit devices 28 are enclosed. Next,bead 33 is solidified, such as by heating at 150 degrees C for one hour. Next, a conventional, hardenable, adhesive, and insulative liquid encapsulating material suitable for encapsulating packages is poured withinbead 33 and fills the cavity formed bybead 33 so thatpackage sites 19, integratedcircuit devices 28, leads 24, diepads 20, andbond wires 29 are covered with encapsulant material. An example liquid encapsulant material is HYSOL 4450 encapsulant. As a final step, the encapsulant material is hardened, such as by heating at 150 degrees C for one hour. This embodiment ofSteps encapsulant material 32 above and onarray 18. - Alternatively, Steps 5 and 6 of Figure 1 may be accomplished using conventional plastic molding techniques and materials, such as injection molding or transfer molding. In such a method, a first step places
array 18 in a conventional two-pocket mold. The lower pocket of the mold is blanked out by a bar so that encapsulant material does not enter the lower pocket. Next, insulative encapsulant material, i.e., molding compound, is provided to the upper pocket of the mold.Encapsulant material 32 is molded ontopackage sites 19 ofarray 18 above and onfirst surface 11 ofplastic sheet 10.Integrated circuit devices 28, leads 24, diepads 20, andbond wires 29 are covered withencapsulant material 32. Next,encapsulant material 32 is hardened in a conventional manner. Where injection molding techniques are used, example encapsulation materials include styrene, liquid crystal polymer, or nylon 66. Where transfer molding techniques are used, SUMITOMO 8100 molding material from the Sumitomo Company of Japan or Plaskon SMT B1RC molding material may be used. -
Step 7 of Figure 1 removesplastic sheet 10 from encapsulatedarray 18. An example method of performingStep 7 is to dissolveplastic sheet 10 in a solvent, such as acetone. The material ofplastic sheet 10 should be chosen in view of its ability to be dissolved, and the solvent must be compatible with theencapsulant material 32. Another method of performingStep 7 is simply to use a solvent to dissolve the adhesive that was used to attachplastic sheet 10 tometal sheet 13 without dissolvingplastic sheet 10.Plastic sheet 10 may then fall away from the encapsulated array or may be peeled away. Still another method of performingstep 7, whereplastic sheet 10 is polyimide, for example, is to soakarray 18 in heated water (e.g., 80 degrees C water) for about an hour, then apply ultra violent light tosheet 10 untilsheet 10 falls off or may easily be peeled offarray 18. For example, ultraviolet light may be applied for about one minute. - Another method of performing
Step 7 is to heatplastic sheet 10 and then peelplastic sheet 10 fromarray 18. For example, the heating could be to a temperature of 80 degrees C. IfStep 5 is done by molding, thenplastic sheet 10 could be removed whilearray 18 is in the mold or afterarray 18 is removed from the mold. -
Step 8 is an optional step that applies conventional solder balls to the exposed surfaces of the leads of encapsulatedpackage sites 19. Figure 7 is a cross-sectional side view ofarray 18 ofpackages sites 19 after removal ofplastic sheet 10 and attachment ofsolder balls 34 to the exposed first surfaces 25 of leads 24.Solder balls 34 are used for connection of the package to external circuitry. - Alternatively,
Step 8 may be omitted. In such a case,first surface 25 ofleads 24 serve as connectors to external circuitry, as in a leadless chip carrier package style. - Finally,
Step 9 of Figure 1 separates individual packages from the encapsulated array.Step 9 may be performed, for example, by cutting encapsulated array with a saw. Disposable material, such asbead 33 is cut away. - Figure 8 is a cross-sectional side view of
array 18 of Figure 7 afterencapsulant material 32 is cut with a saw. Encapsulatedarray 18 is inverted andorthogonal cuts 35 inencapsulant material 32 are made. Prior to cutting, anadhesive plastic film 36 is applied to the top surface of encapsulatedarray 18 to immobilize the packages during the cutting step. Such films are used, for example, in conventional wafer cutting processes. Adhesiveplastic film 36 is placed on the top surface of encapsulatedarray 18 beforeStep 7,Step 8, orStep 9. The cutting step segments encapsulantmaterial 32 without fully severingplastic film 36. The cuts segment the encapsulant material without fully severing the tape. Whenadhesive film 36 is removed from the package tops, the formation ofindividual packages 37 is completed. Figure 9 shows a completedpackage 37 having orthogonal side surfaces 38 at the periphery ofpackage 37. - Another possible technique for singulating packages 37 (Fig. 9) from the encapsulated
array 18 of package sites 19 (Fig. 7) does not require the use of a plastic film 36 (Fig. 8). In this alternative method, the encapsulatedarray 18 is placed on a vacuum chuck formed, for example, of fritted metal. The chuck has criss-crossing grooves in the X and Y directions. The grooves are, for example, 0.05 to 0.08 mm in depth. The grooves correspond to where cuts are to be made betweenpackage sites 19 of the encapsulatedarray 18. A saw cuts along the grooves without contacting the chuck to singulate the packages. A water spray may be used for cooling and/or removal of waste. The packages are then removed from the chuck. - As mentioned above,
plastic sheet 10 may be a continuous tape on a reel. Whereplastic sheet 10 is a continuous tape on a reel, then the process of Figure 1 can be a reel to reel process. For example,Step 1 of Figure 1 may include unrolling a plastic tape from a first reel, attaching a metal tape to an adhesive surface of the unrolled plastic tape, and then rolling up the joined plastic and metal tapes on a second reel.Step 2 may include unrolling the second reel of joined plastic and metal tapes, patterning a selected length of the metal to formpackage sites 19, and then rolling the etched length ofpackage sites 19 onto a third reel. The second reel is advanced until the entire length of the second reel is etched to form a third reel ofpackage sites 19. The third reel ofpackage sites 19 is then unrolled, and segments of selected length, for example, from four to 200package sites 19, are subjected to die attach, bond wire attach, and encapsulation (i.e., Steps 3-6 of Figure 1). After Step 6 (encapsulant hardening), the selected length of encapsulatedpackage sites 18 can be cut from the third reel, and processed as an individual encapsulatedarray 18 through the remaining steps of Figure 1. - Alternatively, if, for example,
Step 5 of Figure 1 is performed by molding, then a mold having multiple two-pocket cavities can be used which molds individual package housings on a selected number ofpackage sites 19. The lower pocket is blocked with a bar so encapsulant material only is applied abovefirst surface 11 ofplastic sheet 10. This is shown in Figure 12, where threepackage sites 19 are molded intoindividual package bodies 39. Moldedwebbing 40 is between the individual package. In such a process, afterStep 6, the reel of molded package sites is advanced onto a fourth reel, and a second segment of packages is molded. The third reel of package sites is then advanced until all of the package sites are subjected to die attach, wire bond, and molding. Next, the fourth roll of molded packages is unrolled, and Steps 7-9 of Figure 1 are performed as discussed above. - In
package 37 of Figure 9, side surfaces 23 ofdie pad 20 and side surfaces 27 ofleads 24 are shown as having an orthogonal orientation. Alternatively, side surfaces 23 and 27 are formed with a reentrant portion for enhancing the connection betweenencapsulant material 32 and diepad 20 and leads 24. Such reentrant surfaces may be formed, for example, by a controlled chemical etch process, or by a standard chemical etch process followed by coining of the patterned metal sheet. - Figure 11 shows an enlarged cross-sectional side view of a completed
package 50 having alternative side surfaces 23 of adie pad 20 and side surfaces 27 of leads. The reentrant portions of side surfaces 23 and 27 are formed duringStep 2 of Figure 1, when patternedarray 18 is formed from platedmetal sheet 13.Package 50 is the same aspackage 37 of Figure 9, except for the side surfaces of the die pad and leads. - In Figure 11, the reentrant portion of side surfaces 23 of
die pad 20 and side surfaces 27 ofleads 24 includes acentral depression 42. In addition, side surfaces 23 and 27 have a roughly-textured surface that includes numerous aspirates on the reentrant surface. Encapsulant material flows intocentral depression 42 and into the areas of the aspirates duringStep 5 of Figure 1. The reentrant portion and the aspirates engageencapsulant material 32 and lock diepad 20 and leads 24 toencapsulant material 32. - Referring to Figure 11, reentrant side surfaces 23 of
die pad 20 and side surfaces 27 ofleads 24 can be formed duringstep 2 by etchingmetal sheet 13 with a conventional liquid etchant using a controlled etch process. The etch process is continued beyond the time that would be required to form orthogonal side surfaces for the die pad and leads. This is usually accomplished by using an oversized mask on uppersecond surface 15 of metal sheet 13 (Figure 2) and using a slight overetch. The size and shape ofdepression 42 of Figure 11 is controlled by the amount of over-etching. - Figure 13 shows a second
alternative package 60 that may be formed by the method of Figure 1.Package 60 is identical to package 50 of Figure 11, except that the side surfaces ofdie pad 20 and leads 24 have a different reentrant profile. Referring to Figure 13, side surfaces 23 ofdie pad 20 have a projectinglip 61 adjacent to uppersecond surface 22.Lip 61 includes a roughly textured surface with aspirates.Side surface 23 ofdie pad 20 has a reentrant orthogonal portion 62 beneathlip 61, i.e., betweenlip 61 and lowerfirst surface 21. Leads 24 also have a similar projecting lip 64 with aspirates. Side surfaces 27 ofleads 24 also have a reentrant orthogonal portion 65 beneath lip 64, i.e., between lip 64 and lowerfirst surface 25. DuringStep 5 of the above described process,encapsulant material 32covers lips 61 and 64, and flows beneathlips 61 and 64 to contact reentrant orthogonal portions 62 and 65. The encapsulant material beneathlips 61 and 64 lock diepad 20 and leads 24 toencapsulant material 32. - The reentrant side surfaces of
die pad 20 and leads 24 of Figure 13 are formed duringStep 2 of the process of Figure 1. In particular, a first step provides a patterned metal sheet having orthogonal side surfaces ondie pad 20 and leads 24, as would be produced in a standard chemical etching process. A second step coins uppersecond surface 22 ofdie pad 20 and uppersecond surface 26 of leads 24. Coining involves applying a high pressure impact to uppersecond surfaces die pad 20 and leads 24 to formlips 61 and 64 (Figure 13). - Fig. 15 is a flow chart of another
method 70 within the present invention of forming a package. Referring to Fig. 16,Step 1 ofmethod 70 provides aplastic sheet 10.Step 2 applies ametal layer 16 to afirst surface 11 ofplastic sheet 10.Metal layer 16 may be applied in a variety of ways. For example,metal layer 16 may be applied by sputtering or chemical vapor deposition. Alternatively,metal layer 16 may be a metal sheet that is attached tofirst surface 11 using an adhesive present either on the metal sheet or onfirst surface 11. For the purpose of example, assume thatmetal layer 16 is copper plated with nickel, although other types of metal may be used. -
Step 3 applies a photoresist pattern to the exposedsecond surface 15 ofmetal layer 16. The photoresist pattern is used to define a plurality ofpackage sites 19, each including adie pad 20 and adjacent leads 24.Step 4 applies asecond metal layer 17 on the exposed areas ofmetal layer 16. As an example, assume thatsecond metal layer 17 is gold and that the gold is plated on the nickel layer, which in turn is plated on the copper layer. Next, the photoresist pattern is stripped away, leaving gold areas where diepads 20 and leads 24 will be formed, as shown in Fig. 16. -
Step 5 selectively etches thefirst metal layer 16 usingsecond metal layer 17 as an etching mask. In this example, the chemical selected as the etchant, typically an acid, must etch copper and nickel without etching or substantially etching the gold. An array ofpackage sites 19 is thus formed, as shown in Fig. 3. - Figure 17 is a cross-sectional side view of a
die pad 20 and twoleads 24 of apackage site 19 produced byStep 5 ofmethod 70 using the exemplary metals discussed above.Die pad 20 and leads 24 include a first layer ofcopper 14, an intermediate layer of nickel 14a and a top layer ofgold 17. The side surfaces 23 and 27 ofdie pad 20 and leads 24, respectively, have reentrant portions incopper layer 14 and nickel layer 14a. The reentrant portions of side surfaces 23 and 27 fill with encapsulant during a subsequent encapsulation step, and thereby lockdie pad 20 and leads 24 to the encapsulant. - Steps 6-12 of
method 70 are similar to Steps 3-9 ofmethod 5 of Fig. 1, and thus do not require further discussion. As withmethod 5,method 70 may be performed as a reel-to-reel process. - Figure 18 is a flow chart of an
alternative method 80 within the present invention of making a package.Step 1 ofmethod 80 provides aplastic sheet 10, which may be, for example, polyimide. Alternatively,plastic sheet 10 may be polyester or polyethermide.Plastic sheet 10 may have an adhesive layer onfirst surface 11 thereof, but an adhesive layer is not necessary. Referring to Fig. 19,Step 2 applies an electrically conductive, metal-containingfirst media 81 ontofirst surface 11 ofplastic sheet 10 in a pattern using a silk screening method. The pattern defines anarray 18 ofpackage sites 19, each having adie pad 20 and leads 24.Step 3 applies an optional second electrically conductive, metal-containingsecond media 82 ontofirst media 81 using a silk screening method. In this embodiment,second media 82 is applied so as to overhang all of the peripheral edges ofmedia 81 so as to form diepads 20 and leads 24 withside surfaces pads 20 and leads 24 to the encapsulant. The silk screening may be performed through a 1000 mesh stainless steel screen. -
First media 81 andsecond media 82 of Fig. 19 may be low temperature, adhesive, metal-containing materials. For example, epoxy-based media or ink-based media may be used. The metals contained therein may vary. For example,first media 81 andsecond media 82 may contain copper and silver, respectively. Gold or aluminum containing media also may be used. A low temperature media is used to avoid meltingplastic sheet 10. Aluminum bond wires may be used. - In an alternative embodiment, a stencil method is used instead of a silk screening method to form
package sites 19. - Steps 4-10 of
method 80 are similar to the steps 3-9 ofmethod 5 of Fig. 1, and thus do not require detailed discussion. With respect toStep 8 ofmethod 80,plastic sheet 10 may be removed fromarray 18 by any of the methods discussed above. For example,plastic sheet 10 may be heated and peeled fromarray 17. Alternatively,array 18 may be placed in a solvent that either dissolves an adhesive connection betweenarray 18 andplastic sheet 10, or dissolvesplastic sheet 10 itself. As withmethod 5 of Fig. 1,method 80 of Fig. 18 may be performed as a reel-to-reel process. - The embodiments described herein are merely examples of the present invention. Artisans will appreciate that variations are possible within the scope of the claims.
Claims (24)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/504,007 US20020100165A1 (en) | 2000-02-14 | 2000-02-14 | Method of forming an integrated circuit device package using a temporary substrate |
US09/863,359 US6586677B2 (en) | 1999-08-25 | 2001-05-22 | Plastic integrated circuit device package having exposed lead surface |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/504,007 US20020100165A1 (en) | 2000-02-14 | 2000-02-14 | Method of forming an integrated circuit device package using a temporary substrate |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/383,022 Continuation-In-Part US6247229B1 (en) | 1999-08-25 | 1999-08-25 | Method of forming an integrated circuit device package using a plastic tape as a base |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/863,359 Division US6586677B2 (en) | 1999-08-25 | 2001-05-22 | Plastic integrated circuit device package having exposed lead surface |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020100165A1 true US20020100165A1 (en) | 2002-08-01 |
Family
ID=24004474
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/504,007 Abandoned US20020100165A1 (en) | 1999-08-25 | 2000-02-14 | Method of forming an integrated circuit device package using a temporary substrate |
US09/863,359 Expired - Lifetime US6586677B2 (en) | 1999-08-25 | 2001-05-22 | Plastic integrated circuit device package having exposed lead surface |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/863,359 Expired - Lifetime US6586677B2 (en) | 1999-08-25 | 2001-05-22 | Plastic integrated circuit device package having exposed lead surface |
Country Status (1)
Country | Link |
---|---|
US (2) | US20020100165A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010033018A1 (en) * | 2000-04-25 | 2001-10-25 | Hiroshi Kimura | Semiconductor device, its manufacturing method and electrodeposition frame |
US6769174B2 (en) * | 2002-07-26 | 2004-08-03 | Stmicroeletronics, Inc. | Leadframeless package structure and method |
US7169643B1 (en) * | 1998-12-28 | 2007-01-30 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, circuit board, and electronic apparatus |
US20070045875A1 (en) * | 2005-08-30 | 2007-03-01 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US20090001563A1 (en) * | 2007-06-27 | 2009-01-01 | Henry Descalzo Bathan | Integrated circuit package in package system with adhesiveless package attach |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
US7226811B1 (en) | 1998-06-10 | 2007-06-05 | Asat Ltd. | Process for fabricating a leadless plastic chip carrier |
US6989294B1 (en) | 1998-06-10 | 2006-01-24 | Asat, Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US7271032B1 (en) | 1998-06-10 | 2007-09-18 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US8330270B1 (en) | 1998-06-10 | 2012-12-11 | Utac Hong Kong Limited | Integrated circuit package having a plurality of spaced apart pad portions |
US7270867B1 (en) | 1998-06-10 | 2007-09-18 | Asat Ltd. | Leadless plastic chip carrier |
US7247526B1 (en) | 1998-06-10 | 2007-07-24 | Asat Ltd. | Process for fabricating an integrated circuit package |
US6933594B2 (en) * | 1998-06-10 | 2005-08-23 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
DE19962231A1 (en) * | 1999-12-22 | 2001-07-12 | Infineon Technologies Ag | Process for the production of micromechanical structures |
US6580031B2 (en) * | 2000-03-14 | 2003-06-17 | Amerasia International Technology, Inc. | Method for making a flexible circuit interposer having high-aspect ratio conductors |
US6949822B2 (en) * | 2000-03-17 | 2005-09-27 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
JP3634735B2 (en) * | 2000-10-05 | 2005-03-30 | 三洋電機株式会社 | Semiconductor device and semiconductor module |
US6734571B2 (en) * | 2001-01-23 | 2004-05-11 | Micron Technology, Inc. | Semiconductor assembly encapsulation mold |
EP2273542A3 (en) * | 2001-12-14 | 2011-10-26 | STMicroelectronics S.r.l. | Semiconductor electronic device and method of manufacturing thereof |
KR101009818B1 (en) * | 2002-04-11 | 2011-01-19 | 엔엑스피 비 브이 | Carrier, method of manufacturing a carrier and an electronic device |
US8236612B2 (en) * | 2002-04-29 | 2012-08-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6812552B2 (en) | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7799611B2 (en) * | 2002-04-29 | 2010-09-21 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
JP3536105B2 (en) * | 2002-06-21 | 2004-06-07 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
JP2004071670A (en) * | 2002-08-02 | 2004-03-04 | Fuji Photo Film Co Ltd | Ic package, connecting structure and electronic apparatus |
US7732914B1 (en) | 2002-09-03 | 2010-06-08 | Mclellan Neil | Cavity-type integrated circuit package |
US20040058478A1 (en) * | 2002-09-25 | 2004-03-25 | Shafidul Islam | Taped lead frames and methods of making and using the same in semiconductor packaging |
US20040108580A1 (en) * | 2002-12-09 | 2004-06-10 | Advanpack Solutions Pte. Ltd. | Leadless semiconductor packaging structure with inverted flip chip and methods of manufacture |
JP4245370B2 (en) * | 2003-02-21 | 2009-03-25 | 大日本印刷株式会社 | Manufacturing method of semiconductor device |
EP1658636B1 (en) * | 2003-08-29 | 2012-01-04 | Infineon Technologies AG | Chip support of a lead frame for an integrated circuit package |
US7009282B2 (en) * | 2003-09-26 | 2006-03-07 | Agere Systems Inc. | Packaged integrated circuit providing trace access to high-speed leads |
DE112004002761T5 (en) * | 2004-02-26 | 2007-02-08 | Infineon Technologies Ag | A non-leaded semiconductor device and a method to assemble them |
US20060090334A1 (en) * | 2004-11-01 | 2006-05-04 | Chen Chi H | Processes for packing memory cards by single mold |
TW200711080A (en) * | 2005-02-23 | 2007-03-16 | Lg Micron Ltd | Lead frame |
JPWO2007057954A1 (en) * | 2005-11-17 | 2009-04-30 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US7507603B1 (en) * | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7425464B2 (en) * | 2006-03-10 | 2008-09-16 | Freescale Semiconductor, Inc. | Semiconductor device packaging |
TWI313943B (en) * | 2006-10-24 | 2009-08-21 | Chipmos Technologies Inc | Light emitting chip package and manufacturing thereof |
EP2084744A2 (en) * | 2006-10-27 | 2009-08-05 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7993979B2 (en) | 2007-12-26 | 2011-08-09 | Stats Chippac Ltd. | Leadless package system having external contacts |
US8115285B2 (en) * | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
US20100044850A1 (en) * | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8124447B2 (en) * | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US20130077256A1 (en) * | 2010-06-09 | 2013-03-28 | Sharp Kabushiki Kaisha | Heat dissipation structure for electronic device |
CN102310602B (en) * | 2010-06-30 | 2014-03-26 | 鸿富锦精密工业(深圳)有限公司 | Aluminium-plastic composite structure and manufacture method thereof |
TWI420630B (en) | 2010-09-14 | 2013-12-21 | Advanced Semiconductor Eng | Semiconductor package structure and semiconductor package process |
TWI419290B (en) | 2010-10-29 | 2013-12-11 | Advanced Semiconductor Eng | Quad flat non-leaded package and manufacturing method thereof |
US8502363B2 (en) | 2011-07-06 | 2013-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with solder joint enhancement element and related methods |
CN103782403B (en) * | 2011-09-06 | 2017-06-30 | 克利公司 | Optical transmitting set packaging part and device and correlation technique with improved wire bonding |
US8674487B2 (en) | 2012-03-15 | 2014-03-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with lead extensions and related methods |
US9653656B2 (en) | 2012-03-16 | 2017-05-16 | Advanced Semiconductor Engineering, Inc. | LED packages and related methods |
EP2709143A1 (en) * | 2012-09-18 | 2014-03-19 | Gemalto SA | Moulding method for manufacturing an electronic package |
US9059379B2 (en) | 2012-10-29 | 2015-06-16 | Advanced Semiconductor Engineering, Inc. | Light-emitting semiconductor packages and related methods |
CN104010441A (en) * | 2014-05-29 | 2014-08-27 | 苏州锟恩电子科技有限公司 | PCB wire welding and dispensing machine easy to operate |
US9839133B2 (en) | 2014-06-04 | 2017-12-05 | Apple Inc. | Low-area overhead connectivity solutions to SIP module |
US9219025B1 (en) * | 2014-08-15 | 2015-12-22 | Infineon Technologies Ag | Molded flip-clip semiconductor package |
US10624214B2 (en) * | 2015-02-11 | 2020-04-14 | Apple Inc. | Low-profile space-efficient shielding for SIP module |
US9570381B2 (en) | 2015-04-02 | 2017-02-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages and related manufacturing methods |
KR102288460B1 (en) * | 2017-03-10 | 2021-08-10 | 삼성전자주식회사 | Electronic device including component separation structure |
CN112985471B (en) * | 2021-04-30 | 2021-11-02 | 深圳市汇顶科技股份有限公司 | Capacitive sensor and manufacturing method thereof |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3982979A (en) | 1973-06-28 | 1976-09-28 | Western Electric Company, Inc. | Methods for mounting an article on an adherent site on a substrate |
FR2524707B1 (en) | 1982-04-01 | 1985-05-31 | Cit Alcatel | METHOD OF ENCAPSULATION OF SEMICONDUCTOR COMPONENTS, AND ENCAPSULATED COMPONENTS OBTAINED |
US5200362A (en) | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
EP0546285B1 (en) | 1991-12-11 | 1997-06-11 | International Business Machines Corporation | Electronic package assembly with protective encapsulant material |
US5355283A (en) | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
US5474958A (en) | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
JP3541491B2 (en) | 1994-06-22 | 2004-07-14 | セイコーエプソン株式会社 | Electronic components |
JPH08306853A (en) | 1995-05-09 | 1996-11-22 | Fujitsu Ltd | Semiconductor device, manufacture thereof and manufacture of lead frame |
US5620928A (en) | 1995-05-11 | 1997-04-15 | National Semiconductor Corporation | Ultra thin ball grid array using a flex tape or printed wiring board substrate and method |
JPH098205A (en) | 1995-06-14 | 1997-01-10 | Dainippon Printing Co Ltd | Resin sealed semiconductor device |
JPH098206A (en) | 1995-06-19 | 1997-01-10 | Dainippon Printing Co Ltd | Lead frame and bga resin sealed semiconductor device |
JPH098207A (en) | 1995-06-21 | 1997-01-10 | Dainippon Printing Co Ltd | Resin sealed semiconductor device |
JP3163961B2 (en) | 1995-09-22 | 2001-05-08 | 日立電線株式会社 | Semiconductor device |
US5937512A (en) | 1996-01-11 | 1999-08-17 | Micron Communications, Inc. | Method of forming a circuit board |
US5977613A (en) | 1996-03-07 | 1999-11-02 | Matsushita Electronics Corporation | Electronic component, method for making the same, and lead frame and mold assembly for use therein |
US6001671A (en) | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
KR0185512B1 (en) * | 1996-08-19 | 1999-03-20 | 김광호 | Column lead type package and method of making the same |
US5894108A (en) | 1997-02-11 | 1999-04-13 | National Semiconductor Corporation | Plastic package with exposed die |
US5929522A (en) | 1998-04-17 | 1999-07-27 | Hestia Technologies, Inc. | Semiconductor non-laminate package and method |
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6247229B1 (en) * | 1999-08-25 | 2001-06-19 | Ankor Technology, Inc. | Method of forming an integrated circuit device package using a plastic tape as a base |
US6333252B1 (en) * | 2000-01-05 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6342730B1 (en) * | 2000-01-28 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
-
2000
- 2000-02-14 US US09/504,007 patent/US20020100165A1/en not_active Abandoned
-
2001
- 2001-05-22 US US09/863,359 patent/US6586677B2/en not_active Expired - Lifetime
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7169643B1 (en) * | 1998-12-28 | 2007-01-30 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, circuit board, and electronic apparatus |
US20010033018A1 (en) * | 2000-04-25 | 2001-10-25 | Hiroshi Kimura | Semiconductor device, its manufacturing method and electrodeposition frame |
US6800508B2 (en) * | 2000-04-25 | 2004-10-05 | Torex Semiconductor Ltd | Semiconductor device, its manufacturing method and electrodeposition frame |
US6769174B2 (en) * | 2002-07-26 | 2004-08-03 | Stmicroeletronics, Inc. | Leadframeless package structure and method |
US20040200062A1 (en) * | 2002-07-26 | 2004-10-14 | Stmicroelectronics, Inc. | Leadframeless package structure and method |
US20060261450A1 (en) * | 2002-07-26 | 2006-11-23 | Stmicroelectronics, Inc. | Leadframeless package structure and method |
US20070045875A1 (en) * | 2005-08-30 | 2007-03-01 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US7807505B2 (en) * | 2005-08-30 | 2010-10-05 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US20100327462A1 (en) * | 2005-08-30 | 2010-12-30 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US8704380B2 (en) | 2005-08-30 | 2014-04-22 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US20090001563A1 (en) * | 2007-06-27 | 2009-01-01 | Henry Descalzo Bathan | Integrated circuit package in package system with adhesiveless package attach |
US8203214B2 (en) | 2007-06-27 | 2012-06-19 | Stats Chippac Ltd. | Integrated circuit package in package system with adhesiveless package attach |
Also Published As
Publication number | Publication date |
---|---|
US20020027010A1 (en) | 2002-03-07 |
US6586677B2 (en) | 2003-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6586677B2 (en) | Plastic integrated circuit device package having exposed lead surface | |
US6247229B1 (en) | Method of forming an integrated circuit device package using a plastic tape as a base | |
US6433277B1 (en) | Plastic integrated circuit package and method and leadframe for making the package | |
US6399415B1 (en) | Electrical isolation in panels of leadless IC packages | |
US7863757B2 (en) | Methods and systems for packaging integrated circuits | |
US7122406B1 (en) | Semiconductor device package diepad having features formed by electroplating | |
US9595453B2 (en) | Chip package method and package assembly | |
US7332375B1 (en) | Method of making an integrated circuit package | |
WO2006074543A1 (en) | Thin array plastic package without die attach pad and process for fabricating the same | |
US6769174B2 (en) | Leadframeless package structure and method | |
US7993981B2 (en) | Electronic device package and method of manufacture | |
US7354795B2 (en) | Methods for packaging and encapsulating semiconductor device assemblies that include tape substrates | |
US7112474B1 (en) | Method of making an integrated circuit package | |
JP3137323B2 (en) | Semiconductor device and manufacturing method thereof | |
US7005326B1 (en) | Method of making an integrated circuit package | |
US20040232531A1 (en) | Semiconductor package device and method for fabricating the same | |
US7030474B1 (en) | Plastic integrated circuit package and method and leadframe for making the package | |
US7071541B1 (en) | Plastic integrated circuit package and method and leadframe for making the package | |
US6893900B1 (en) | Method of making an integrated circuit package | |
JP3569642B2 (en) | Semiconductor device carrier substrate, method of manufacturing the same, and method of manufacturing a semiconductor device | |
JP2000332146A (en) | Resin-sealed semiconductor device, circuit material usable therefor and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: AMKOR TECHNOLOGY, ARIZONA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLEEN, THOMAS P.;REEL/FRAME:010615/0961 Effective date: 20000210 |
|
AS | Assignment |
Owner name: SOCIETE GENERALE, NEW YORK Free format text: SECURITY INTEREST;ASSIGNORS:AMKOR TECHNOLOGY, INC.;GUARDIAN ASSETS, INC.;REEL/FRAME:011491/0917 Effective date: 20000428 |
|
AS | Assignment |
Owner name: CITICORP USA, INC., NEW YORK Free format text: SECURITY INTEREST;ASSIGNORS:SOCIETE GENERALE;GUARDIAN ASSETS, INC.;REEL/FRAME:011682/0416 Effective date: 20010330 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |