US8674485B1 - Semiconductor device including leadframe with downsets - Google Patents

Semiconductor device including leadframe with downsets Download PDF

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US8674485B1
US8674485B1 US12963431 US96343110A US8674485B1 US 8674485 B1 US8674485 B1 US 8674485B1 US 12963431 US12963431 US 12963431 US 96343110 A US96343110 A US 96343110A US 8674485 B1 US8674485 B1 US 8674485B1
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inner
semiconductor
die
leads
package
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Gi Jeong Kim
Jae Yoon Kim
Kyu Won Lee
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Amkor Technology Inc
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Amkor Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49558Insulating layers on lead frames, e.g. bridging members
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

In one embodiment, a semiconductor package includes a generally planar die paddle or die pad that defines multiple peripheral edge segments, and includes one or more tie bars protruding therefrom. In addition, the semiconductor package includes a plurality of leads, portions of which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body. The one or more tie bars and the plurality of leads include downsets that are sized and oriented relative to each other to facilitate enhanced manufacturing.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

Not Applicable

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to integrated circuit package technology and, more particularly, to an increased capacity semiconductor device or package (e.g., a quad flat pack or QFP semiconductor package) which includes a uniquely configured leadframe adapted to provide various efficiencies and economies in the manufacturing process for the semiconductor package.

2. Description of the Related Art

Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.

The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body. Exemplary semiconductor packages or devices employing leadframes include a through-hole mounting dual type inline package (DIP), a surface mounting type quad flat package (QFP), and a small outline package (SOP).

As indicated above, one type of semiconductor package commonly including a leadframe is a quad flat pack (QFP) package. QFP semiconductor packages or devices are particularly advantageous for their smaller size and superior electrical performance. A typical QFP package comprises a thin, generally square package body defining four peripheral sides of substantially equal length. Protruding from each of the four peripheral sides of the package body are a plurality of leads which each have a generally gull-wing configuration. Portions of the leads are internal to the package body, and are electrically connected to respective ones of the pads or terminals of a semiconductor die also encapsulated within the package body. The semiconductor die is itself mounted to a die paddle or die pad of the QFP package leadframe. In certain types of QFP packages referred to as QFP exposed pad packages, one surface of the die pad is exposed within the bottom surface of the package body. When the leadframe is in its original, unsingulated state, both the leads and the die pad are typically attached to a peripheral dambar, with the attachment of the die pad to the dambar often being facilitated by multiple tie bars which protrude from the die pad.

In those leadframes having the above-described structural attributes, a downset is typically formed in each of the tie bars that results in the die pad and at least portions of the leads residing on respective ones of spaced, generally parallel planes. The downsets in the tie bars are typically formed in close proximity to the die pad. The positioning of the die pad relative to the leads attributable to the inclusion of the downsets and the tie bars is often selected to ensure that the semiconductor die mounted to the die pad is fully covered by the encapsulant material which is ultimately applied thereto and hardens into the package body of the semiconductor package. In addition to ensuring that the semiconductor die is completely covered by the encapsulant material, the position of the die pad relative to the leads resulting from the inclusion of the downsets in the tie bars is also selected to ensure that the wire bonds used to facilitate the electrical connection of the semiconductor die to the leads are also fully covered by the encapsulant material applied thereto.

In the manufacturing process for a semiconductor package such as a QFP package including a leadframe having the above-described structural attributes, the leadframe is typically mounted on a heat block for wire bonding. In this stage of the manufacturing process, a recess having a predetermined depth in which the downsets of the tie bars and the die pad are mounted is formed in the heat block. Stated another way, a recess having a predetermined depth is formed in the heat block to allow the die pad of the leadframe to be mounted and seated therein.

However, one of the drawbacks in the design of the above-described leadframes is attributable to the proximity which must normally be maintained between the inner ends or tips of the leads and the peripheral edge of the die pad. In this regard, if the inner ends or tips of the leads are positioned too close to the die pad, such leads are typically not seated in a stable manner in the recess of the heat block, but rather remain unsupported in such recess, thus causing severe bouncing during the wire bonding process and often resulting in poor wire bonding efficiency. Though this particular problem is lessened by positioning the inner ends or tips of the leads further from the die pad, such increased separation necessitates an undesirable increase in the length of those wires used in the wire bonding process to facilitate the electrical connection of the semiconductor die to the leads. The present invention provides a leadframe which is suitable for integration into a semiconductor device or package such as a QFP package and addresses many of the aforementioned shortcomings. Among other things, the leadframe of the present invention is adapted to provide various efficiencies and economies in the manufacturing process for a semiconductor package including the same. These, as well as other features and attributes of the present invention, will be discussed in more detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein:

FIG. 1 is a top plan view of a first embodiment of an unsingulated leadframe which may integrated into a semiconductor package constructed in accordance with the present invention, further depicting a tape layer which may be applied to the leadframe;

FIG. 1A is a partial top perspective view of the leadframe shown in FIG. 1;

FIG. 2 is a top plan view of a second embodiment of an unsingulated leadframe which may integrated into a semiconductor package constructed in accordance with the present invention, further depicting a tape layer which may be applied to the leadframe;

FIG. 3 is a top plan view of a third embodiment of an unsingulated leadframe which may be integrated into a semiconductor package constructed in accordance with the present invention;

FIG. 4 is a top plan view of a fourth embodiment of an unsingulated leadframe which may be integrated into a semiconductor package constructed in accordance with the present invention;

FIG. 5 is a top plan view of a fifth embodiment of an unsingulated leadframe which may be integrated into a semiconductor package constructed in accordance with the present invention;

FIG. 6 is a partial top perspective view of a heat block which may be used in the fabrication process for a semiconductor package including a leadframe constructed in accordance with any embodiment of the present invention;

FIG. 7A is a partial top perspective view of the leadframe shown in FIGS. 1 and 1A as interfaced to the heat block shown in FIG. 6 as a precursor to the initiation of a wire bonding process;

FIG. 7B is a partial side-elevational view of the leadframe shown in FIGS. 1 and 1A as interfaced to the heat block shown in FIG. 6 as a precursor to the initiation of a wire bonding process;

FIG. 8 is a partial top perspective view of the leadframe shown in FIGS. 1 and 1A having a semiconductor die attached and wire bonded thereto;

FIG. 9 is a cross-sectional view of a semiconductor package constructed in accordance with a first embodiment of the present invention and including the leadframe shown in FIGS. 1 and 1A subsequent to the singulation thereof;

FIG. 10 is a cross-sectional view of a semiconductor package constructed in accordance with a second embodiment of the present invention and including the leadframe shown in FIGS. 1 and 1A subsequent to the singulation thereof;

FIG. 11 is a cross-sectional view of a semiconductor package constructed in accordance with a third embodiment of the present invention and including the leadframe shown in FIGS. 1 and 1A subsequent to the singulation thereof; and

FIG. 12 is a cross-sectional view of a semiconductor package constructed in accordance with a fourth embodiment of the present invention and including the leadframe shown in FIGS. 1 and 1A subsequent to the singulation thereof.

Common reference numerals are used throughout the drawings and detailed description to indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein the showings are for purposes of illustrating preferred embodiments of the present invention only, and not for purposes of limiting the same, FIGS. 1 and 1A depict a leadframe 100 which is constructed in accordance with a first embodiment of the present invention. The leadframe 100 is adapted for integration into a semiconductor device or semiconductor package, including the semiconductor packages 200, 300, 400, 500 which are shown in respective ones of FIGS. 9-12, and will be described in more detail below.

The leadframe 100 of the present invention comprises a generally quadrangular (e.g., square) die pad 110 which defines four peripheral edge segments 111 and four corner regions 112. Integrally connected to the die pad 110 is a plurality of tie bars 120. More particularly, the leadframe 100 includes four tie bars 120 which extend diagonally from respective ones of the four corner regions 112 defined by the die pad 110. Each of the tie bars 120 is integrally connected to a peripheral dambar 140 of the leadframe 100. As such, as is seen in FIG. 1, the die pad 110 is circumvented by the dambar 140. The dambar 140 itself has a generally quadrangular (e.g., square) configuration.

As is best seen in FIG. 1A, each of the tie bars 120 is bent to include a downset 123 therein, the downset 123 being located between the die pad 110 and the dambar 140. Due to the inclusion of the downset 123 therein, each of the tie bars 120 defines a first tie bar region 121 which is disposed between the die pad 110 and the downset 123 and extends in generally co-planar relation to the die pad 110, and a second tie bar region 122 which extends between the downset 123 and the dambar 140 and resides on a plane which is elevated above that of the die pad 110. Stated another way, the die pad 110 and the first tie bar regions 121 of the tie bars 120 reside on a first plane, with the second tie bar regions 122 of the tie bars 120 and the dambar 140 each residing on a second plane which is disposed in spaced, generally parallel relation to the first plane.

As is further apparent from FIGS. 1 and 1A, the first tie bar region 121 of each tie bar 120 is of a length exceeding that of the second tie bar region 122 thereof. In other words, the second tie bar region 122 of each tie bar 120 is shorter than the corresponding first tie bar region 121 thereof. Additionally, the second tie bar region 122 of each tie bar 120 is preferably formed to define a locking projection 125 a having an aperture 125 b extending through the approximate center thereof. During the fabrication process for a semiconductor device or package including the leadframe 100, the encapsulant material used to form the package body of the semiconductor package is able to flow over the locking projection 125 a of each of the tie bars 120, and through the locking aperture 125 b thereof, thus improving the bonding or mechanical interlock between the package body of the semiconductor package and those portions of the tie bars 120 covered or encapsulated thereby.

As indicated above, the tie bars 120 of the leadframe 100 are integrally connected to the dambar 140 which circumvents the die pad 110. As also indicated above, the dambar 140 is provided in the form of a substantially quadrangular ring which interconnects the distal ends of the tie bars 120, thus resulting in the dambar 140 extending in generally co-planar relation to the second tie bar regions 122 of the tie bars 120. As seen in FIG. 1, the dambar 140 defines four peripheral edge segments which extend in spaced, generally parallel relation to respective ones of the peripheral edge segments 111 defined by the die pad 110. In the fabrication process for the semiconductor package including the leadframe 100, the dambar 140 is singulated or removed from the leadframe 100 to electrically isolate various structural features of the leadframe 100 from each other, as will be described in more detail below.

The leadframe 100 further comprises a plurality of inner leads 130 which are integrally connected to the dambar 140 and extend inwardly therefrom toward the die pad 110. More particularly, the inner leads 130 are segregated into four sets, with the inner leads 130 of each set being integrally connected to and extending inwardly from a respective one of the four peripheral edge segments defined by the dambar 140 toward a corresponding one of the four peripheral edge segments 111 defined by the die pad 110. The inner leads 130 of each set are also arranged at a predetermined pitch and are each of a predetermined length.

In the leadframe 100, each of the inner leads 130 is bent to include a downset 133 therein. Due to the inclusion of the downset 133 therein, each of the inner leads 130 includes a first inner lead region 131 which is disposed between the die pad 110 and the downset 133 and extends in generally co-planar relation to the die pad 110, and a second inner lead region 132 which extends between the downset 133 and the dambar 140 and resides on a plane which is elevated above that of the die pad 110 and the corresponding first inner lead region 131. Thus, the die pad 110, the first tie bar regions 121 of the tie bars 120 and the first inner lead regions 131 of the inner leads 130 reside on a first plane, with the second tie bar regions 122, the second inner lead regions 132 and the dambar 140 each residing on a second plane which is disposed in spaced, generally parallel relation to the first plane.

As is also apparent from FIGS. 1 and 1A, the first inner lead region 131 of each inner lead 130 is longer than the second inner lead region 132 thereof. In addition, within each set of the inner leads 130, the lengths of the second inner lead regions 132 gradually decrease as the inner leads 130 are oriented closer toward the center of the adjacent, corresponding peripheral edge segment 111 of the die pad 110. More particularly, each set of the inner leads 130 extends between a corresponding pair of the tie bars 120, toward a corresponding peripheral edge segment 111 of the die pad 110. The second inner lead regions 132 of the outermost pair of the inner leads 130 of the set (which are disposed closest to the tie bars 120) are of the greatest length, with the second inner lead regions 132 of the adjacent pair of the inner leads 130 which is aligned with the approximate center of the corresponding peripheral edge segment 111 of the die pad 110 being of the shortest length. In addition, as is also apparent from FIG. 1, the distance separating the tips of first inner lead regions 131 of the inner leads 130 of the same set from the corresponding peripheral edge segment 111 of the die pad 110 gradually increases as the inner leads 130 move from the tie bars 120 of the corresponding pair toward the center of such corresponding peripheral edge segment 111 of the die pad 110.

In the leadframe 100, the second inner lead region 132 of each inner lead 130 is preferably formed to define a locking projection 135 a having an aperture 135 b extending through the approximate center thereof. During the fabrication process for a semiconductor device or package including the leadframe 100, the encapsulant material used to form the package body of the semiconductor package is also able to flow over the locking projection 135 a of each of the inner leads 130, and through the locking aperture 135 b thereof, thus improving the bonding or mechanical interlock between the package body of the semiconductor package and those portions of the inner leads 130 covered or encapsulated thereby.

The leadframe 100 constructed in accordance with the present invention further comprises a plurality of outer leads 150 which are integrally connected to the dambar 140. The outer leads 150, like the inner leads 130, are preferably segregated into four sets, with each set of the outer leads 150 extending between an adjacent pair of the tie bars 120. The outer leads 150 of each set also extend generally perpendicularly relative to a respective one of the peripheral edge segments of the dambar 140 at a predetermined length, the outer leads 150 of each set also being arranged at a predetermined pitch. Additionally, as best seen in FIG. 1, each outer lead 150 is preferably aligned with the locking projection 135 a within the second inner lead region 132 of a corresponding inner lead 130. However, each outer lead is separated from the second inner lead region 132 of the corresponding inner lead 130 by the dambar 140.

Based on the structural attributes of the leadframe 100 as described above, the die pad 110, the first tie bar regions 121 of the tie bars 120 and the first inner lead regions 131 of the inner leads 130 reside on a first plane, with the second tie bar regions 122 of the tie bars 120, the second inner lead regions 132 of the inner leads 130, the dambar 140 and the outer leads 150 each residing on a second plane which is disposed in spaced, generally parallel relation to the first plane. Additionally, during the process of fabricating a semiconductor package including the leadframe 100, the singulation or removal of the dambar 140 from the leadframe 100 is preferably completed in manner wherein each of the inner leads 130 is integrally connected to that outer lead 150 of the corresponding set which is aligned therewith, though each joined pair of inner and outer leads 130, 150 is electrically isolated from every other joined pair thereof as well as the die pad 110 and tie bars 120. However, even after the singulation of the dambar 140, the integral connection between the tie bars 120 and the die pad 110 is maintained. In a semiconductor package including the leadframe 100 having the dambar 140 removed therefrom in the aforementioned manner, each joined pair of inner and outer leads 130, 150 provides a common electrical path, the outer leads 150 further providing a modality to electrically connect the semiconductor package to an external device.

It is contemplated that the leadframe 100 of the present invention may be made of a copper series material (e.g., Cu:Fe:P=99.8:0.01:0.025), a copper alloy series material (e.g., Cu:Cr:Sn:Zn=99:0.25:0.25:0.22), an alloy 42 series material (e.g., Fe:Ni=58:42), and equivalents thereof. However, those of ordinary skill in the art will recognize that the present invention is not intended to be limited to any specific material for the leadframe 100.

In FIG. 1, the leadframe 100 is depicted as having a ring-shape segment of lead locking tape 160 adhered to the top surface thereof, and more particularly to the top surfaces of the first inner lead regions 131 of the inner leads 130. The lead locking tape 160 allows the inner leads 130, and in particular the first inner lead regions 131 thereof, to be positioned at the same height and to be spaced at a predetermined distance apart from each other. Additionally, when viewed from the perspective shown in FIG. 1, the lead locking tape 160 is also adhered to the top surfaces of the tie bars 120, and in particular the top surfaces of the first tie bar regions 121 thereof. The lead locking tape 160 is an optional element of the leadframe 100 and any semiconductor package fabricated to include the same. Additionally, the shape of the lead locking tape 160 shown in FIG. 1 is exemplary only, in that the lead locking tape 160 may consist of separate segments rather than a continuous quadrangular frame as depicted. As indicated above, the lead locking tape 160, if included in the leadframe 100, is used to prevent the inner leads 130 from undergoing any deformation or variation in position during the fabrication process related to the semiconductor package including the leadframe 100.

As further shown in FIG. 1, it is contemplated that the leadframe 100 may include a plating region 114 which is formed on the periphery of the top surface of the die pad 110, and extends to each of the peripheral edge segments 111 thereof. In addition to the plating region 114 of the die pad 110, a portion of the top surface of the first inner lead region 131 of each inner lead 130 may be provided with a plating region 134 which extends to the end thereof disposed closest to the die pad 110. Thus, it is the top surface of the first inner lead portion 131 of each of the inner leads 130 which defines the wire bonding area thereof. In this regard, the plating regions 114, 134 allow conductive wires to be more effectively bonded to both the die pad 110 and the first inner lead regions 131 of the inner leads during the process of manufacturing a semiconductor device or package including the leadframe 100. The plating regions 114, 134 may be made of gold (Au), silver (Ag), nickel (Ni), palladium (Pd), solder, and equivalents thereof. However, those of ordinary skill in the art will recognize that the present invention is not intended to be limited to any specific material for the plating regions 114, 134. Alternatively, the leadframe 100 may a pre-plated leadframe (PPF) to provide enhance wire bonding areas. Additionally, it should be noted that neither the lead locking tape 160 or plating regions 114, 134 are depicted in FIG. 1A.

Those or ordinary skill in the art will recognize that the number of inner leads 130 and outer leads 150 shown in FIG. 1 is for illustrative purposes only, and may be modified according to application field. Additionally, though the inner leads 130 and outer leads 150 are each shown as each being segregated into four sets, it will be recognized that fewer sets of the inner leads 130 and outer leads 150 may be provided, and may be arranged along any combination of two or three of the peripheral edge segments 111 of the die pad 110. Moreover, less than four tie bars 120 may be included in the leadframe 100, extending to respective corners of the die pad 110 in any combination. It is further contemplated that the leadframe 100 may be fabricated through the implementation of a chemical etching process or alternatively a mechanical stamping process.

Referring now to FIG. 2, there is shown a leadframe 101 constructed in accordance with a second embodiment of the present invention. The leadframe 101 bears substantial structural similarity to the above-described leadframe 100, with only the distinctions between the leadframes 100, 101 being described below.

The sole distinction between the leadframes 100, 101 lies in the structural features of the inner leads 130 a of the leadframe 101 in comparison to the inner leads 130 of the leadframe 100. In the leadframe 101, each of the inner leads 130 a is bent to include a downset 133 a therein. Due to the inclusion of the downset 133 a therein, each of the inner leads 130 a includes a first inner lead region 131 a which is disposed between the die pad 110 and the downset 133 a and extends in generally co-planar relation to the die pad 110, and a second inner lead region 132 a which extends between the downset 133 a and the dambar 140 and resides on a plane which is elevated above that of the die pad 110 and the corresponding first inner lead region 131 a. Thus, the die pad 110, the first tie bar regions 121 of the tie bars 120 and the first inner lead regions 131 a of the inner leads 130 a reside on a first plane, with the second tie bar regions 122, the second inner lead regions 132 a and the dambar 140 each residing on a second plane which is disposed in spaced, generally parallel relation to the first plane.

As is also apparent from FIG. 2, the first inner lead region 131 a of each inner lead 130 a is longer than the second inner lead region 132 a thereof. In addition, within each of the four sets of the inner leads 130 a, the lengths of the second inner lead regions 131 a gradually decrease as the inner leads 130 a move away from that pair of the tie bars 120 between which such set of inner leads 130 a is positioned, and toward each of the opposed ends of the adjacent, corresponding peripheral edge segment 111 of the die pad 110. More particularly, each set of the inner leads 130 a extends between a corresponding pair of the tie bars 120, toward a corresponding peripheral edge segment 111 of the die pad 110. The second inner lead regions 132 a of the outermost groups of about six or seven inner leads 130 a each of the set (which are disposed closest to the tie bars 120) are of gradually decreasing length, with the lengths of the second inner regions 132 a of the remaining inner leads 130 a of the set disposed between the outermost groups being of substantially equal length. As further seen in FIG. 2, the downsets 133 a of the inner leads 130 a included in each of the two outermost groups are substantially linearly aligned with the downset 123 of the adjacent tie bar 120. Forming the downsets 133 a in the inner leads 130 a in the orientations shown in FIG. 2 assists in avoiding undesirable deformation of the inner leads 130 a.

Referring now to FIG. 3, there is shown a leadframe 102 constructed in accordance with a third embodiment of the present invention. The leadframe 102 also bears substantial structural similarity to the above-described leadframe 100, with only the distinctions between the leadframes 100, 102 being described below.

The sole distinction between the leadframes 100, 102 lies in the number and structural features of the inner leads 130 b of the leadframe 102 in comparison to the inner leads 130 of the leadframe 100. As is apparent from FIG. 3, the first inner lead region 131 b of each inner lead 130 b is longer than the second inner lead region 132 b thereof. In addition, within each set of the inner leads 130 b, the lengths of the second inner lead regions 132 b gradually decrease as the inner leads 130 b are oriented closer toward the center of the adjacent, corresponding peripheral edge segment 111 of the die pad 110. More particularly, each set of the inner leads 130 b extends between a corresponding pair of the tie bars 120, toward a corresponding peripheral edge segment 111 of the die pad 110. The second inner lead regions 132 b of the outermost pair of the inner leads 130 b of the set (which are disposed closest to the tie bars 120) are of the greatest length, with the second inner lead region 132 b of the single, center inner lead 130 b which is aligned with the approximate center of the corresponding peripheral edge segment 111 of the die pad 110 being of the shortest length.

In the leadframe 102, the number of leads 130 b included in each set allows for such set to define a single, center lead, in contrast to a center adjacent pair as in the leadframes 100, 101 described above. As further shown in FIG. 3, in the center lead 130 b of each set included in the leadframe 102, the downset 133 b thereof is actually formed in a bent or angled configuration, as opposed to be generally straight as in the remaining leads 130 b of the same set. The formation of the downset 133 b of the central lead 130 b of each set in this manner minimizes potential damage to the leads 130 b of each set which may otherwise occur during the process of forming the downsets 133 b therein.

Referring now to FIG. 4, there is shown a leadframe 103 constructed in accordance with a fourth embodiment of the present invention. The leadframe 103 bears substantial structural similarity to the above-described leadframe 102, with only the distinctions between the leadframes 102, 103 being described below.

The sole distinction between the leadframes 102, 103 lies in the structural features of the inner leads 130 c of the leadframe 103 in comparison to the inner leads 130 b of the leadframe 102. As is apparent from FIG. 4, the first inner lead region 131 c of each inner lead 130 c is longer than the second inner lead region 132 c thereof. In addition, within each set of the inner leads 130 c, the lengths of the second inner lead regions 132 c gradually decrease as the inner leads 130 c are oriented closer toward the center of the adjacent, corresponding peripheral edge segment 111 of the die pad 110. More particularly, each set of the inner leads 130 c extends between a corresponding pair of the tie bars 120, toward a corresponding peripheral edge segment 111 of the die pad 110. The second inner lead regions 132 c of the outermost pair of the inner leads 130 c of the set (which are disposed closest to the tie bars 120) are of the greatest length, with the second inner lead region 132 c of the single, center inner lead 130 c which is aligned with the approximate center of the corresponding peripheral edge segment 111 of the die pad 110 being of the shortest length.

In the leadframe 103, the number of leads 130 c included in each set allows for such set to define a single, center lead, in contrast to a center adjacent pair as in the leadframes 100, 101 described above. As further shown in FIG. 4, in the center lead 130 c of each set included in the leadframe 102, and those two leads 130 c disposed adjacent thereto (i.e., along each of the opposed sides thereof), the downsets 133 c of such leads 130 c are each substantially parallel to the corresponding segment of the dambar 140, as well as the adjacent peripheral edge segment 111 of the die pad 110. The formation of the downsets 133 c of the central three leads 130 c of each set in this manner minimizes potential damage to the leads 130 c of each set which may otherwise occur during the process of forming the downsets 133 c therein.

Referring now to FIG. 5, there is shown a leadframe 104 constructed in accordance with a fifth embodiment of the present invention. The leadframe 104 bears substantial structural similarity to the above-described leadframe 103, with only the distinctions between the leadframes 103, 104 being described below.

The sole distinction between the leadframes 103, 104 lies in the structural features of the inner leads 130 d and tie bars 120 of the leadframe 104 in comparison to the inner leads 130 c and tie bars 120 of the leadframe 103. More particularly, as is apparent from FIG. 5, the inner leads 130 d differ from the inner leads 130 c by virtue of the omission of the locking projection 135 a and the locking aperture 135 b in each of the inner leads 130 d. Similarly, the tie bars 120 of the leadframe 104 differ from those included in the leadframe 103 by virtue of the omission of the locking projection 125 a and the locking aperture 125 b in each of the tie bars 120 of the leadframe 104. The proximity of the downsets 133 d, 123 to the dambar 140, and the ability of such downsets 133 d, 123 to facilitate a firm mechanical interlock of the inner leads 130 d and tie bars 120 to the package body of the semiconductor device when covered by the encapsulant material which ultimately hardens into the package body, avoids the need for the locking projections 125 a, 135 a, and the locking apertures 125 b, 135 b.

Referring now to FIG. 6, there is shown a partial perspective view of a heat block 10 in which any of the above-described leadframes 100, 101, 102, 103, 104 may be positioned during a wire bonding process involved in the fabrication of a semiconductor device or package incorporating any of such leadframes 100, 101, 102, 103, 104. In FIG. 8, a semiconductor device or package in a partially fabricated state is depicted, such semiconductor package including the leadframe 100 shown in FIGS. 1 and 1A. In FIG. 8, a semiconductor die 211 is shown as being attached to the top surface of the die pad 110, the peripheral edge of the semiconductor die 211 being spaced inwardly from the peripheral edge segments 111 of the die pad 110. Additionally, in FIG. 8, the semiconductor die 211 is shown as being electrically connected to the first inner lead regions 131 of each of the inner leads 130 through the use of a multiplicity of conductive wires 220. As previously explained, a portion of the top surface of the first inner lead region 131 of each inner lead 130 may be provided with a plating region 134 which extends to the end thereof disposed closest to the die pad 110, the plating regions 134 enhancing the electrical connection of the conductive wires 220 to the first inner lead regions 131 of respective ones of the inner leads 130. Though not shown in FIG. 8, it is contemplated that one or more conductive wires 220 may be used to electrically connect the semiconductor die 211 to the peripheral portion of the top surface of the die pad 110. In this regard, as also indicated above, the leadframe 100 preferably includes a plated region 114 which is formed on the periphery of the top surface of the die pad 110 and extends to each of the peripheral edge segments 111 thereof, such plating region 114 thus being used to enhance the integrity of the electrical connection of any conductive wire 220 to the die pad 110.

The heat block 10 shown in FIG. 6 is an essential component needed to complete the process of electrically connecting the semiconductor die 211 to the inner leads 130 through the use of the conductive wires 220 in the manner described above in relation to FIG. 8. In this regard, in order to achieve good bonding between the conductive wires 220 and the top surfaces of the first inner lead regions 131 of the inner leads 130, or between the conductive wire(s) 220 and the top surface of the die pad 110, a high level of heat must be applied to the leadframe 100. The heat block 10 provides such heat to the leadframe 100 when the leadframe 100 is positioned thereon during the wire bonding process. To facilitate the desired engagement of the leadframe 100 thereto, the heat block 10 includes a body 12 which has a protruding part 11 protruding upwardly from one surface thereof.

Referring now to FIGS. 7A and 7B, the leadframe 100 is depicted as being cooperatively engaged to the heat block 10 shown in FIG. 6 in a manner as would occur to complete the wire bonding process between the semiconductor die 211 and the inner leads 130 of the leadframe 100 as described above in relation to the partially fabricated semiconductor package shown in FIG. 8. As shown in FIGS. 7A and 7B, the bottom surface of the die pad 110, and the bottom surfaces of the first inner lead regions 131 of the inner leads 130, which extend in generally co-planar relation to each other, are positioned or seated upon the top surface of the protruding part 11 of the heat block 10. As a result, as seen in FIG. 7B, the downsets 132 and second inner lead regions 133 of the inner leads 130 extend in spaced, juxtaposed relation to that surface of the body 12 of the heat block 10 from which the protruding part 11 extends. Since both the die pad 110 and at least portions of the first inner lead regions 131 of the inner leads 130 are positioned upon and supported by the protruding part 11 of the heat block 10, they are not susceptible to being “bounced” during the process of bonding corresponding ends of the conductive wires 220 thereto, thereby avoiding wire bonding failures. Heat transfer between the heat block 10 and the leadframe 100 is also maximized by the direct contact of the die pad 110 and first inner lead regions 131 of the inner leads 130 with the protruding part 11.

In addition, even if the first inner lead regions 131 of the inner leads 130 are formed to be disposed in very close proximity to corresponding peripheral edge segments 111 of the die pad 110, the protruding part 11 of the heat block 10 maintains the generally co-planar relationship between the die pad 110 and the first inner lead regions 131 during the completion of the wire bonding process described above. Stated another way, since a gap or space is not created between the first inner lead regions 131 and the heat block 10, a bouncing phenomenon does not occur to the first inner lead regions 131 during the wire bonding process, such bouncing phenomenon also being prevented as a result of the inner leads 130 and the outer leads 150 also being mutually supported by the dambar 140. Further, since the downsets 123 of the tie bars 120 are not positioned between the plating regions 134 of the first inner lead regions 131 and the die pad 110, or even at a location close to the plating regions 134 of the first inner lead regions 131, but rather are positioned outside of the lead locking tape 160, it is possible to minimize the distance separating the ends of the first inner lead regions 131 of the inner leads 130 from the corresponding peripheral edge segments 111 of the die pad 110, thereby allowing for a reduction in the length of the conductive wires 220 extending therebetween. As is well known in the electrical arts, if the length of the conductive wires 220 is reduced, the electrical resistance is reduced accordingly, thus ultimately improving the electrical characteristics of the semiconductor device or package including the leadframe 100.

Though FIGS. 7A and 7B partially depict the engagement of the leadframe 100 to the heat block 10, and FIG. 8 depicts a partially fabricated semiconductor package including the leadframe 100, those or ordinary skill in the art will recognize that the aforementioned discussion regarding FIGS. 7A, 7B and 8 is equally applicable to each of the leadframes 101, 102, 103 and 104 as well. Along these lines, it is contemplated that the heat block 10 can be used in conjunction with any type of leadframe, so long as such leadframe includes a die pad and first inner lead regions occupying a size or area which is smaller than or equal to that of the protruding part 11 of the heat block 10, as is the case with the die pad 110 and first inner lead regions 131 of the leadframe 100 as shown in FIGS. 7A and 7B. These relative proportions ensure that the tips of the inner leads remains stably seated during the wire bonding process, as opposed to being susceptible to bouncing during such wire bonding process which could result in frequent wire bonding failure.

Referring now to FIG. 9, there is shown a semiconductor device or semiconductor package 200 constructed in accordance with a first embodiment of the present invention, and fabricated to include the leadframe 100 described above in relation to FIGS. 1 and 1A. As will be recognized by those ordinary skill in the art, in the completed semiconductor package 200, the dambar 140 is singulated or removed from the leadframe 100 to facilitate the electrical isolation of the various structural features of the leadframe 100 from each other. More particularly, the dambar 140 is singulated in a manner wherein each of the inner leads 130 is integrally connected to that outer lead 150 of the corresponding set which is aligned therewith, though each joined pair of inner and outer leads 130, 150 is electrically isolated from every other joined pair thereof as well as the die pad 110 and the tie bars 120. However, even after the singulation of the dambar 140, the integral connection between the tie bars 120 and the die pad 110 is maintained.

In the semiconductor package 200, the semiconductor die 211 is attached to the top surface of the die pad 110 through the use of an adhesive layer 211 a. The semiconductor package 200 further comprises the above-described conductive wires 220 which are used to electrically connect the semiconductor die 211 to respective ones of the first inner lead regions 131 of the inner leads 130 in the same manner described above in relation to FIG. 8. As also indicated above, in electrically connecting the semiconductor die 211 to the inner leads 130, it is contemplated that the conductive wires 220 will be extended from the semiconductor die 211 to the plating regions 134 on the top surfaces of the first inner lead regions 131 of respective ones of the inner leads 130. Since the die pad 110 and the first inner lead regions 131 extend in generally co-planar relation to each other, the height of the conductive wires 220 is relatively small. Thus, the semiconductor package 200 may be fabricated to have a slimmer profile by virtue of maintaining the height of the conductive wires 220 at a reduced level. The lengths of the conductive wires 220 are also reduced by virtue of the first inner lead regions 131 of the inner leads 130 being formed in extremely close proximity to corresponding peripheral edge segments 111 of the die pad 110. This reduced length of the conductive wires 220 in turn reduces electrical resistance, and ultimately further improves the electrical characteristics of the semiconductor package 200. The conductive wires 220 may be fabricated from aluminum, copper, gold, silver, or a functional equivalent. However, those of ordinary skill in the art will recognize that the present invention is not limited to any particular material for the wires 220. Though not shown in FIG. 9, as indicated above, one or more conductive wires 220 may also be used to electrically connect the semiconductor die 211 directly to the peripheral portion of the top surface of the die pad 110, and in particular to the plating region 114 preferably formed thereon. Such electrical connection allows for the use of the plated die pad 110 as a ground region.

In the semiconductor package 200, the die pad 110, the tie bars 120, the first inner lead regions 131 of the inner leads 130, the downsets 133 of the inner leads 130, and portions of the second inner lead regions 132 of the inner leads 130 are encapsulated or covered by an encapsulant material which, upon hardening, forms a package body 230 of the semiconductor package 200. Also encapsulated by the package body 230 are the semiconductor die 211 and the conductive wires 220 used to electrically connect the same to the inner leads 130. The outer leads 150 are not covered by the package body 230, and hence protrude from respective sections of the peripheral side surface thereof. During the process of fabricating the semiconductor package 200, the dambar 140 of the leadframe 100 is also not covered by the package body 230, so that it may ultimately be removed in the aforementioned manner through the completion of a suitable singulation process subsequent to the formation of the package body 230.

Though not shown in FIG. 9, the exposed outer leads 150 may be bent to assume a gull-winged configuration to allow the same to be electrically connected to an underlying substrate such as a printed circuit board. As indicated above, in order to complete the fabrication of the semiconductor package 200 to allow the same to assume the configuration shown in FIG. 9, the dambar 140 must be removed from the leadframe 100 as explained above. In this regard, it is contemplated that a conventionally known debarring process may be implemented to remove the dambar 140.

Referring now to FIG. 10, there is shown a semiconductor device or semiconductor package 300 constructed in accordance with a second embodiment of the present invention. The semiconductor package 300 bears substantial structural similarity to the above-described semiconductor package 200, with only the distinctions between the semiconductor packages 200, 300 being described below.

The sole distinction between the semiconductor package 200, 300 lies in the inclusion of a second semiconductor die 311 in the semiconductor package 300. From the perspective shown in FIG. 10, the second semiconductor die 311 is attached to the top surface of the first semiconductor die 211 through the use of an adhesive layer 311 a. The second semiconductor die 311 is electrically connected to the first inner lead regions 131 of the inner leads 130 through the use of conductive wires 320 in the same manner described above in relation to the use of the conductive wires 220 to facilitate the electrical connection of the first semiconductor die 211 to the first inner lead regions 131 of the inner leads 130. Thus, each of the conductive wires 320 is electrically connected to and extended between the second semiconductor die 311 and the plating region 134 disposed on the top surface of the first inner lead region 131 of a corresponding one of the inner leads 130. In the semiconductor package 300, both the second semiconductor die 311 and the conductive wires 320 used to electrically connect the same to the inner leads 130 are covered by the package body 230.

As is further seen in FIG. 10, the width of the first semiconductor die 211 in the semiconductor package 300 exceeds that of the second semiconductor die 311. As a result of this size disparity, the second semiconductor die 311 does not interfere with the conductive wires 220 used to electrically connect the first semiconductor die 211 to the inner leads 130 when the second semiconductor die 311 is attached to the top surface of the first semiconductor die 211 through the use of the adhesive layer 311 a. Due to the die pad 110 and first inner lead regions 131 extending in generally co-planar relation to each other, the overall height or profile of the semiconductor package 300 is still minimized, despite the inclusion of the second semiconductor die 311 and the conductive wires 320 used to electrically connect the same to the inner leads 130.

Referring now to FIG. 11, there is shown a semiconductor device or semiconductor package 400 constructed in accordance with a third embodiment of the present invention. The semiconductor package 400 bears substantial structural similarity to the above-described semiconductor package 300, with only the distinctions between the semiconductor packages 300, 400 being described below.

In the semiconductor package 400, the second semiconductor die 311 described in relation to the semiconductor package 300 is replaced with a second semiconductor die 411 which is attached to the surface of the underlying first semiconductor die 211. However, rather than being directly attached to the underlying first semiconductor die 211 through the use of an adhesive layer such as the adhesive layer 311 a described above in relation to the semiconductor package 300, the second semiconductor die 411 in the semiconductor package 400 is maintained at a prescribed distance from the first semiconductor die 211 by virtue of a spacer 411 a being interposed therebetween. In this regard, it is contemplated that an adhesive layer will be applied to each of the opposed top and bottom surfaces of the spacer 411 a (as viewed from the perspective shown in FIG. 11), with the bottom surface of the spacer 411 a being attached to the top surface of the first semiconductor die 211, and the bottom surface of the second semiconductor die 411 being secured to the top surface of the spacer 411 a.

In contrast to the first and second semiconductor dies 211, 311 of the semiconductor package 300 which are described above as being of differing sizes, in the semiconductor package 400, the widths of the first and second semiconductor dies 211, 411 are substantially equal to each other. In addition, the width of the spacer 411 a is smaller than that of the first and second semiconductor dies 211, 411. The second semiconductor die 411 is electrically connected to the first inner lead regions 131 of the inner leads 130 through the use of conductive wires 420 in the same manner described above in relation to the use of the conductive wires 220 to facilitate the electrical connection of the first semiconductor die 211 to the first inner lead region 131 of the inner leads 130. Thus, each of the conductive wires 420 is electrically connected to and extended between the second semiconductor die 411 and the plating region 134 disposed on the top surface of the first inner lead region 131 of a corresponding one of the inner leads 130. In the semiconductor package 400, both the second semiconductor die 411 and the conductive wires 420 used to electrically connect the same to the inner leads 130 are covered by the package body 230.

In the semiconductor package 400, since the die pad 110 and the first inner lead regions 131 extend in generally co-planar relation to each other, the conductive wires 220 are formed such that they are downwardly wire-bonded from the first semiconductor die 211 to the first inner lead regions 131 of the inner leads 130. The downward wire bonding also holds true in relation to the conductive wires 420 extending from the second semiconductor die 411 to the first inner lead regions 131 of the inner leads 130. Such downward wire bonding of the conductive wires 220, 420 to the first inner lead regions 131 is adapted to prevent electrical shorting between the conductive wires 220, 420, or between the conductive wires 220 and the second semiconductor die 411. Indeed, if the first inner lead regions 131 were positioned higher than the die pad 110, there would be a greater susceptibility to the conductive wires 220 being electrically shorted to the second semiconductor die 411.

If, in the semiconductor package 400, the conductive wires 220 were wire bonded upwardly and the conductive wires 420 wire bonded downwardly, such conductive wires 220, 420 would cross each other into substantially X-shaped pattern, which would create substantially greater susceptibility to electrical shorting or other performance problems in the semiconductor package 400. However, in the semiconductor package 400 electrical shorting between the conductive wires 220, 420, between the conductive wires 220 and the second semiconductor die 411, and between adjacent first inner lead regions 131 (attributable to capillary contact) is substantially prevented by the structural features of the leadframe 100, in combination with the downward wire-bonding of the conductive wires 220, 420 as described above. This reduced susceptibility to electrical shorting is facilitated despite the first and second semiconductor dies 211, 411 being of substantially the same width and provided in a stacked arrangement. However, despite the first and second semiconductor dies 211, 411 being stacked, it is not necessary to form the spacer 411 a to be of excessive thickness, nor is it necessary to provide the first and second semiconductor dies 211, 411 in extremely small thicknesses. In addition, the height of the conductive wires 420 can be adjusted over a wide range, allowing wire bonding to be accomplished very easily.

Referring now to FIG. 12, there is shown a semiconductor device or semiconductor package 500 constructed in accordance with a fourth embodiment of the present invention. The semiconductor package 500 bears substantial structural similarity to the above-described semiconductor package 400, with only the distinctions between the semiconductor packages 400, 500 being described below.

In the semiconductor package 500, the second semiconductor die 411 described above in relation to the semiconductor package 400 is substituted with a second semiconductor die 511 which is of a greater width than the underlying first semiconductor die 211. Interposed between the first and second semiconductor die 211, 511 in the semiconductor package 500 is a spacer 511 a which is identically configured to the spacer 411 a described above, and is secured to each of the first and second semiconductor dies 211, 511 via adhesive layers in a manner also described above in relation to the semiconductor package 400. The second semiconductor die 511 is electrically connected to the first inner lead regions 131 of the inner leads 130 through the use of conductive wires 520 in the same manner described above in relation to the use of the conductive wires 220 to facilitate the electrical connection of the first semiconductor die 211 to the first inner lead regions 131 of the inner leads 130. Thus, each of the conductive wires 520 is electrically connected to and extends between the second semiconductor die 511 and the plating region 134 disposed on the top surface of the first inner lead region 131 of a corresponding one of the inner leads 130. In the semiconductor package 500, both the second semiconductor die 511 and the conductive wires 520 used to electrically connect the same to the inner leads 130 are covered by the package body 230.

In the semiconductor package 500, due to the die pad 110 and the first inner lead regions 131 extending in generally co-planar relation to each other, the conductive wires 220 are able to be formed to have a relatively small height, thus allowing them to facilitate the electrical connection of the first semiconductor die 211 to the inner leads 130, despite the increased sized of the second semiconductor die 511 relative to the first semiconductor die 211. In this regard, as viewed from the perspective shown in FIG. 12, the conductive wires 220 are not shorted to the second semiconductor die 511, despite the second semiconductor die 511 overhanging portions of the conductive wires 220.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure. For example, the semiconductor packages 200, 300, 400, 500 described above may include any of the above-described leadframes 101, 102, 103, 104 as an alternative to the leadframe 100.

Claims (20)

What is claimed is:
1. A semiconductor package comprising:
a die pad defining multiple peripheral edge segments;
a plurality of inner leads that each include a downset formed therein, the inner leads being segregated into at least two sets that extend along respective ones of at least two peripheral edge segments of the die pad, wherein each of the inner leads defines first and second inner lead regions that are separated by the downset therein, the first inner lead region being disposed between the downset and the die pad, and wherein the first inner lead region of each of the inner leads is longer than the second inner lead region thereof, and wherein the second inner lead regions of the inner leads of each set thereof are of gradually decreasing length as the inner leads are oriented closer toward the center of an adjacent, corresponding peripheral edge segment of the die pad;
at least one tie bar integrally connected to and extending from the die pad, the tie bar including a downset formed therein that is positioned to segregate the tie bar into at least two regions of differing length;
at least one semiconductor die attached to the die pad and electrically connected to at least one of the inner leads; and
a package body defining a peripheral side surface, the package body at least partially encapsulating the die pad, the inner leads, the tie bars and the semiconductor die such that the downsets of the inner leads and the tie bars are covered by the package body.
2. The semiconductor package of claim 1 further comprising a plurality of outer leads integrally connected to respective ones of the inner leads, at least portions of the outer leads protruding from the side surface of the package body.
3. The semiconductor package of claim 1, wherein the semiconductor die is electrically connected to the inner leads by conductive wires that are covered by the package body.
4. The semiconductor package of claim 1, wherein:
the tie bar defines first and second tie bar regions that are separated by the downset therein, the first tie bar region being disposed between the downset and the die pad;
the die pad, the first inner lead regions and the first tie bar region extend in generally co-planar relation to each other;
the second inner lead regions and the second tie bar region extend in generally co-planar relation to each other; and
conductive wires extending from the semiconductor die to respective ones of the first inner lead regions to electrically connect the semiconductor die thereto.
5. The semiconductor package of claim 1, wherein:
the die pad has a generally quadrangular configuration defining four corner regions;
at least four tie bars are integrally connected to and extend diagonally from respective ones of four corner regions of the die pad; and
the inner and outer leads are segregated into at least four sets that each extend along a respective one of the peripheral edge segments of the die pad between an adjacent pair of the tie bars.
6. The semiconductor package of claim 5, wherein:
the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;
the second inner lead regions of an adjacent central pair of the inner leads of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad are each of a second length that is less than the first length; and
the second inner lead regions of the inner leads of each set that extend between the outermost and central pairs each gradually decrease from the first length to the second length.
7. The semiconductor package of claim 5, wherein:
the second inner lead regions of two outermost groups of the inner leads of each set are of gradually decreasing length; and
the second inner lead regions of the inner leads of each set that are disposed between the outermost groups are of substantially equal length.
8. The semiconductor package of claim 7, wherein the downsets of the inner leads included in each of the two outermost groups of each set are substantially linearly aligned with the downset of the tie bar disposed closest thereto.
9. The semiconductor package of claim 5, wherein:
the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;
the second inner lead region of a central inner lead of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad is of a second length that is less than the first length; and
the second inner lead regions of the inner leads of each set that extend between the outermost pair and the central inner lead each gradually decrease from the first length to the second length.
10. The semiconductor package of claim 9, wherein the downset of the central inner lead of each set has an angled configuration.
11. The semiconductor package of claim 9, wherein the downset of the central inner lead of each set, and the downsets of two of the inner leads disposed adjacent thereto and extending along respective ones of opposed sides thereof, are each substantially parallel to the adjacent, corresponding peripheral edge segment of the die pad.
12. The semiconductor package of claim 4, wherein the first tie bar region of the tie bar is longer than the second tie bar region thereof.
13. The semiconductor package of claim 1 further comprising a second semiconductor die stacked upon the semiconductor die and electrically connected to at least one of the inner leads.
14. The semiconductor package of claim 13 further comprising a spacer interposed between the semiconductor die and the second semiconductor die.
15. A semiconductor package comprising:
a die pad defining multiple peripheral edge segments;
a plurality of inner leads that each include a downset formed therein, each of the inner leads defines first and second inner lead regions that are separated by the downset therein, the first inner lead region of each of the inner leads being disposed between the downset and the die pad and being longer than the second inner lead region thereof;
a plurality of tie bars integrally connected to and extending from the die pad, each of the tie bars defining first and second tie bar regions that are separated by a downset therein, the first tie bar region of each of the tie bars being disposed between the downset and the die pad and being longer than the second tie bar region thereof, the first inner lead regions being segregated into at least two sets that each extend along a respective one of at least two peripheral edge segments of the die pad and between an adjacent pair of the tie bars, wherein the second inner lead regions of the inner leads of each set thereof are of gradually decreasing length as the inner leads advance toward the center of an adjacent, corresponding peripheral edge segment of the die pad;
at least one semiconductor die attached to the die pad and electrically connected to the first inner lead region of at least one of the inner leads; and
a package body defining a peripheral side surface, the package body at least partially encapsulating the die pad, the inner leads, the tie bars and the semiconductor die such that the downsets of the inner leads and the tie bars are covered by the package body.
16. The semiconductor package of claim 15, wherein:
the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;
the second inner lead regions of an adjacent central pair of the inner leads of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad are each of a second length that is less than the first length; and
the second inner lead regions of the inner leads of each set that extend between the outermost and central pairs each gradually decrease from the first length to the second length.
17. The semiconductor package of claim 15, wherein:
the second inner lead regions of two outermost groups of the inner leads of each set are of gradually decreasing length; and
the second inner lead regions of the inner leads of each set that are disposed between the outermost groups are of substantially equal length.
18. A semiconductor package comprising:
a die pad;
a plurality of inner leads that each include a downset formed therein, each of the inner leads defines first and second inner lead regions that are separated by the downset therein, the first inner lead region of each of the inner leads being disposed between the downset and the die pad and being longer than the second inner lead region thereof;
a plurality of tie bars integrally connected to and extending from the die pad, each of the tie bars defining first and second tie bar regions that are separated by a downset therein, the first tie bar region of each of the tie bars being disposed between the downset and the die pad and being longer than the second tie bar region thereof, wherein the inner leads are segregated into multiple sets, and the second inner lead regions of the inner leads of each set thereof are of gradually decreasing length as the inner leads advance toward the center of an adjacent, corresponding peripheral edge segment of the die pad;
at least one semiconductor die attached to the die pad and electrically connected to the first inner lead region of at least one of the inner leads; and
a package body defining a peripheral side surface, the package body at least partially encapsulating the die pad, the inner leads, the tie bars and the semiconductor die such that the downsets of the inner leads and the tie bars are covered by the package body, wherein the downsets within the tie bar and the inner leads being sized and oriented relative to each other to minimize the separation between the inner leads and the die pad.
19. The semiconductor package of claim 18, wherein:
the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;
the second inner lead regions of an adjacent central pair of the inner leads of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad are each of a second length that is less than the first length; and
the second inner lead regions of the inner leads of each set that extend between the outermost and central pairs each gradually decrease from the first length to the second length.
20. The semiconductor package of claim 18, wherein:
the second inner lead regions of two outermost groups of the inner leads of each set are of gradually decreasing length; and
the second inner regions of the inner leads of each set that are disposed between the outermost groups are of substantially equal length.
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US20140048920A1 (en) * 2012-05-02 2014-02-20 Texas Instruments Incorporated Selective Leadframe Planishing
US20150325506A1 (en) * 2012-03-23 2015-11-12 Renesas Electronics Corporation Semiconductor device and a manufacturing method thereof

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