KR100220154B1 - Method manufacture of semiconductor package - Google Patents

Method manufacture of semiconductor package Download PDF

Info

Publication number
KR100220154B1
KR100220154B1 KR1019960009774A KR19960009774A KR100220154B1 KR 100220154 B1 KR100220154 B1 KR 100220154B1 KR 1019960009774 A KR1019960009774 A KR 1019960009774A KR 19960009774 A KR19960009774 A KR 19960009774A KR 100220154 B1 KR100220154 B1 KR 100220154B1
Authority
KR
South Korea
Prior art keywords
lead
semiconductor chip
package
molding
semiconductor
Prior art date
Application number
KR1019960009774A
Other languages
Korean (ko)
Other versions
KR970072358A (en
Inventor
허영욱
Original Assignee
김규현
아남반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김규현, 아남반도체주식회사 filed Critical 김규현
Priority to KR1019960009774A priority Critical patent/KR100220154B1/en
Publication of KR970072358A publication Critical patent/KR970072358A/en
Application granted granted Critical
Publication of KR100220154B1 publication Critical patent/KR100220154B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 반도체패키지의 제조방법 및 구조에 관한 것으로, 반도체칩의 저면을 외부로 노출시켜 회로동작시 발생되는 열방출의 효과를 극대화하여 패키지의 수명을 연장시키고, 신뢰성을 향상 시킴은 물론, 패키지의 몰딩부 외측에 위치한 리드는 절단하고, 몰딩부 내측에 위치한 리드는 그 저면을 외부로 노출시켜 마더보드에 실장시 리드의 저면에서 신호전달을 하도록 함으로서 실장면적을 최소화 할 수 있는 반도체패키지이다.The present invention relates to a manufacturing method and structure of a semiconductor package, by exposing the bottom surface of the semiconductor chip to the outside to maximize the effect of heat dissipation generated during circuit operation to extend the life of the package, improve the reliability, as well as the package The lead located outside the molding part of the cut is cut, the lead located inside the molding part is a semiconductor package that can minimize the mounting area by exposing the bottom surface to the outside to transmit a signal from the bottom of the lead when mounted on the motherboard.

Description

반도체패키지의 제조방법Manufacturing method of semiconductor package

제 1 도는 일반적인 반도체패키지의 구조를 보인 단면도1 is a cross-sectional view showing the structure of a general semiconductor package

제 2 도는 본 발명에 적용되는 리드프레임을 도시한 평면도2 is a plan view showing a lead frame applied to the present invention

제 3a 도 내지 제 3e 도는 본 발명의 제조 공정도3a to 3e is a manufacturing process diagram of the present invention

제 4a 도 내지 제 4d 도는 본 발명의 실시예에 의한 제조 공정도4a to 4d is a manufacturing process diagram according to an embodiment of the present invention

제 5 도는 본 발명에 의한 반도체패키지의 저면도5 is a bottom view of a semiconductor package according to the present invention.

제 6 도는 본 발명의 리드를 도시한 확대도6 is an enlarged view showing the lid of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 반도체칩 20 : 리드프레임10: semiconductor chip 20: lead frame

21 : 리드 30 : 와이어21: lead 30: wire

41 : 액상봉지재 42 : 컴파운드41: liquid encapsulant 42: compound

본 발명은 반도체패키지의 제조방법에 관한 것으로, 더욱 상세하게는 반도체칩의 저면을 외부로 노출시켜 회로동작시 발생되는 열방출의 효과를 극대화하여 패키지의 수명을 연장시키고, 신뢰성을 향상시킴은 물론, 패키지의 몰딩부 외측에 위치한 리드는 절단하고, 몰딩부 내측에 위치한 리드는 그 저면을 외부로 노출시켜 마더보드에 실장시 리드의 저면에서 신호전달을 하도록 함으로서 실장면적을 최소화 할 수 있는 반도체패키지의 제조방법에 관한것이다. 일반적으로 반도체패키지는 제 1 도에 도시된 바와 같이, 리드프레임의 칩탑재판(2a)상에 에폭시 어드히시브(Epoxy Adhesive)를 도포하여 반도체칩(1)올 접착시키고, 반도체칩(1)상의 칩패드와 리드프레임의 리드(2)를 와이어(3)로 본딩한 후, 컴파운드(4)로 몰딩하여 반도체패키지를 제조하였다. 그러나, 이러한 구조는 컴파운드(4) 외부로 리드(2)를 노출시켜 소정의 형태로 리드(2)를 절곡하여 입출력 단자로 사용하있으므로, 외부로 노출된 리드(2)에 충격이 가해져 쉽게 변형되는 이유로 유지 관리가 어려우며 패키지의 크기를 크게 만드는 요인이 되었다. 또한, 반도체칩(1)을 리드프레임의 칩탑재판(2a)에 접착시킬때 에폭시 어드히시브를 사용하기 때문에 에폭시와 반도체칩(1)의 인터페이스(Interface)부분에서 계면박리 및 크랙(Crack)을 발생시키는 요인이 되었던 것이다. 뿐만 아니라, 반도체칩(1)이 컴파운드(4)의 내부에 위치하기 때문에 열방출이 되지 않아 패키지의 수명을 단축시키는 등의 문제점이 있었던 것이다. 따라서, 본 발명은 이러한 문제점을 해소하기 위하여 발명된 것으로, 칩탑재판이 구비되지 않은 리드프레임으로 패키지를 제조함으로서 반도체칩과 칩탑체판과의 계면박리 및 불량을 방지하고, 패키지의 신뢰성을 향상 시킬수 있도록 된 반도체패키지 제조방법을 제공함에 그 목적이 있다. 이러한 본 발명의 목적을 달성하기 위해서는 다수의 리드가 형성되고, 상기 다수의 리드 중앙부에는 칩탑재판이 없는 리드프레임을 형성하는 단계와; 상기 리드프레임의 다수의 리드 중앙부에 반도체칩을 위치시켜 와이어본딩을 실시하는 단계와; 상기 와이어본딩된 리드, 반도체칩 및 와이어를 외부의 산화 및 부식으로 부터 보호하기 위하여 몰딩하는 단계와; 상기 단계후에 몰딩영역 외각에 위치한 리드를 절단하는 단계로 이루어 진 것을 특징으로하는 반도체패키지의 제조방법에 의해 가능하다. 이하, 본 발명을 첨부도면을 참조하여 상세히 설명하면 다음과 같다. 제 2 도는 본 발명에 사용되는 리드프레임을 도시한 평면도로서, 본 발명의 리드프레임(20)에는 반도체칩(10)이 부착되는 칩탑재판이 형성되어 있지 않은 것을 알 수 있다. 제 3a 도 내지 제 3e 도는 본 발명의 제조 공정을 나타낸 도면으로서, 제 3a 도는 칩탑재판이 없는 리드프레임(20)에 기존의 다이본딩시 반도체칩(10)이 위치되는 부분, 즉 다수의 리드(21) 중앙부에 반도체칩(10)을 위치시킨 상태를 도시한 것이고, 제 3b 도는 이와같이 반도체칩(10)이 다수의 리드(21)의 중앙부에 위치된 상태에서 와이어(30) 본딩을 실시한 상태를 도시한 것이다. 이때, 상기 반도체칩(10)은 제 7 도에 도시된 바와 같이 히터블럭(H)의 상부에 안착되는데, 이 히터블럭(H)에는 배큠 홀(V : Vacuum Hole)이 형성되고, 상기 배큠 홀(V)로 공기를 빨아들여 반도체칩(10)을 고정 지지함으로서 와이어 본딩 중에 반도체칩(10)이 혼들림을 방지하는 것이다.The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to expose the bottom surface of the semiconductor chip to the outside to maximize the effect of heat dissipation generated during circuit operation to extend the life of the package, improve reliability as well as The lead is located outside the molded part of the package, and the lead located inside the molded part is exposed to the outside to allow signal transmission from the bottom of the lead when mounted on the motherboard, thereby minimizing the mounting area. It relates to a method of manufacturing. In general, as shown in FIG. 1, the semiconductor package is coated with an epoxy adhesive on the chip mounting plate 2a of the lead frame to bond the semiconductor chip 1 to the semiconductor chip 1, The chip pad and the lead 2 of the lead frame were bonded to the wire 3, and then molded into the compound 4 to manufacture a semiconductor package. However, this structure exposes the leads 2 to the outside of the compound 4, so that the leads 2 are bent and used as input / output terminals in a predetermined form, so that the leads 2 exposed to the outside are easily impacted and deformed. This makes it difficult to maintain and makes the package larger. In addition, since the epoxy adsorb is used to bond the semiconductor chip 1 to the chip mounting plate 2a of the lead frame, the interface peeling and cracking are performed at the interface of the epoxy and the semiconductor chip 1. It was a factor that caused the. In addition, since the semiconductor chip 1 is located inside the compound 4, heat dissipation does not occur, thereby reducing the life of the package. Therefore, the present invention was invented to solve this problem, and by manufacturing a package with a lead frame that is not provided with a chip mounting plate to prevent the interface peeling and defects between the semiconductor chip and the chip top plate, to improve the reliability of the package The purpose is to provide a method for manufacturing a semiconductor package. In order to achieve the object of the present invention, a plurality of leads are formed, and forming a lead frame without a chip mounting plate in the plurality of lead centers; Placing a semiconductor chip in a plurality of lead centers of the lead frame to perform wire bonding; Molding the wire bonded leads, semiconductor chips and wires to protect against external oxidation and corrosion; After the step is possible by the method of manufacturing a semiconductor package, characterized in that the step consisting of cutting the lead located on the outer surface of the molding region. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 2 is a plan view showing a lead frame used in the present invention, and it can be seen that the chip mounting plate to which the semiconductor chip 10 is attached is not formed in the lead frame 20 of the present invention. 3A to 3E are views illustrating a manufacturing process of the present invention, and FIG. 3A is a portion in which a semiconductor chip 10 is positioned when a die is conventionally bonded to a lead frame 20 without a chip mounting plate, that is, a plurality of leads ( 21) shows a state in which the semiconductor chip 10 is placed in the center portion, and FIG. 3b shows a state in which the semiconductor chip 10 is bonded in the state where the semiconductor chip 10 is positioned in the center portion of the plurality of leads 21. It is shown. At this time, the semiconductor chip 10 is seated on the heater block (H) as shown in Figure 7, the heater block (H) has a vacuum hole (V: vacuum hole) is formed, the vacuum hole The semiconductor chip 10 is prevented from being mixed during wire bonding by sucking the air at (V) to fix and support the semiconductor chip 10.

이와 같이 리드프레임과 반도체칩이 와이어 본딩되면, 상기 리드프레임(20)을 운반 및 취급시에는 상기 반도체칩과 리드프레임이 와이어 본딩에 의해 서로 연결되어 있으므로 반도체칩(10)이 분리되지 않는 것이다. 제 3c 도와 제 3d 도는 와이어 본딩된 리드프레임(20)에 몰딩을 실시하여 반도체칩(10)을 외부의 산화 및 부석으로 부터 보호하는 것으로, 여기서는 액상 봉지재(41)를 사용하여 본딩한 상태를 도시한 것이다. 이때, 상기 액상 봉지재(41)가 흘러 넘치는 것을 방지하기 위하여 몰딩영역에 미리 댐(411)을 형성한 후, 액상 봉지재(41)로 몰딩을 실시하면 액상 봉지재(41)가 흘러 넘치는 것을 방지할 수 있다. 이와 같이 몰딩을 실시한 다음에는 150℃ 이상의 고온에서 수시간 노출시켜 액상 봉지재(41)를 경화시키고, 제 3e 도와 같이 몰딩영역의 외부에 위치된 리드(21)를 절단하여 반도체패키지를 완성하는 것이다. 상기 제조 공정중 몰딩을 실시할때 액상 봉지재(41)를 사용하지 않고, 액폭시 몰드 컴파운드(42)를 사용하여 제 4a 도 내지 제 4d 도에 도시된 바와같이 몰딩을 실시할 수 있는 바, 컴파운드(42)를 사용하여 몰딩을 실시할 겅우에는 몰드금형이 필요하게 되고, 몰딩잉역의 외곽으로 댐(411)을 형성할 필요는 없다. 이때에도 몰드 컴파운드(42)로 몰딩공정과 경화공정을 거친 후, 몰딩영역의 외각으로 돌출된 리드(21)를 절단하는 것이다. 이와 같은 제조공정을 거쳐 완성된 반도체패키지는 제 5 도에 도시된 바와 같이 저면에 반도체칩(10)과 다수의 리드(21)가 노출된 상태로 형성되는 것이로, 반도체칩(10)의 저면이 외부로 직접 노출되기 때문에 열방출이 우수하며, 다이본딩 공정을 거치지 않음으로서 계면박리가 발생되지 않는 것이다. 또한, 이와 같은 반도체패키지는 몰딩영역의 외각으로 위치되는 리드(21)가 없어 취급시 리드(21)가 휘거나, 손상되는 것을 방지할수 있으며, 패키지의 터미널(입출력단자) 부분이 패키지의 밑면에서 이루어짐으로 마더보드에 실장시 그 크기를 최소화 할 수 있는 것이다. 또한, 상기 반도체패키지의 저변에는 그라인드(Grind)을 실시하여 패키지의 저면에서 발생할 수 있는 플래쉬(Flash)를 제거할 수 있다. 즉, 몰딩 후에 플래쉬(몰드 찌거기)를 제거하는 플래쉬 제거단계를 추가할 수 있다. 또한, 제 6 도와 같이 본발명의 반도체패키지는 몰딩영역 외각에 위치한 리드(21)를 절단시 리드(21)의 절단을 용이하게 하기 위하여 절단되는 부위의 리드(21)에 노치(211 : Notch)를 형성할 수 있다. 이와 같은 제조방법에 의해 형성된 반도체패키지의 구조는, 저면이 외부로 직접 노출되는 반도체칩(10)과, 상기 반도체칩(10)의 외측에 위치되고 몰딩영역을 벗어나지 않으며 저변이 외부로 노출되어 저면에서 신호의 입출력이 이루어지는 다수의 리드(21)와, 상기 반도체칩(10)과 리드(21)를 연결시켜주는 와이어와, 상기 반도체칩(10), 리드(21) 및 와이어(30)를 외부 환경으로부터 보호하기 위하여 몰딩된 액상 봉지재(41) 또는 컴파운드(42)로 구성된 것이다.When the lead frame and the semiconductor chip are wire bonded as described above, the semiconductor chip 10 is not separated when the lead frame 20 is transported and handled since the semiconductor chip and the lead frame are connected to each other by wire bonding. The 3C and 3D wire-bonded lead frame 20 is molded to protect the semiconductor chip 10 from external oxidation and pumice. In this case, the bonded state using the liquid encapsulant 41 is shown. It is shown. In this case, in order to prevent the liquid encapsulant 41 from flowing out, the dam 411 is formed in advance in the molding region, and then the liquid encapsulant 41 flows when the liquid encapsulant 41 is molded. You can prevent it. After molding as described above, the liquid encapsulant 41 is cured by exposing at a high temperature of 150 ° C. or more for several hours, and the semiconductor package is completed by cutting the leads 21 positioned outside the molding region as shown in FIG. . When molding during the manufacturing process, it is possible to perform molding as shown in FIGS. 4A to 4D without using the liquid encapsulant 41 and using the epoxy mold compound 42. When molding is performed using the compound 42, a mold mold is required, and it is not necessary to form the dam 411 outside the molding area. In this case, after the molding process and the curing process are performed with the mold compound 42, the lead 21 protruding to the outer surface of the molding region is cut. As shown in FIG. 5, the semiconductor package completed through the manufacturing process is formed with the semiconductor chip 10 and the plurality of leads 21 exposed on the bottom, and the bottom surface of the semiconductor chip 10. Since heat is directly exposed to the outside, heat dissipation is excellent and interfacial peeling does not occur by not undergoing a die bonding process. In addition, since the semiconductor package does not have a lead 21 positioned outside the molding region, the lead 21 can be prevented from being bent or damaged during handling, and the terminal (input / output terminal) portion of the package is formed at the bottom of the package. It is possible to minimize the size when mounted on the motherboard. In addition, the bottom of the semiconductor package may be ground to remove flash, which may occur on the bottom of the package. That is, a flash removing step of removing the flash (molding residue) after molding may be added. In addition, as shown in FIG. 6, the semiconductor package of the present invention has a notch 211 (notch) in the lead 21 of the cut portion to facilitate the cutting of the lead 21 when cutting the lead 21 located outside the molding region. Can be formed. The structure of the semiconductor package formed by such a manufacturing method includes a semiconductor chip 10 having a bottom surface directly exposed to the outside, and a bottom surface of which is located outside the semiconductor chip 10 and does not leave the molding region and is exposed to the outside. A plurality of leads 21 for inputting and outputting signals, wires connecting the semiconductor chip 10 and the leads 21, and the semiconductor chip 10, the leads 21, and the wire 30 are externally connected. It is composed of a molded liquid encapsulant 41 or compound 42 to protect from the environment.

여시서, 상기 액상 봉지재(41)로 몰딩할 경우에는 액상 봉지재(41)가 흘러 넘치는 것을 방지하기 위하여 몰딩영역의 외각으로 댐(411)을 형성한다. 또한, 상기 몰딩된 액상 봉지재(41) 및 컴파운드(42)는 리드(21) 및 반도체칩(10)의 상부로만 몰딩되는 것이며, 상기 반도체패키지의 저면에는 플래쉬(Flash)의 제거를 위해 그라인드(Grind)를 실시할 수 있다. 이와 같은 구성의 반도체패키지는 저면으로 반도체칩과 다수의 리드가 직접 노출되므로 열방출이 우수하며 계면박리가 발생되지 않고, 몰딩영역의 외각으로 위치되는 리드가 없어 취급시 리드가 휘거나, 손상되는 것을 방지할수 있으며, 패키지의 터미널(입출력단자) 부분이 패키지의 밑면에서 이루어짐으로 마더보드에 실장시 그 크기를 최소화 할 수 있는 잇점이 있다.In this case, in the case of molding with the liquid encapsulant 41, a dam 411 is formed at an outer side of the molding region to prevent the liquid encapsulant 41 from flowing out. In addition, the molded liquid encapsulant 41 and the compound 42 are molded only to the upper portion of the lead 21 and the semiconductor chip 10, and the bottom of the semiconductor package is ground (grind) to remove the flash (Flash) Grind) can be performed. Since the semiconductor package of the above structure is directly exposed to the bottom surface of the semiconductor chip and a number of leads, the heat dissipation is excellent and no interfacial peeling occurs. The terminal (input and output terminals) of the package is made at the bottom of the package, which has the advantage of minimizing its size when mounted on the motherboard.

Claims (3)

(정정) 다수의 리드가 형성되고, 이 다수의 리드 중앙부에는 칩탑재판이 없는 리드프레임을 제공하는 단계와; 상기 리드프레임의 다수의 리드중앙부에 반도체칩을 위치시키되, 상기 반도체칩은 배큠 홀(VacuumHole)이 형성된 히터블럭에 안착시킨 후, 상기 배큠 홀로 공기를 빨아들여서 반도체칩을 지지 고정한 상태에서 와이어본딩을 실시하는 단계와; 상기 와이어본딩된 리드, 반도체칩 및 와이어를 외부의 산화 및 부식으로 부터 보호하기 위하여 몰딩하는 단계와; 상기 단계후에 몰딩영역 외각에 위치한 리드를 절단하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체패키지의 제조방법.(Correction) providing a plurality of leads, the lead frame having no chip mounting plate in the plurality of lead centers; A semiconductor chip is placed in a plurality of lead centers of the lead frame, and the semiconductor chip is seated on a heater block in which a vacuum hole is formed, and the wire bonding is performed while sucking air into the vacuum hole to support the semiconductor chip. Performing; Molding the wire bonded leads, semiconductor chips and wires to protect against external oxidation and corrosion; And cutting the lead located outside the molding region after the step. 제 1 항에 있어서, 상기 몰딩하는 단계 후에는 반도체 패키지의 저면에 그라인드(Grind)를 설치하여 플래쉬(Flash)를 제거하는 플레쉬 제거 단계를 더 포함하여서 이루어진 것을 특징으로 하는 반도체패키지의 제조방법.The method of claim 1, further comprising: removing a flash by removing a flash by installing a grind on a bottom surface of the semiconductor package after the molding. 제 1 항에 있어서, 상기 몰딩영역의 외각에 위치한 리드를 절단하는 단계는, 상기 리드의 절단되는 부위에 노치(Notch)를 형성하여 상기리드가 용이하게 절단되도록 한 것을 특징으로 하는 반도체패키지의 제조방법.The method of claim 1, wherein the cutting of the lead located at the outer surface of the molding region comprises forming a notch in the cut portion of the lead so that the lead is easily cut. Way.
KR1019960009774A 1996-04-01 1996-04-01 Method manufacture of semiconductor package KR100220154B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009774A KR100220154B1 (en) 1996-04-01 1996-04-01 Method manufacture of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009774A KR100220154B1 (en) 1996-04-01 1996-04-01 Method manufacture of semiconductor package

Publications (2)

Publication Number Publication Date
KR970072358A KR970072358A (en) 1997-11-07
KR100220154B1 true KR100220154B1 (en) 1999-09-01

Family

ID=19454812

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960009774A KR100220154B1 (en) 1996-04-01 1996-04-01 Method manufacture of semiconductor package

Country Status (1)

Country Link
KR (1) KR100220154B1 (en)

Cited By (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US7932595B1 (en) 2002-11-08 2011-04-26 Amkor Technology, Inc. Electronic component package comprising fan-out traces
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8154111B2 (en) 1999-12-16 2012-04-10 Amkor Technology, Inc. Near chip size semiconductor package
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8304866B1 (en) 2007-07-10 2012-11-06 Amkor Technology, Inc. Fusion quad flat semiconductor package
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8410585B2 (en) 2000-04-27 2013-04-02 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
KR20020058209A (en) 2000-12-29 2002-07-12 마이클 디. 오브라이언 Semiconductor package
KR100731007B1 (en) 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 stack-type semiconductor package
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
KR100393448B1 (en) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure

Cited By (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853836B1 (en) 1998-06-24 2014-10-07 Amkor Technology, Inc. Integrated circuit package and method of making the same
US9224676B1 (en) 1998-06-24 2015-12-29 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8963301B1 (en) 1998-06-24 2015-02-24 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8154111B2 (en) 1999-12-16 2012-04-10 Amkor Technology, Inc. Near chip size semiconductor package
US8410585B2 (en) 2000-04-27 2013-04-02 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US8102037B2 (en) 2001-03-27 2012-01-24 Amkor Technology, Inc. Leadframe for semiconductor package
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US8298866B1 (en) 2002-11-08 2012-10-30 Amkor Technology, Inc. Wafer level package and fabrication method
US8119455B1 (en) 2002-11-08 2012-02-21 Amkor Technology, Inc. Wafer level package fabrication method
US8710649B1 (en) 2002-11-08 2014-04-29 Amkor Technology, Inc. Wafer level package and fabrication method
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US10665567B1 (en) 2002-11-08 2020-05-26 Amkor Technology, Inc. Wafer level package and fabrication method
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US7932595B1 (en) 2002-11-08 2011-04-26 Amkor Technology, Inc. Electronic component package comprising fan-out traces
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US8501543B1 (en) 2002-11-08 2013-08-06 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US8441110B1 (en) 2006-06-21 2013-05-14 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US8089141B1 (en) 2006-12-27 2012-01-03 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US8304866B1 (en) 2007-07-10 2012-11-06 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7872343B1 (en) 2007-08-07 2011-01-18 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8283767B1 (en) 2007-08-07 2012-10-09 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8319338B1 (en) 2007-10-01 2012-11-27 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US8227921B1 (en) 2007-10-03 2012-07-24 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US8729710B1 (en) 2008-01-16 2014-05-20 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7906855B1 (en) 2008-01-21 2011-03-15 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8084868B1 (en) 2008-04-17 2011-12-27 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8299602B1 (en) 2008-09-30 2012-10-30 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US8432023B1 (en) 2008-10-06 2013-04-30 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8823152B1 (en) 2008-10-27 2014-09-02 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US8188579B1 (en) 2008-11-21 2012-05-29 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via
US11869829B2 (en) 2009-01-05 2024-01-09 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device with through-mold via
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8558365B1 (en) 2009-01-09 2013-10-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8729682B1 (en) 2009-03-04 2014-05-20 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US10546833B2 (en) 2009-12-07 2020-01-28 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US9324614B1 (en) 2010-04-06 2016-04-26 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US9159672B1 (en) 2010-08-02 2015-10-13 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8900995B1 (en) 2010-10-05 2014-12-02 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US9275939B1 (en) 2011-01-27 2016-03-01 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9508631B1 (en) 2011-01-27 2016-11-29 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US9431323B1 (en) 2011-11-29 2016-08-30 Amkor Technology, Inc. Conductive pad on protruding through electrode
US11043458B2 (en) 2011-11-29 2021-06-22 Amkor Technology Singapore Holding Pte. Ltd. Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US10410967B1 (en) 2011-11-29 2019-09-10 Amkor Technology, Inc. Electronic device comprising a conductive pad on a protruding-through electrode
US8981572B1 (en) 2011-11-29 2015-03-17 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10014240B1 (en) 2012-03-29 2018-07-03 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9543235B2 (en) 2013-10-24 2017-01-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method

Also Published As

Publication number Publication date
KR970072358A (en) 1997-11-07

Similar Documents

Publication Publication Date Title
KR100220154B1 (en) Method manufacture of semiconductor package
KR100859624B1 (en) A method of manufacturing a semiconductor de?ice
US20020119603A1 (en) Semiconductor device and method of manufacturing same
EP0623956A2 (en) A semiconductor device having no die supporting surface and method for making the same
US20050184404A1 (en) Photosensitive semiconductor package with support member and method for fabricating the same
US5583371A (en) Resin-sealed semiconductor device capable of improving in heat radiation characteristics of resin-sealed semiconductor elements
JP2010153726A (en) Manufacturing method for semiconductor device, and semiconductor device
JP2000058711A (en) Semiconductor package with bga structure of csp
JPH09199637A (en) Resin sealing type semiconductor device and its manufacture
JPH05226564A (en) Semiconductor device
JPH05299530A (en) Resin sealed semiconductor device and manufacturing mehtod thereof
US6091135A (en) Lead frame with pre-mold paddle for a semiconductor chip package
KR20020093250A (en) ELP type leadframe and ELP using the same
KR100279252B1 (en) Ceramic Package
KR100198312B1 (en) Structure of lead frame and package
KR100197876B1 (en) Semiconductor package and method of manufacturing the same
JPH06132443A (en) Semiconductor device and lead frame used for manufacture thereof
JPH0637221A (en) Resin sealing type semiconductor device
KR200155169Y1 (en) Semiconductor package device
KR100348862B1 (en) Method for fabricating Semiconductor package
KR100233860B1 (en) Semiconductor package and method for manufacture of the same
US5905300A (en) Reinforced leadframe to substrate attachment
KR200152650Y1 (en) Semiconductor package
JPH1168034A (en) Semiconductor device
KR20010087444A (en) Stacked buttom leaded plastic package and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130613

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20140612

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20150611

Year of fee payment: 17

EXPY Expiration of term