KR20020049944A - semiconductor package and method for fabricating the same - Google Patents

semiconductor package and method for fabricating the same Download PDF

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Publication number
KR20020049944A
KR20020049944A KR1020000079272A KR20000079272A KR20020049944A KR 20020049944 A KR20020049944 A KR 20020049944A KR 1020000079272 A KR1020000079272 A KR 1020000079272A KR 20000079272 A KR20000079272 A KR 20000079272A KR 20020049944 A KR20020049944 A KR 20020049944A
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South Korea
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chip
semiconductor package
wire
die paddle
circuit board
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KR1020000079272A
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Korean (ko)
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송주성
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000079272A priority Critical patent/KR20020049944A/en
Publication of KR20020049944A publication Critical patent/KR20020049944A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE: A semiconductor package is provided to simplify a fabricating process and to guarantee reliability in a board level, by supplying a new type of a semiconductor package in which a circuit board is attached to a lead frame. CONSTITUTION: A chip(1) is settled in a die paddle(4). Leads(5) are disposed near the die paddle. The circuit board(2) is attached to the upper surface of the leads, including a window for exposing the die paddle, a bond finger(8) for wire bonding and a via hole for an electrical connection with the leads. A wire(6) electrically connects a bonding pad of the chip with the bond finger of the circuit board. A mold body(7) encapsulates the chip, the wire and the bond finger.

Description

반도체 패키지 및 그 제조방법{semiconductor package and method for fabricating the same} A semiconductor package and its manufacturing method {semiconductor package and method for fabricating the same}

본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 회로기판과 리드프레임을 접목시킨 형태의 기판으로써 공정의 단순화를 도모함과 더불어 보드 레벨의 신뢰성을 확보할 수 있는 새로운 구조의 반도체 패키지를 제공하기 위한 것이다. The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly, to a semiconductor package having a novel structure capable of ensuring the reliability of the board-level with domoham simplification of the process by the form of the substrate that combine the circuit board and the lead frame It intended to provide.

일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다. Generally, in the semiconductor industry, packaging technology for integrated circuits have been developed until now in order to meet the needs for miniaturization and mounting reliability.

즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다. In other words, demand for miniaturization is accelerating the development of the adjacent packages in a chip scale, the need for mounting reliability is highlighted the importance of the package manufacturing technology that can improve the mechanical and electrical reliability after efficiency and the mounting of the mounting operation there was.

한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다. On the other hand, in general, a semiconductor device, after each of the individually separated chip in a wafer state the integrated circuit is formed, is subjected to a packaging step of assembling this mounted in a plastic package or a ceramic package, to facilitate the mounting of the substrate.

이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다. Thus the main purpose of the packaging process is performed for the semiconductor device can be said to ensure the protection function of the shape for mounting on a circuit board or socket.

또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다. In addition, recently, according to high integration of integrated circuit pinhwa, microfabrication technology, and it is greatly changed in accordance with the art related to the degree of three minutes each type screen or the like, the assembly process of a package according to a diversity of packaging types.

반도체 조립공정의 개요에 대해 현재 가장 많이 사용되고 있는 플라스틱 타입의 반도체소자를 예로 들어 설명하면 다음과 같다. It will be described for a semiconductor device of a plastic-type that is currently most widely used for the outline of the semiconductor assembly process for example as follows.

먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일 칩으로 분리하는데, 이때 Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라 브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다. First, to separate the wafer electrical circuit formed in each of the single chip, wherein the Si (silicon) is because it has a hard and fragile properties as a Mohs hardness of 7 and placed it the material for cutting in the line to be pre-separated in the production of wafers along the division line is applied to the brake stress often takes a process for fracture separation.

또한, 분리된 각각의 반도체 칩은 리드프레임의 다이패들에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다. In addition, each of the semiconductor chips separated is bonded to the die paddle of the lead frame, the bonding method of this case is such as Au-Si process (共 晶) method, a soldering method, a resin adhesion method, select the appropriate method depending on the application It is used.

한편, 전술한 바와 같이 반도체 칩을 리드프레임의 다이패들에 접착하는 목적은 조립이 완료된 후 기판에 실장시키기 위해서 뿐만 아니라, 전기적 입출력단자나 어스(earth)를 겸하는 일도 있으며 소자의 동작시 발생하는 열의 방열통로로서도 필요로 하는 경우가 있기 때문이다. On the other hand, for bonding a semiconductor chip to the die paddle of the lead frame as described above, the purpose is not only in order to mount on the substrate after the assembly is completed, the work serving as an electric input and output terminals, a ground (earth), and that occur during the device operation, is because if needed also as a heat dissipation path of heat.

상기와 같이 반도체 칩을 본딩한 후에는 칩의 본딩패드와 리드프레임의 인너리드를 와이어로 본딩하므로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 패키지에서는 일반적으로 골드 와이어를 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다. After bonding the semiconductor chip as described above is connected By bonding the inner lead bonding pads and the lead frame of the chip by a wire, in the plastic sealed package by the wire bonding method generally thermocompression bonding using a gold wire method or a thermocompression the method for mixing method and the ultrasonic method is mainly used.

또한, 와이어 본딩에 의해 반도체 칩과 인너리드가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합하므로써 몰드바디를 형성시키는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다. Further, after a wire-bonding the semiconductor chip and the inner lead electrically connected to the there is a molding process for forming a molded body performing By molding seal the chip by using high-purity epoxy resin, wherein the epoxy resin used is the reliability of the integrated circuit is an important factor influencing the, there is a propulsion improving such low stress screen for reducing the stress given to the high purity and the molding of the resin when the integrated circuit.

그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판에 실장하기 위해 아웃터리드(outer lead)를 소정의 형상으로 절단하고 성형하는 공정이 행해지며, 아웃터리드에는 실장접합성(납땜성)을 향상시키기 위해 도금이나 납딥(dip)이 처리된다. Then, after the above process is completed, a process of the outer leads (outer lead) cutting and shaping to a predetermined shape to mount the IC package to the socket or the substrate used which outer leads reinforce the mounting bonding properties (solderability) the plating or napdip (dip) is treated to.

한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로서는 전술한 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지( Ball Grid Array package), BLP(Bottom Leaded Package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다. On the other hand, the semiconductor package is divided into several types according to the mounting type and lead type, typical examples of the package above a DIP (Dual Inline Package) in addition to QFP (Quad Flat Package), (Thin Small Outline Package) TSOP, BGA package (Ball etc. Grid Array package), Bottom Leaded Package (BLP), and continues Chemistry dapin (多 -pin) screen or frivolous chancel (輕薄 短小).

상기한 패키지 타입중, BGA 패키지(Ball Grid Array package)는 반도체 칩이부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여 아웃터리드(outer lead) 대신으로 사용하게 되며, 상기 BGA 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있으며, QFP와는 달리 리드의 변형이 없는 장점이 있다. Of the one package type, BGA package (Ball Grid Array package) is to the arrangement (Array) of spherical solder balls of the rear surface of the semiconductor chip mounting substrate with a predetermined condition used in place of the outer leads (outer lead), the BGA package can be a package body (package body) area smaller than the QFP (Quad Flat package) type, there is an advantage without deformation of the lid unlike the QFP.

대신, 상기 BGA 패키지는 기존의 리드프레임에 비해 값이 비싼 회로기판을 사용하므로 제조원가가 높아지고, 반도체 칩 및 골드 와이어의 보호를 위해 봉지공정 수행시 상형 및 하형에 의해 회로기판이 눌러져 솔더마스크에 크랙이 발생할 우려가 높아지는 등의 단점이 있다. Alternatively, the BGA package used for costly circuit board compared to the conventional lead frame, so manufacturing costs are high, and in order to protect the semiconductor chip and a gold wire is pressed on the circuit board by the upper die and the lower die when performing a sealing process cracks in solder mask this may cause a disadvantage such concerns are high.

한편, BLP(Bottom Leaded Package)는 패키지 몸체의 바텀면을 통해 노출된 리드를 이용하여 기판에 실장하므로, 패키지 몸체의 두께를 아웃터리드를 갖는 DIP나 QFP 타입에 비해 작게 할 수 있다. On the other hand, since (Bottom Leaded Package) BLP is mounted on the substrate by using the read exposed through the bottom surface of the package body, it is possible to reduce the thickness of the package body than in DIP or QFP type having an outer lead.

그리고, 최근에는 μ-BGA등 반도체 패키지의 개발이 가속화되고 있으며, 상기한 각 반도체 패키지들은 실장면적, 입출력 단자수, 전기적 신뢰성, 제조공정의 유연성, 제조비용등에 있어 제각기 장점 및 단점을 갖고 있다. And, in recent years, and development of a semiconductor package such as μ-BGA is accelerating, the semiconductor package above may have the respective advantages and disadvantages it like mounting area, the number of input-output terminals, electrical reliability, and the flexibility of the manufacturing process, the manufacturing cost.

따라서, 상기한 각 패키지들의 장점을 살리면서 단점을 해소한 새로운 타입의 반도체 패키지가 지속적으로 연구 개발되고 있는 실정이다. Therefore, a situation where a semiconductor package of eliminating the drawbacks while making the benefits of each package above a new type of continuous development and research.

본 발명은 상기한 바와 같이 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 반도체 패키지를 제공하기 위한 것으로서, 회로기판과 리드프레임을 접목시킨 형태의 기판을 이용하므로써 공정의 단순화를 도모함과 더불어 보드 레벨의 신뢰성을 확보할 수 있는 새로운 구조의 반도체 패키지를 제공하는데 그 목적이 있다. The present invention simplifies the process By maximum raised while drawback is used a substrate of which combine to the circuit board and the lead frame serves to provide a semiconductor package of the resolved new type form the advantages of the conventional semiconductor package, as described above in addition to the domoham provide a semiconductor package having a new structure capable of ensuring the reliability of board level has its objectives.

도 1은 본 발명의 반도체 패키지를 나타낸 종단면도 1 is a longitudinal sectional view of the semiconductor package of the present invention

도 2a 내지 도 2h는 본 발명의 패키지 제조 과정을 나타낸 것으로서, Figure 2a to 2h are as showing a package manufacture process of the present invention,

도 2a는 본 발명 반도체 패키지 제조에 적용되는 회로기판을 나타낸 평면도 Figure 2a is a plan view showing a circuit board to be applied to manufacture a semiconductor package of this invention

도 2b는 본 발명 반도체 패키지 제조에 적용되는 리드프레임을 나타낸 평면도 Figure 2b is a plan view showing the lead frame applicable to the present invention manufactured a semiconductor package

도 2c는 도 2b의 리드프레임 상부에 회로기판이 올려진 상태를 한 유니트를 예로 들어 나타낸 평면도 Figure 2c is a plan view showing an example state in which the circuit board to the lead frame the upper part of Figure 2b up to a unit example

도 2d는 도 2c의 Ⅰ-Ⅰ선을 따른 종단면도 Figure 2d is a longitudinal cross-sectional view along the line of Figure 2c Ⅰ-Ⅰ

도 2e는 다이패들 상면에 칩이 어태치된 상태를 나타낸 종단면도 Figure 2e is a longitudinal cross-sectional view showing an upper surface of the chip on the die attach paddle state

도 2f는 와이어 본딩후의 상태를 나타낸 종단면도 Figure 2f is a longitudinal cross-sectional view showing a state after the wire bonding

도 2g는 봉지후의 상태를 나타낸 종단면도 Figure 2g is a longitudinal cross-sectional view showing a state after sealing

도 2h는 트리밍 후의 상태를 나타낸 종단면도 Figure 2h is a longitudinal cross-sectional view showing a state after trimming

도 3은 본 발명의 반도체 패키지가 마더보드에 실장된 상태를 나타낸 종단면도 Figure 3 is a longitudinal sectional view of the semiconductor package of the present invention showing a state mounted on the mother board

도 4는 본 발명의 반도체 패키지가 스택된 상태를 나타낸 종단면도 Figure 4 is a longitudinal sectional view showing a semiconductor package of the present invention the stack state

* 도면의 주요부분에 대한 부호의 설명 * * Description of the Related Art *

1:칩 2:회로기판 1: Chip 2: circuit board

3:리드프레임 4:다이패들 3: the dies D: lead frame 4

5:리드 6:와이어 5: Lead 6: Wire

7:몰드바디 8:본드핑거 7: 8 molded body: the bond fingers

9:비어홀 10:윈도우 9: Beer hall 10: Windows

11:마더보드 12:솔더 11: 12 Motherboard: Solder

상기한 목적을 달성하기 위해, 본 발명은 칩이 안착되는 다이패들과, 상기 다이패들 주위에 배치되는 리드와, 상기 리드 상면에 부착되며 다이패들이 노출되도록 하는 윈도우와 와이어 본딩을 위한 본드핑거 및 리드와의 전기적 접속을 위한 비어홀이 구비된 회로기판과, 상기 칩의 본딩패드와 회로기판의 본드핑거를 전기적으로 연결하는 와이어와, 상기 칩과 와이어 및 본드핑거를 봉지하는 몰드바디를 포함하여서 됨을 특징으로 하는 반도체 패키지가 제공된다. To achieve the above object, the present invention is attached to the lid and the upper surface of the lead arranged in the periphery of the die paddle and the die paddle which the chip is mounted bond for windows and wire bonding that allows a die paddle exposure including a circuit board via hole is provided for the electrical connection to the fingers and the lead and a wire electrically connected to the bond fingers of the bonding pad and the circuit substrate of the chip, and a molded body for sealing the chip and the wire and the bond fingers the semiconductor package as hayeoseo that the features are provided.

상기한 목적을 달성하기 위한 본 발명의 다른 형태에 따르면, 다이패들 및 리드를 구비한 리드프레임 상면에 다이패들 노출을 위한 윈도우와 와이어 본딩을 위한 본드핑거 및 리드와의 전기적 접속을 위한 비어홀이 구비된 회로기판 스트립을 부착하는 단계와, 상기 다이패들 상면에 칩을 부착하는 단계와, 상기 칩의 본딩패드와 회로기판의 본드핑거를 와이어를 이용하여 전기적으로 연결하는 단계와, 상기 칩과 와이어 및 본드핑거를 봉지제로 봉지하여 몰드바디를 형성하는 단계와, 상기 회로기판 스트립 및 리드프레임으로부터 각 유니트가 분리되도록 트리밍하는 단계를 포함하여서 됨을 특징으로 하는 반도체 패키지 제조방법이 제공된다. According to another aspect of the present invention for achieving the above object, the via hole for electrical connection to the bond finger and the lead for the window and the wire-bonded to the die paddle exposed to the upper surface of a lead frame with a die paddle and leads and the step of attaching a provided a circuit board strip, comprising the steps of: connecting with the step of attaching the chip to the top surface of the die D, the bond fingers of the bonding pad and the circuit substrate of the chip to the electrically using a wire, the chip and a semiconductor package manufacturing method is provided with a wire and forming a molded body by sealing the bond finger bag zero, hayeoseo comprising the step of trimming so that each unit is separated from the circuit board and the lead frame strip that feature.

이하, 본 발명의 실시예를 첨부도면 도 1 내지 도 4를 참조하여 설명하면 다음과 같다. Hereinafter, it will be described with reference to the accompanying drawings FIG embodiment of the present invention refer to FIGS. 1 to 4 as follows.

도 1은 본 발명의 반도체 패키지를 나타낸 종단면도로서, 칩(1)이 안착되는다이패들(4)과, 상기 다이패들(4) 주위에 배치되는 리드(5)와, 상기 리드(5) 상면에 부착되며 다이패들(4)이 노출되도록 하는 윈도우(10)와 와이어 본딩을 위한 본드핑거(8) 및 리드(5)와의 전기적 접속을 위한 비어홀(9)이 구비된 회로기판(2)과, 상기 칩(1)의 본딩패드와 회로기판(2)의 본드핑거(8)를 전기적으로 연결하는 와이어(6)와, 상기 칩(1)과 와이어(6) 및 본드핑거(8)를 봉지하는 몰드바디(7)를 포함하여 구성된다. 1 is a longitudinal sectional view of the semiconductor package of the present invention, the lid 5 is placed around the die paddle which the chip (1) is mounted (4) and the die paddle (4), the leads (5 ) is attached to the upper surface of the die paddle (4) a window 10 with the circuit board via hole 9 is provided for electrical connection to the bond finger (8) and lid (5) for wire bonding to be exposed (2 ) and, with the wire 6 that electrically connect the bond fingers (8) of the bonding pad and the circuit board 2 of the chip 1, the chip 1 and the wire 6 and the bond fingers (8) a is configured to include a molded body (7) for sealing.

이 때, 회로기판(2)의 비어홀(9) 영역에는 비어홀(9)과 리드(5)가 접합되어 전기적으로 연결되도록 하는 솔더(12)가 도포된다. At this time, the solder 12 for bonding to electrically connect the via hole 9 area, the via hole 9 and the lid 5 of the circuit board (2) is applied.

한편, 상기 리드(5)와 회로기판(2) 사이 및, 다이패들(4)과 칩(1) 사이에는 어드헤시브가 개재되며, 상기 어드헤시브로서는 접착테이프 또는 에폭시가 사용된다. On the other hand, there is interposed an adjuster H. sheave between the lid 5 and the circuit board (2) and between the die paddle (4) and the chip (1), the adjuster H. sheave As the pressure-sensitive adhesive tape or epoxy is used.

한편, 상기 다이패들(4)은 회로기판(2)에 부착되는 타이바에 의해 지지되며, 몰드바디(7) 외측으로 노출된다. On the other hand, the die paddle (4) is supported by tie bars attached to the circuit board 2 and is exposed to the outside the mold body (7).

이와 같이 구성된 본 발명 패키지의 제조 과정을 도 2a 내지 도 2h를 참조하여 설명하면 다음과 같다. According to this description with reference to Fig. 2a to 2h a manufacturing process diagram of the present invention, the package is configured as follows.

먼저, 도 2a에 도시된 바와 같이, 다이패들(4)이 노출되도록 하는 윈도우(10)와 와이어 본딩을 위한 본드핑거(8) 및 리드(5)와의 전기적 접속을 위한 비어홀(9)이 구비된 회로기판(2)을 준비한다. First, the die paddle (4) via holes (9) for electrical connection to the bond fingers 8 and the lid 5 to the window 10 and the wire bonding such that the exposure is provided as shown in Figure 2a prepare a circuit board (2).

이와 더불어, 도 2b에 도시된 바와 같이, 다이패들(4)과 이를 지지하기 위한 타이바 및 상기 다이패들(4) 주위에 배치되는 리드(5)를 구비한 리드프레임(3)을준비한다. In addition, as shown in Figure 2b, preparing a lead frame (3) provided with a lid 5 which is disposed about the die paddle 4 and the tie bars and the die paddle (4) for supporting this do.

이 때, 리드(5)들에는 리드 록 테이프(13)가 부착되어 있다. At this time, the lid 5 has a lid lock tape 13 is attached.

이와 같이 회로기판 스트립(200) 및 리드프레임(3)이 준비된 상태에서, 도 2c 및 도 2d에 나타낸 바와 같이 리드프레임(3) 상부면에 회로기판 스트립(200)을 부착한다. In this way the prepared circuit substrate strip 200 and the lead frame (3) status, is attached to the lead frame 3, a substrate strip (200) circuit on a top surface as shown in Fig. 2c and 2d.

그 후, 도 2e에 나타낸 바와 같이, 상기 다이패들(4) 상면에 칩(1)을 어태치하고, 이어 도 2f에서와 같이 칩(1)의 본딩패드와 회로기판(2)의 본드핑거(8)를 골드와이어(6) 등으로 연결하는 와이어 본딩을 실시한다. After that, as shown in Fig. 2e, the die paddle (4) attach control chip (1) on the upper surface and, after the bonding pads and the circuit board 2 of the chip 1, as shown in Fig. 2f bond fingers (8) subjected to wire bonding to connect to, such as a gold wire 6.

그 다음, 도 2g에 나타낸 바와 같이, 칩(1)과 와이어(6)와 본드핑거(8)를 봉지제로써 봉지하여 몰드바디(7)를 형성한다. Then, also forming, chip 1 and the wire 6 and the bond fingers (8) of the mold body (7) by sealing as a sealing material, as shown in Fig. 2g.

상기, 몰드바디(7)는 트랜스퍼 몰딩에 의해 수행가능하며, 이 때 상기 다이패들(4) 저면은 몰드바디(7) 외측으로 노출되어 히트싱크 역할을 겸하게 된다. Wherein, the mold body (7) can be performed by a transfer molding and, at this time, is exposed the die paddle (4) has a bottom surface to the outside the mold body (7) is a heat sink gyeomhage role.

한편, 몰드바디(7) 형성후에는, 도 2h에 나타낸 바와 같이 트리밍하여 리드를 리드프레임으로부터 분리시킴과 동시에 개별 유니트별로 분리하므로써 반도체 패키지를 완성하게 된다 On the other hand, after the molded body (7) is formed, and By and simultaneously also separated from the leadframe leads by trimming as shown in 2h separated into individual units to complete the semiconductor package

상기와 같이 제조된 본 발명의 반도체 패키지는 마더보드(11)등에의 실장시, 도 3에 나타낸 바와 같이 트리밍된 비어홀(9) 영역에 솔더(12)를 도포하여 비어홀(9)과 리드(5)가 전기적으로 접속되도록 한 상태에서 실장하게 된다. The semiconductor package of the present invention prepared as described above is the mother board 11 during mounting of the like, the via hole (9) by applying a solder 12 in the via hole 9 area trimming as shown in Fig. 3 and the lid (5 ) it is mounted in a state to be electrically connected to each other.

이와 같이 제조된 본 발명의 반도체 패키지는 리드프레임(3)을 사용하므로써 구조적으로 강하고, 리드(5)가 기판에 직접 접합되므로 접합 신뢰성이 향상된다. The semiconductor package of the present invention produced in this manner is by the use of a lead frame 3, is structurally strong, the lid 5 is directly bonded to the substrate since the bonding reliability can be improved.

한편, 회로기판 스트립(200)과 리드프레임(3)을 단순 접합 후 와이어 본딩 및 몰딩을 이용하는 간단한 공정에 의해 제조하며, 스트립 상태에서 전공정을 끝낸 후 낱개로 분리하기 때문에 제조시간을 단축시킬 수 있게 된다. On the other hand, the circuit board strip 200 and the lead frame 3, a shallow junction after and prepared by a simple process using the wire bonding and molding, since the separation individually After finishing the pre-process in a strip state to shorten the production time it is possible.

또한, 본 발명의 패키지는 다이패들(4) 저면이 몰드바디(7) 외측으로 노출되어 히트싱크 역할을 함에 따라, 열방출 성능이 향상된다. In addition, the package of the present invention is a bottom view of the die paddle (4) is exposed to the outside the mold body (7), improving the heat radiation performance as a heat sink role.

한편, 본 발명의 반도체 패키지는 도 4에 도시한 바와 같은 형태로 스택 패키지를 구현할 수 있게 된다. On the other hand, the semiconductor package of the present invention is able to implement a stack package in the form as shown in Fig.

이상에서와 같이, 본 발명은 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 반도체 패키지를 제공하기 위한 것이다. As described above, the present invention as much as possible while utilizing the benefits of a conventional semiconductor package to provide a semiconductor package of a new type of eliminating disadvantages.

즉, 본 발명은 회로기판과 리드프레임을 접목시킨 형태의 기판으로써 공정의 단순화를 도모함과 더불어 보드 레벨의 신뢰성을 확보할 수 있는 새로운 구조의 반도체 패키지를 제공할 수 있게 된다. That is, the present invention is possible to provide a semiconductor package having a novel structure capable of ensuring the reliability of the board-level with domoham simplification of the process as of the type that incorporate a circuit board and the lead frame board.

Claims (10)

  1. 칩이 안착되는 다이패들과, The die paddle which the chip is seated and,
    상기 다이패들 주위에 배치되는 리드와, And leads disposed around said die paddle,
    상기 리드 상면에 부착되며 다이패들이 노출되도록 하는 윈도우와 와이어 본딩을 위한 본드핑거 및 리드와의 전기적 접속을 위한 비어홀이 구비된 회로기판과, Attached to the lid top surface and the die paddle and a circuit board having a via hole for electrical connection to the bond finger and the read window for the wire bonding to be exposed,
    상기 칩의 본딩패드와 회로기판의 본드핑거를 전기적으로 연결하는 와이어와, And wire for electrically connecting the bonding fingers of the bonding pads and the circuit substrate of the chip,
    상기 칩과 와이어 및 본드핑거를 봉지하는 몰드바디를 포함하여서 됨을 특징으로 하는 반도체 패키지. The semiconductor package as claimed hayeoseo comprises a molded body to seal the chip and the wire and the bond fingers.
  2. 제 1 항에 있어서, According to claim 1,
    상기 회로기판의 비어홀 영역에 도포되어 상기 비어홀과 리드가 전기적으로 연결되도록 하는 솔더가 포함됨을 특징으로 하는 반도체 패키지. The semiconductor package is applied to a via hole area of ​​said circuit board with solder in which the via hole and the lead to be electrically connected to that feature included.
  3. 제 1 항에 있어서, According to claim 1,
    상기 리드와 회로기판 사이 및, 다이패들과 칩 사이에는 어드헤시브가 개재됨을 특징으로 하는 반도체 패키지. Between the lead and the circuit board and the die paddle and the semiconductor chip package, it characterized in that the adjuster is interposed H. sheave.
  4. 제 3 항에 있어서, 4. The method of claim 3,
    상기 어드헤시브는 접착테이프 또는 에폭시임을 특징으로 하는 반도체 패키지. The adjuster H. sheave is a semiconductor package characterized in that the pressure-sensitive adhesive tape or epoxy.
  5. 제 1 항에 있어서, According to claim 1,
    상기 다이패들 저면은 몰드바디 외측으로 노출됨을 특징으로 하는 반도체 패키지. The die paddle bottom surface of the semiconductor package is characterized by the exposure of the outer molded body.
  6. 제 1 항에 있어서, According to claim 1,
    상기 몰드바디는 트랜스퍼 몰딩에 의해 형성됨을 특징으로 하는 반도체 패키지. The mold body is a semiconductor package characterized by formed by transfer molding.
  7. 다이패들 및 리드를 구비한 리드프레임 상면에 다이패들 노출을 위한 윈도우와 와이어 본딩을 위한 본드핑거 및 리드와의 전기적 접속을 위한 비어홀이 구비된 회로기판 스트립을 부착하는 단계와, And the die paddle and comprising: a circuit board having a via hole strip for electrical connection to the bond finger and the lead on the upper surface of a lead frame having a lead for the window and the wire-bonded to a die attach paddle exposed,
    상기 다이패들 상면에 칩을 부착하는 단계와, And the step of attaching the chip to the top surface of the die paddle,
    상기 칩의 본딩패드와 회로기판의 본드핑거를 와이어를 이용하여 전기적으로 연결하는 단계와, And the step of connecting the bond fingers of the bonding pad and the circuit substrate of the chip to the electrically using a wire,
    상기 칩과 와이어 및 본드핑거를 봉지제로 봉지하여 몰드바디를 형성하는 단계와, Forming a molded body by sealing the chip and the wire and the bond fingers sealing agent,
    상기 회로기판 스트립 및 리드프레임으로부터 각 유니트가 분리되도록 트리밍하는 단계를 포함하여서 됨을 특징으로 하는 반도체 패키지 제조방법. The semiconductor package manufacturing method as claimed hayeoseo comprising the step of trimming so that each unit is separated from the circuit board and the lead frame strip.
  8. 제 7 항에 있어서, The method of claim 7,
    상기 어드헤시브는 열전도성 접착테이프 또는 에폭시임을 특징으로 하는 반도체 패키지 제조방법. The adjuster H. sheaves method of manufacturing a semiconductor package characterized in that the thermally conductive adhesive tape, or epoxy.
  9. 제 7 항에 있어서, The method of claim 7,
    몰드바디를 형성하는 단계는 트랜스퍼 몰딩에 의해 수행됨을 특징으로 하는 반도체 패키지 제조방법. Forming a molded body is a semiconductor package manufacturing method according to claim performed by an transfer molding.
  10. 제 7 항에 있어서, The method of claim 7,
    회로기판의 비어홀 영역에 도포되는 솔더에 의해 비어홀과 리드가 전기적으로 연결되도록 접합됨을 특징으로 하는 반도체 패키지 제조방법. A semiconductor circuit manufacturing packages of features so that the via hole and bonding the leads are electrically connected by the solder to be applied to the via hole area of ​​the substrate.
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US6927478B2 (en) * 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
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