KR100600213B1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
KR100600213B1
KR100600213B1 KR1020000046958A KR20000046958A KR100600213B1 KR 100600213 B1 KR100600213 B1 KR 100600213B1 KR 1020000046958 A KR1020000046958 A KR 1020000046958A KR 20000046958 A KR20000046958 A KR 20000046958A KR 100600213 B1 KR100600213 B1 KR 100600213B1
Authority
KR
South Korea
Prior art keywords
semiconductor chip
circuit board
input
semiconductor
chip
Prior art date
Application number
KR1020000046958A
Other languages
Korean (ko)
Other versions
KR20020013287A (en
Inventor
도병태
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020000046958A priority Critical patent/KR100600213B1/en
Publication of KR20020013287A publication Critical patent/KR20020013287A/en
Application granted granted Critical
Publication of KR100600213B1 publication Critical patent/KR100600213B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

이 발명은 반도체패키지에 관한 것으로, 반도체패키지의 부피 변화없이 복수의 반도체패키지를 적층할 수 있는 동시에, 실장밀도를 극대화하고 고기능화를 구현할 수 있도록, 하면에 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 상면에 접착된 칩탑재판과, 상기 칩탑재판의 외주연에 방사상으로 형성된 다수의 내부리드 및 이것에 연결된 외부리드로 이루어진 리드프레임과; 상면에 다수의 입출력패드가 형성된 채, 상기 리드프레임의 칩탑재판 상면에 접착된 제2반도체칩과; 상기 제1반도체칩 및 제2반도체칩의 입출력패드를 내부리드에 전기적으로 접속하는 도전성와이어와; 상기 리드프레임중 내부리드 하부의 제1반도체칩, 도전성와이어 등을 봉지하는 봉지재와; 상기 리드프레임의 내부리드 상면에 형성된 절연성댐과; 상기 절연성 댐상에 부착된 글래스를 포함하여 이루어진 것을 특징으로 함.The present invention relates to a semiconductor package, wherein a plurality of semiconductor packages can be stacked without changing the volume of the semiconductor package, and at the same time, a first semiconductor chip having a plurality of input / output pads formed on a lower surface thereof in order to maximize mounting density and realize high functionalization, ; A lead frame comprising a chip mounting plate bonded to an upper surface of the first semiconductor chip, a plurality of inner leads radially formed on an outer circumference of the chip mounting plate, and an outer lead connected thereto; A second semiconductor chip bonded to an upper surface of the chip mounting plate of the lead frame with a plurality of input / output pads formed on the upper surface; Conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip to internal leads; An encapsulant for encapsulating a first semiconductor chip, a conductive wire, and the like under the inner lead of the lead frame; An insulating dam formed on an upper surface of the inner lead of the lead frame; And glass attached to the insulating dam.

Description

반도체패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

도1은 종래의 통상적인 리드프레임을 이용한 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor package using a conventional lead frame.

도2는 본 발명의 제1실시예에 의한 반도체패키지를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package according to a first embodiment of the present invention.

도3은 본 발명의 제2실시예에 의한 반도체패키지를 도시한 단면도이다.3 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention.

도4는 본 발명의 제3실시예에 의한 반도체패키지를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package according to a third embodiment of the present invention.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

100'; 종래의 반도체패키지100 '; Conventional Semiconductor Package

101~103; 본 발명에 의한 반도체패키지101-103; Semiconductor package according to the present invention

1; 제1반도체칩 2; 제2반도체칩One; A first semiconductor chip 2; Second semiconductor chip

1a, 2a; 입출력패드 4; 내부리드1a, 2a; Input / output pad 4; Internal lead

5; 칩탑재판 6; 외부리드5; Chip mounting plate 6; External lead

8; 도전성와이어 10; 회로기판8; Conductive wire 10; Circuit board

11; 수지층 12; 회로패턴11; Resin layer 12; Circuit pattern

12a; 본드핑거 12b; 볼랜드12a; Bondfinger 12b; Borland

13; 비아홀 14; 커버코트13; Via hole 14; Cover coat

16; 도전성볼 18; 봉지재16; Conductive ball 18; Encapsulant

19; 절연성댐 22; 글래스19; Insulating dam 22; Glass

본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 반도체패키지의 부피 변화없이 복수의 반도체패키지를 적층할 수 있는 동시에, 실장밀도를 극대화하고 고기능화를 구현할 수 있는 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of stacking a plurality of semiconductor packages without changing the volume of the semiconductor package, maximizing the mounting density and implementing high functionality.

통상 반도체패키지는 반도체칩을 외부 환경으로부터 안전하게 보호함은 물론, 그 반도체칩과 마더보드(Mother Board)와의 전기적 신호가 용이하게 교환되도록 한 장치를 말한다.In general, a semiconductor package refers to a device that not only protects a semiconductor chip from an external environment but also easily exchanges electrical signals between the semiconductor chip and a motherboard.

이러한 반도체패키지로서 종래 리드프레임을 이용한 통상적인 반도체패키지(100')를 도1에 도시하였으며 그 구조를 간단히 설명하면 다음과 같다.As such a semiconductor package, a conventional semiconductor package 100 'using a conventional lead frame is shown in FIG. 1, and the structure thereof will be briefly described as follows.

도시된 바와 같이 상면에 다수의 입출력패드(2a')가 형성된 반도체칩(2')과, 접착제가 개재되어 상기 반도체칩(2')이 탑재되는 칩탑재판(5')과, 상기 칩탑재판(5')의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드(4')와, 상기 내부리드(4')로부터 외측으로 연장된 외부리드(6')와, 상기 반도체칩(2')과 내부리드(4')를 전기적으로 접속시키는 다수의 도전성와이어(8')와, 상기 반도체칩(2'), 도전성와이어(8'), 칩탑재판(5') 및 내부리드(4') 등을 외부 환경으로부터 보호하는 봉지재(10')로 이루어져 있다.As shown, a semiconductor chip 2 'having a plurality of input / output pads 2a' formed on an upper surface thereof, a chip mounting plate 5 'on which the semiconductor chip 2' is mounted with an adhesive interposed therebetween, and the chip mounting. A plurality of inner leads 4 'formed at a predetermined distance apart from the outer circumference of the plate 5', an outer lead 6 'extending outward from the inner lead 4', and the semiconductor chip 2 '. ) And a plurality of conductive wires 8 'electrically connecting the inner lead 4', the semiconductor chip 2 ', the conductive wire 8', the chip mounting plate 5 'and the inner lead 4'. ') Is made of an encapsulant 10' to protect the environment from the outside.

이러한 반도체패키지(100')는 봉지재(10') 외측으로 연장된 외부리드(6')가 솔더에 의해 마더보드에 실장된다. 또한 반도체칩과 마더보드 사이의 신호 교환은 도전성와이어, 내부리드 및 외부리드를 통해서 이루어진다.In the semiconductor package 100 ', an outer lead 6' extending outside the encapsulant 10 'is mounted on the motherboard by soldering. In addition, signal exchange between the semiconductor chip and the motherboard is performed through conductive wires, inner leads and outer leads.

이상에서와 같은 리드프레임을 이용한 반도체패키지는 최종 입출력수단인 외부리드가 봉지재 외주연으로 연장된 채 마더보드에 실장됨으로써 반도체패키지가 마더보드에서 차지하는 면적이 커지는(실장밀도가 작아지는) 문제가 있다. 상기와 같이 하여, 그 반도체패키지의 실장밀도가 작기 때문에 전자부품의 고기능화를 구현하기 위해서는 그 전자부품의 크기 내지 부피가 커져야 하는 문제도 있다.As described above, the semiconductor package using the lead frame has a problem that the semiconductor package occupies a large area on the motherboard (the mounting density decreases) because the external lead as the final input / output means is mounted on the motherboard with the outer peripheral edge of the encapsulant extending. have. As described above, since the mounting density of the semiconductor package is small, there is also a problem that the size or volume of the electronic component must be large in order to realize high functionalization of the electronic component.

최근에는 마더보드에의 실장밀도를 높이는 동시에 반도체패키지의 고기능화를 위해 적층형 반도체패키지가 제조되고 있다.Recently, laminated semiconductor packages have been manufactured to increase the mounting density on the motherboard and to improve the functionality of the semiconductor packages.

그러나, 이러한 적층형 반도체패키지는 대부분 동일한 형태의 반도체패키지를 적층하는 구조로 되어 있음으로써, 그 부피 즉, 반도체패키지의 높이가 높아지는 단점이 있다. 이렇게 반도체패키지의 높이가 커지게 되면 비록 실장밀도나 전기적 성능을 높일 수는 있지만, 결국 그 반도체패키지가 실장되는 전자부품의 부피 또는 높이가 커지는 문제가 있다.However, such stacked semiconductor packages have a structure in which most of the same type semiconductor packages are stacked, so that the volume, that is, the height of the semiconductor package is increased. As the height of the semiconductor package increases, the mounting density and the electrical performance may be increased, but the volume or height of the electronic component on which the semiconductor package is mounted increases.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 부피 변화없이 복수의 반도체패키지를 적층할 수 있는 동시에, 실장밀도를 극대화하고 고기능화를 구현할 수 있는 반도체패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-described problems, and to provide a semiconductor package that can be stacked a plurality of semiconductor packages without changing the volume, maximizing the mounting density and high functionality.

상기한 목적을 달성하기 위해 본 발명은 하면에 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 상면에 접착된 칩탑재판과, 상기 칩탑재판의 외주연에 방사상으로 형성된 다수의 내부리드 및 이것에 연결된 외부리드로 이루어진 리드프레임과; 상면에 다수의 입출력패드가 형성된 채, 상기 리드프레임의 칩탑재판 상면에 접착된 제2반도체칩과; 상기 제1반도체칩 및 제2반도체칩의 입출력패드를 내부리드에 전기적으로 접속하는 도전성와이어와; 상기 리드프레임중 내부리드 하부의 제1반도체칩, 도전성와이어 등을 봉지하는 봉지재와; 상기 리드프레임의 내부리드 상면에 형성된 절연성댐과; 상기 절연성 댐상에 부착된 글래스를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device comprising: a first semiconductor chip having a plurality of input / output pads formed on a bottom surface thereof; A lead frame comprising a chip mounting plate bonded to an upper surface of the first semiconductor chip, a plurality of inner leads radially formed on an outer circumference of the chip mounting plate, and an outer lead connected thereto; A second semiconductor chip bonded to an upper surface of the chip mounting plate of the lead frame with a plurality of input / output pads formed on the upper surface; Conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip to internal leads; An encapsulant for encapsulating a first semiconductor chip, a conductive wire, and the like under the inner lead of the lead frame; An insulating dam formed on an upper surface of the inner lead of the lead frame; It characterized in that it comprises a glass attached to the insulating dam.

여기서, 상기 리드프레임과 제2반도체칩 사이에는 수지층을 중심으로 상,하면에 회로패턴이 형성되어 이루어진 회로기판이 더 위치되어 있고, 상기 제2반도체칩의 입출력패드는 상기 회로기판의 회로패턴에 도전성와이어로 접속되어 있고, 상기 회로기판의 하면에 형성된 회로패턴은 선택된 내부리드에 전기적으로 접속될 수 있다.Here, a circuit board is formed between the lead frame and the second semiconductor chip on the upper and lower surfaces of the resin layer, and the input / output pad of the second semiconductor chip is the circuit pattern of the circuit board. And a circuit pattern formed on the lower surface of the circuit board may be electrically connected to the selected inner lead.

또한, 상기 절연성 댐은 재질을 봉지재로 하여 형성할 수도 있다.In addition, the insulating dam may be formed using a material as an encapsulant.

또한, 상기한 목적을 달성하기 위해 본 발명에 반도체패키지는 하면에 다수의 입출력패드가 형성된 제1반도체칩과; 상기 제1반도체칩의 상면에 그 외주연으로 확장된 채 접착된 수지층과, 상기 수지층의 상,하면에 본드핑거 및 볼랜드를 갖도록 형성된 다수의 도전성 회로패턴으로 이루어진 회로기판과; 상면에 다수의 입출력패드가 형성된 채 상기 회로기판의 상면 중앙에 접착된 제2반도체칩과; 상기 제1 반도체칩 및 제2반도체칩의 입출력패드를 회로기판의 본드핑거에 전기적으로 접속하는 도전성와이어와; 상기 회로기판의 하부에 위치하는 제1반도체칩, 도전성와이어를 봉지하는 봉지재와; 상기 회로기판의 상면중 본드핑거의 외주면에 형성된 절연성댐과; 상기 절연성 댐 상부에 부착된 글래스와; 상기 회로기판 하면의 볼랜드에 융착된 도전성볼을 포함하여 이루어 질 수도 있다.In addition, in order to achieve the above object, the semiconductor package according to the present invention comprises a first semiconductor chip formed with a plurality of input and output pads on the bottom surface; A circuit board comprising a resin layer bonded to an upper surface of the first semiconductor chip with its outer periphery extended, and a plurality of conductive circuit patterns formed on the upper and lower surfaces of the resin layer to have bond fingers and ball lands; A second semiconductor chip bonded to the center of the upper surface of the circuit board with a plurality of input / output pads formed on the upper surface; Conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip to bond fingers of the circuit board; An encapsulant for encapsulating a first semiconductor chip and a conductive wire disposed under the circuit board; An insulating dam formed on an outer circumferential surface of a bond finger among upper surfaces of the circuit board; Glass attached to an upper portion of the insulating dam; It may be made of a conductive ball fused to the ball land on the lower surface of the circuit board.

상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 반도체패키지의 부피 특히 높이를 종래와 같이 유지하면서도 소위 적층된 형태의 반도체패키지를 구현함으로써 실장밀도를 높이는 동시에 반도체패키지의 고기능화를 구현할 수 있게 된다. 결국, 상기 반도체패키지를 사용한 전자 부품은 그 크기를 더욱 소형화하는 동시에, 고기능화할 수 있게 된다.According to the semiconductor package according to the present invention as described above, while maintaining the volume, in particular the height of the semiconductor package as in the prior art, by implementing a so-called stacked semiconductor package it is possible to increase the mounting density and at the same time to realize high functionalization of the semiconductor package. As a result, the electronic component using the semiconductor package can be further downsized and highly functional.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2는 본 발명의 제1실시예에 의한 반도체패키지(101)를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package 101 according to a first embodiment of the present invention.

먼저, 하면에 다수의 입출력패드(1a)가 형성된 제1반도체칩(1)이 위치되어 있고, 상기 제1반도체칩(1)의 상면에는 칩탑재판(5)이 접착수단으로 접착되어 있다. 또한 상기 칩탑재판(5)을 중심으로 그 외측을 향하는 두방향 또는 네방향으로는 다수의 내부리드(4)가 위치되어 있으며, 상기 각각의 내부리드(4) 외측으로는 외부리드(6)가 연장되어 있다.First, a first semiconductor chip 1 having a plurality of input / output pads 1a formed thereon is positioned, and a chip mounting plate 5 is bonded to an upper surface of the first semiconductor chip 1 by an adhesive means. In addition, a plurality of inner leads 4 are positioned in two or four directions toward the outside of the chip mounting plate 5, and the outer leads 6 outside the respective inner leads 4. Is extended.

여기서, 상기 칩탑재판(5), 내부리드(4) 및 외부리드(6)는 총칭하여 통상 리 드프레임으로 불려진다.Here, the chip mounting plate 5, the inner lead 4 and the outer lead 6 are generically called a lead frame.

상기 제1반도체칩(1)의 입출력패드(1a)와 내부리드(4)는 골드와이어 또는 알루미늄 와이어와 같은 도전성와이어(8)에 의해 서로 접속되어 있다. 또한, 상기 리드프레임의 하면 즉, 칩탑재판(5) 및 내부리드(4)의 하면에 위치하는 제1반도체칩(1), 도전성와이어(8) 등은 봉지재(18)로 봉지되어 외부 환경으로부터 보호되도록 되어 있다.The input / output pad 1a and the inner lead 4 of the first semiconductor chip 1 are connected to each other by a conductive wire 8 such as a gold wire or an aluminum wire. In addition, the first semiconductor chip 1, the conductive wire 8, and the like, which are positioned on the lower surface of the lead frame, that is, the lower surface of the chip mounting plate 5 and the inner lead 4, are encapsulated with an encapsulant 18 and externally provided. Protected from the environment

계속해서, 상기 칩탑재판(5)의 상면에는 제2반도체칩(2)이 접착제로 접착되어 있으며, 이것은 상면에 다수의 입출력패드(2a)가 형성되어 있다. 상기 제2반도체칩(2)의 입출력패드(2a)와 상기 봉지재(18) 상면의 내부리드(4)는 역시 도전성와이어(8)로 연결되어 있다.Subsequently, the second semiconductor chip 2 is bonded to the upper surface of the chip mounting plate 5 with an adhesive, and a plurality of input / output pads 2a are formed on the upper surface. The input / output pad 2a of the second semiconductor chip 2 and the inner lead 4 of the upper surface of the encapsulant 18 are also connected by conductive wires 8.

또한, 상기 내부리드(4)의 상면에는 상기 제2반도체칩(2) 및 도전성와이어(8)가 내측에 위치하도록 봉지재(18) 재질의 절연성댐(19)이 형성되어 있다. 물론, 상기 절연성댐(19)은 상기 내부리드(4)와 내부리드(4) 사이의 봉지재(18) 상부에도 형성되며, 상기 절연성댐(19)의 상부에는 투명한 글래스(22)가 위치되어 있다. 따라서, 상기 제2반도체칩(2)이 CCD용 반도체칩일 경우에는 외부의 광(光)을 용이하게 센싱할 수 있게 된다. 또한 상기 글래스(22)에는 도시하지 않았지만 렌즈를 더 설치하여 그 수광율를 증가시킬 수 있다.In addition, an insulating dam 19 made of an encapsulant 18 is formed on an upper surface of the inner lead 4 so that the second semiconductor chip 2 and the conductive wire 8 are located inside. Of course, the insulating dam 19 is also formed on the encapsulant 18 between the inner lead 4 and the inner lead 4, the transparent glass 22 is located on the upper portion of the insulating dam 19 have. Therefore, when the second semiconductor chip 2 is a CCD semiconductor chip, it is possible to easily sense external light. In addition, although not shown, the glass 22 may further include a lens to increase light reception.

따라서, 상기 제1반도체칩(1)의 입출력신호는 소정의 내부리드(4) 및 외부리드(6)를 통해 외부의 마더보드와 교신하게 되며, 또한 제2반도체칩(2)의 입출력신호도 선택된 내부리드(4) 및 외부리드(6)를 통해 외부의 마더보드와 교신하게 된 다.Therefore, the input / output signal of the first semiconductor chip 1 communicates with the external motherboard through the predetermined internal lead 4 and the external lead 6, and also the input / output signal of the second semiconductor chip 2 also. The selected inner lead 4 and outer lead 6 communicate with the external motherboard.

상기와 같이 칩탑재판(5)을 중심으로 그 상,하면에 제1반도체칩(1) 및 제2반도체칩(2)이 위치됨으로써 종래와 동일하거나 또는 유사한 높이를 가지면서도 반도체칩이 적층된 형태의 반도체패키지를 구현하게 된다.As described above, the first semiconductor chip 1 and the second semiconductor chip 2 are positioned on the upper and lower surfaces of the chip mounting plate 5 so that the semiconductor chips may be stacked with the same or similar height as in the related art. The semiconductor package of the type will be implemented.

도3은 본 발명의 제2실시예에 의한 반도체패키지(102)를 도시한 단면도이다. 여기서 상기 반도체패키지(102)는 상기 제1실시예에 의한 반도체패키지(101)와 유사하므로, 이 반도체패키지(102)의 특징적인 구성만을 설명하기로 한다.3 is a cross-sectional view showing a semiconductor package 102 according to a second embodiment of the present invention. Here, since the semiconductor package 102 is similar to the semiconductor package 101 according to the first embodiment, only the characteristic configuration of the semiconductor package 102 will be described.

우선 제1실시예와 다르게 본 발명의 제2실시예는 칩탑재판(5), 봉지재(18) 및 내부리드(4) 상면에 회로기판(10)이 더 접착되어 있다.First, unlike the first embodiment, in the second embodiment of the present invention, the circuit board 10 is further adhered to the upper surface of the chip mounting plate 5, the encapsulant 18, and the inner lead 4.

상기 회로기판(10)은 수지층(11)(또는 테이프, 필름 등)을 중심으로 그 상,하면에 도전성 회로패턴(12)이 형성되어 있으며, 상기 상,하면의 회로패턴(12)은 도전성비아홀(13)에 의해 상호 연결되어 있다.The circuit board 10 has conductive circuit patterns 12 formed on and under the resin layer 11 (or tape, film, etc.), and the circuit patterns 12 on the upper and lower surfaces are conductive. They are interconnected by via holes 13.

상기 회로기판(10)의 상면 중앙에는 제2반도체칩(2)이 접착제로 접착되어 있으며, 상기 제2반도체칩(2)은 상면에 다수의 입출력패드(2a)가 형성되어 있다.A second semiconductor chip 2 is attached to the center of the upper surface of the circuit board 10 by an adhesive, and a plurality of input / output pads 2a are formed on the upper surface of the second semiconductor chip 2.

상기 제2반도체칩(2)의 입출력패드(2a)는 도전성와이어(8)에 의해 상기 회로기판(10)의 상면에 형성된 회로패턴(12)에 접속되어 있다.The input / output pad 2a of the second semiconductor chip 2 is connected to the circuit pattern 12 formed on the upper surface of the circuit board 10 by conductive wires 8.

물론, 상기 회로기판(10)의 하면에 형성된 회로패턴(12)은 소정의 선택된 내부리드(4) 상면에 솔더 등과 같은 접속부재에 의해 접속되어 있다.Of course, the circuit pattern 12 formed on the lower surface of the circuit board 10 is connected to the upper surface of the predetermined selected inner lead 4 by a connecting member such as solder or the like.

계속해서, 상기 제2반도체칩(2) 및 그것에 연결된 도전성와이어(8)의 외주연인 회로기판(10)에는 일정높이의 절연성댐(19)이 형성되어 있다. 물론, 상기 절연 성댐(19)은 재질을 봉지재(18)와 같은 재질로 할 수 있다. Subsequently, an insulating dam 19 having a predetermined height is formed on the circuit board 10 that is the outer circumference of the second semiconductor chip 2 and the conductive wire 8 connected thereto. Of course, the insulating dam 19 may be made of the same material as the encapsulant 18.

또한, 상기 절연성댐(19)의 상부에는 투명체의 글래스(22)가 접착되어 있으며, 따라서 상기 제2반도체칩(2)을 CCD용 반도체칩으로 함이 바람직하다.In addition, the glass 22 of the transparent body is adhered to the upper portion of the insulating dam 19, so that the second semiconductor chip 2 is preferably a semiconductor chip for CCD.

한편, 제1반도체칩(1)의 전기적 신호는 도전성와이어(8), 내부리드(4) 및 외부리드(6)를 통하여 마더보드와 교신하게 되고, 제2반도체칩(2)의 전기적 신호는 도전성와이어(8), 회로기판(10) 상면의 회로패턴(12), 도전성 비아홀(13), 회로기판(10) 하면의 회로패턴(12), 내부리드(4) 및 외부리드(6)를 통하여 마더보드와 교신하게 된다.On the other hand, the electrical signal of the first semiconductor chip 1 communicates with the motherboard through the conductive wire 8, the inner lead 4 and the outer lead 6, the electrical signal of the second semiconductor chip 2 The conductive wire 8, the circuit pattern 12 on the upper surface of the circuit board 10, the conductive via hole 13, the circuit pattern 12 on the lower surface of the circuit board 10, the inner lead 4 and the outer lead 6 Communicate with the motherboard through.

도4는 본 발명의 제3실시예에 의한 반도체패키지(103)를 도시한 단면도이다.4 is a cross-sectional view showing a semiconductor package 103 according to a third embodiment of the present invention.

먼저, 하면에 다수의 입출력패드(1a)가 형성된 제1반도체칩(1)이 위치되어 있고, 상기 제1반도체칩(1)의 상면에는 그것보다 면적이 넓은 회로기판(10)이 접착제로 접착되어 있다. 상기 회로기판(10)은 수지층(11)(또는 필름, 테이프 등등)을 중심으로 그 상,하면에 도전성 회로패턴(12)이 형성되어 있다. 상기 상면의 회로패턴(12)은 본드핑거(12a)를 포함하고, 하면의 회로패턴(12)은 본드핑거(12a) 및 볼랜드(12b)를 포함한다. 물론, 상기 상,하면의 회로패턴(12)은 도전성 비아홀(13)에 의해 상호 연결되어 있다. 또한, 상기 회로기판(10)의 상,하면에는 상기 본드핑거(12a) 및 볼랜드(12b)를 제외한 전체 영역이 커버코트(14)에 의해 코팅되어 있다.First, a first semiconductor chip 1 having a plurality of input / output pads 1a formed thereon is positioned on a lower surface thereof, and a circuit board 10 having a larger area than that of the first semiconductor chip 1 is bonded with an adhesive. It is. The circuit board 10 has a conductive circuit pattern 12 formed on and under the resin layer 11 (or film, tape, etc.). The upper circuit pattern 12 includes a bond finger 12a, and the lower circuit pattern 12 includes a bond finger 12a and a ball land 12b. Of course, the upper and lower circuit patterns 12 are interconnected by conductive via holes 13. In addition, upper and lower surfaces of the circuit board 10 are coated with the cover coat 14 except for the bond finger 12a and the borland 12b.

상기 제1반도체칩(1)의 입출력패드(1a)는 골드와이어 또는 알루미늄와이어와 같은 도전성와이어(8)에 의해 회로기판(10) 하면에 형성된 본드핑거(12a)와 전기적 으로 접속되어 있다. 또한, 상기 회로기판(10) 하면에 위치된 상기 제1반도체칩(1) 및 도전성와이어(8)는 봉지재(18)에 의해 봉지되어 있다. The input / output pad 1a of the first semiconductor chip 1 is electrically connected to the bond finger 12a formed on the bottom surface of the circuit board 10 by a conductive wire 8 such as a gold wire or an aluminum wire. In addition, the first semiconductor chip 1 and the conductive wire 8 positioned on the lower surface of the circuit board 10 are sealed by an encapsulant 18.

또한, 상기 회로기판(10) 하면에 위치된 볼랜드(12b)에는 솔더볼과 같은 도전성볼(16)이 융착되어 있음으로써 차후 마더보드에 실장 가능한 형태로 되어 있다.In addition, since the conductive balls 16 such as solder balls are fused to the ball lands 12b disposed on the lower surface of the circuit board 10, the ball lands 12b may be mounted on the motherboard later.

상기 회로기판(10)의 상면 중앙부에는 제2반도체칩(2)이 접착제로 접착되어 있으며, 상기 제2반도체칩(2)은 상면에 다수의 입출력패드(2a)가 형성되어 있다. 상기 제2반도체칩(2)의 입출력패드(2a)는 회로기판(10) 상면의 본드핑거(12a)와 도전성와이어(8)에 의해 상호 접속되어 있다.The second semiconductor chip 2 is bonded to the center of the upper surface of the circuit board 10 with an adhesive, and the plurality of input / output pads 2a are formed on the upper surface of the second semiconductor chip 2. The input / output pads 2a of the second semiconductor chip 2 are connected to each other by the bond fingers 12a on the upper surface of the circuit board 10 and the conductive wires 8.

또한, 상기 제2반도체칩(2) 및 그것에 연결된 도전성와이어(8)의 외주연인 회로기판(10) 상면에는 일정높이의 절연성댐(19)이 형성되어 있다. 상기 절연성댐(19)은 봉지재(18) 재질로 할 수 있다.In addition, an insulating dam 19 having a predetermined height is formed on the upper surface of the circuit board 10 that is the outer circumference of the second semiconductor chip 2 and the conductive wire 8 connected thereto. The insulating dam 19 may be made of an encapsulant 18.

더불어, 상기 절연성댐(19)의 상부에는 투명체의 글래스(22)가 부착되어 있으며, 따라서, 상기 제2반도체칩(2)은 CCD용 반도체칩으로 구비함이 바람직하다. 물론, 상기 글래스(22)에는 도시하지 않았지만 렌즈를 더 설치하여 그 수광율를 증가시킬 수 있다.In addition, the glass 22 of the transparent body is attached to the upper portion of the insulating dam 19, and therefore, the second semiconductor chip 2 is preferably provided as a CCD semiconductor chip. Of course, although not shown, the glass 22 may be further provided with a lens to increase its light receiving rate.

여기서, 제1반도체칩(1)의 전기적 신호는 도전성와이어(8), 회로패턴(12) 및 도전성볼(16)을 통하여 마더보드와 교신하게 되고, 제2반도체칩(2)의 전기적 신호는 도전성와이어(8), 회로기판(10) 상면의 회로패턴(12), 도전성 비아홀(13), 회로기판(10) 하면의 회로패턴(12) 및 도전성볼(16)을 통하여 마더보드와 교신하게 된 다.Here, the electrical signal of the first semiconductor chip 1 is in communication with the motherboard through the conductive wire 8, the circuit pattern 12 and the conductive ball 16, the electrical signal of the second semiconductor chip 2 The conductive wire 8, the circuit pattern 12 on the upper surface of the circuit board 10, the conductive via hole 13, the circuit pattern 12 and the conductive ball 16 on the lower surface of the circuit board 10 communicate with the motherboard. do.

상기와 같이 회로기판(10)을 중심으로 그 상,하면에 제1반도체칩(1) 및 제2반도체칩(2)이 위치됨으로써 종래와 동일하거나 또는 유사한 높이를 가지면서도 반도체칩이 적층된 형태의 반도체패키지를 구현하게 된다.As described above, the first semiconductor chip 1 and the second semiconductor chip 2 are positioned on the upper and lower surfaces of the circuit board 10 with the same or similar height as the conventional semiconductor chip. To implement the semiconductor package.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 반도체패키지에 의하면, 반도체패키지의 부피 특히 높이를 종래와 동일하게 유지하면서도 소위 적층된 형태의 반도체패키지를 구현함으로써 실장밀도를 높이는 동시에 반도체패키지의 고기능화를 구현할 수 있는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, while maintaining the volume, in particular, the height of the semiconductor package as in the prior art, by implementing a so-called stacked semiconductor package there is an effect that it is possible to increase the mounting density and high functionality of the semiconductor package.

또한, 상기 반도체패키지를 사용한 전자 부품은 그 크기를 더욱 소형화하는 동시에, 고기능화할 수 있는 효과도 있다.In addition, the electronic component using the semiconductor package has the effect of further downsizing the size and high functionality.

Claims (4)

삭제delete 하면에 다수의 입출력패드가 형성된 제1반도체칩과,A first semiconductor chip having a plurality of input / output pads formed on a lower surface thereof, 상기 제1반도체칩의 상면에 접착된 칩탑재판과, 상기 칩탑재판의 외주연에 방사상으로 형성된 다수의 내부리드 및 이것에 연결된 외부리드로 이루어진 리드프레임과,A lead frame comprising a chip mounting plate bonded to an upper surface of the first semiconductor chip, a plurality of inner leads radially formed on an outer circumference of the chip mounting plate, and an outer lead connected thereto; 상면에 다수의 입출력패드가 형성된 채, 상기 리드프레임의 칩탑재판 상면에 접착된 제2반도체칩과,A second semiconductor chip bonded to an upper surface of the chip mounting plate of the lead frame with a plurality of input / output pads formed on the upper surface; 상기 제1반도체칩 및 제2반도체칩의 입출력패드를 내부리드에 전기적으로 접속하는 도전성와이어와,Conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip to internal leads; 상기 리드프레임중 내부리드 하부의 제1반도체칩, 도전성와이어 등을 봉지하는 봉지재와,An encapsulant for encapsulating a first semiconductor chip, a conductive wire, and the like under the inner lead of the lead frame; 상기 리드프레임의 내부리드 상면에 형성된 절연성댐과,An insulating dam formed on an upper surface of the inner lead of the lead frame; 상기 절연성 댐상에 부착된 글래스를 포함하고,A glass attached to the insulating dam, 상기 리드프레임과 제2반도체칩 사이에는 수지층을 중심으로 상,하면에 회로패턴이 형성되어 이루어진 회로기판이 더 위치되어 있고, 상기 제2반도체칩의 입출력패드는 상기 회로기판의 회로패턴에 도전성와이어로 접속되어 있고, 상기 회로기판의 하면에 형성된 회로패턴은 선택된 내부리드에 전기적으로 접속된 것을 특징으로 하는 반도체패키지.A circuit board is formed between the lead frame and the second semiconductor chip with upper and lower circuit patterns formed on the resin layer, and the input / output pad of the second semiconductor chip is conductive to the circuit pattern of the circuit board. And a circuit pattern formed on a lower surface of the circuit board by a wire, and electrically connected to a selected internal lead. 제 2 항에 있어서, 상기 절연성 댐은 재질이 봉지재인 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 2, wherein the insulating dam is made of an encapsulant. 하면에 다수의 입출력패드가 형성된 제1반도체칩과,A first semiconductor chip having a plurality of input / output pads formed on a lower surface thereof, 상기 제1반도체칩의 상면에 그 외주연으로 확장된 채 접착된 수지층과, 상기 수지층의 상,하면에 본드핑거 및 볼랜드를 갖도록 형성된 다수의 도전성 회로패턴으로 이루어진 회로기판과,A circuit board comprising a resin layer bonded to the upper surface of the first semiconductor chip with its outer periphery extended, a plurality of conductive circuit patterns formed on the upper and lower surfaces of the resin layer to have bond fingers and ball lands; 상면에 다수의 입출력패드가 형성된 채 상기 회로기판의 상면 중앙에 접착된 제2반도체칩과,A second semiconductor chip bonded to the center of the upper surface of the circuit board with a plurality of input / output pads formed on the upper surface; 상기 제1반도체칩 및 제2반도체칩의 입출력패드를 회로기판의 본드핑거에 전기적으로 접속하는 도전성와이어와,Conductive wires electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip to the bond fingers of the circuit board; 상기 회로기판의 하부에 위치하는 제1반도체칩, 도전성와이어를 봉지하는 봉지재와,An encapsulant for encapsulating the first semiconductor chip and the conductive wire, which is located under the circuit board; 상기 회로기판의 상면중 본드핑거의 외주면에 형성된 절연성댐과,An insulating dam formed on an outer circumferential surface of a bond finger among upper surfaces of the circuit board; 상기 절연성 댐 상부에 부착된 글래스와,Glass attached to the insulating dam, 상기 회로기판 하면의 볼랜드에 융착된 도전성볼을 포함하여 이루어진 반도체패키지.A semiconductor package comprising a conductive ball fused to the ball land on the lower surface of the circuit board.
KR1020000046958A 2000-08-14 2000-08-14 Semiconductor package KR100600213B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000046958A KR100600213B1 (en) 2000-08-14 2000-08-14 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000046958A KR100600213B1 (en) 2000-08-14 2000-08-14 Semiconductor package

Publications (2)

Publication Number Publication Date
KR20020013287A KR20020013287A (en) 2002-02-20
KR100600213B1 true KR100600213B1 (en) 2006-07-13

Family

ID=19683104

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000046958A KR100600213B1 (en) 2000-08-14 2000-08-14 Semiconductor package

Country Status (1)

Country Link
KR (1) KR100600213B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100818083B1 (en) * 2005-12-23 2008-03-31 주식회사 하이닉스반도체 Stack type package
KR100833184B1 (en) * 2006-09-21 2008-05-28 삼성전자주식회사 Stacked semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227984A (en) * 1995-02-21 1996-09-03 Nec Corp Solid-state image pickup device
JPH0955489A (en) * 1995-08-11 1997-02-25 Sony Corp Solid-state image pick-up device
JPH0997888A (en) * 1995-09-29 1997-04-08 Sony Corp Optical device and manufacture thereof
US6034429A (en) * 1997-04-18 2000-03-07 Amkor Technology, Inc. Integrated circuit package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227984A (en) * 1995-02-21 1996-09-03 Nec Corp Solid-state image pickup device
JPH0955489A (en) * 1995-08-11 1997-02-25 Sony Corp Solid-state image pick-up device
JPH0997888A (en) * 1995-09-29 1997-04-08 Sony Corp Optical device and manufacture thereof
US6034429A (en) * 1997-04-18 2000-03-07 Amkor Technology, Inc. Integrated circuit package

Also Published As

Publication number Publication date
KR20020013287A (en) 2002-02-20

Similar Documents

Publication Publication Date Title
US6982488B2 (en) Semiconductor package and method for fabricating the same
KR100260997B1 (en) Semiconductor package
KR20030018204A (en) Multi chip package having spacer
KR20020015214A (en) Semiconductor package
KR100600213B1 (en) Semiconductor package
KR100400826B1 (en) semiconductor package
KR100549311B1 (en) Semiconductor package
KR100542673B1 (en) Semiconductor package
KR100646474B1 (en) Semiconductor package and its manufacturing method
KR100401018B1 (en) attaching method of wafer for semiconductor package
KR100600176B1 (en) Semiconductor package
KR100400827B1 (en) semiconductor package
KR100623317B1 (en) Semiconductor package
KR100399724B1 (en) Semiconductor package
KR100583493B1 (en) Semiconductor package
KR100542664B1 (en) Semiconductor package and its manufacturing method
KR100708052B1 (en) Semiconductor package
KR100381838B1 (en) Semiconductor package
KR100542672B1 (en) Semiconductor package
KR100369387B1 (en) semiconductor package and its manufacturing method
KR100729051B1 (en) Semiconductor package and its manufacturing method
KR100411808B1 (en) semiconductor package and its manufacturing method
KR100406447B1 (en) semiconductor package and its manufacturing method
KR20020077712A (en) Semiconductor package and its manufacturing method
KR20020029251A (en) Semiconductor package and its manufacturing method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130705

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20140704

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20150702

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20160704

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20170704

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20180702

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20190701

Year of fee payment: 14