KR100411808B1 - semiconductor package and its manufacturing method - Google Patents
semiconductor package and its manufacturing method Download PDFInfo
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- KR100411808B1 KR100411808B1 KR10-1999-0065926A KR19990065926A KR100411808B1 KR 100411808 B1 KR100411808 B1 KR 100411808B1 KR 19990065926 A KR19990065926 A KR 19990065926A KR 100411808 B1 KR100411808 B1 KR 100411808B1
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- semiconductor chip
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- semiconductor
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- resin layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 다수의 반도체칩을 적층한 상태로 패키징함으로써 고기능화 및 고용량화를 구현할 수 있도록, 중앙부에 관통부가 형성된 수지층을 중심으로, 상기 관통부 외주연의 수지층 상,하면에는 외측으로 오픈된 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀에 의해 상호 연결되어 있는 회로기판과; 상기 관통부에 상,하 방향으로 적층되어 위치되며, 각각의 일면에는 다수의 입출력패드가 형성된 적어도 2개 이상의 반도체칩과; 상기 각 반도체칩의 입출력패드와 회로기판의 각 본드핑거를 접속하는 도전성와이어와; 상기 각 반도체칩, 도전성와이어 및 관통부를 포함하는 회로기판의 일정 영역을 봉지하는 봉지재와; 상기 회로기판의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same. The number of outer periphery of the through part is mainly based on a resin layer having a through part formed in a central part to realize high functionality and capacity by packaging a plurality of semiconductor chips in a stacked state. Circuit patterns including a bond finger and a ball land opened outward on upper and lower surfaces of the strata, and the upper and lower circuit patterns are connected to each other by conductive via holes; At least two semiconductor chips stacked on the penetrating portion in an up and down direction, each of which has a plurality of input / output pads; Conductive wires connecting the input / output pads of the semiconductor chips and the bond fingers of the circuit boards; An encapsulant for encapsulating a predetermined area of the circuit board including the semiconductor chip, the conductive wire, and the through part; It characterized in that it comprises a plurality of conductive balls fused to the ball land of the circuit board.
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 다수의 반도체칩을 적층한 상태로 패키징함으로써 고기능화 및 고용량화를 구현할 수 있는 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same, which can realize high functionality and high capacity by packaging a plurality of semiconductor chips in a stacked state.
최근의 전자기기 예를 들면, 휴대폰, 셀룰러 폰, 노트북 등의 마더보드에는 많은 수의 반도체칩들이 패키징되어 최소시간내에 그것들이 다기능을 수행할 수 있도록 설계되는 동시에, 상기 반도체칩을 패키징한 반도체패키지 및 상기 반도체패키지들이 실장되는 전자기기도 소형화되어 가는 추세에 있다. 더불어 최근의 반도체패키지는 그 두께를 초박형화하기 위해 회로기판에 관통된 관통부를 형성하고 상기 관통부 내측에 반도체칩을 탑재한 반도체패키지도 제조되고 있다.In recent years, a large number of semiconductor chips are packaged on a motherboard such as a mobile phone, a cellular phone, a notebook computer, and designed to perform multifunction in a minimum time, and at the same time, a semiconductor package packaging the semiconductor chip. In addition, electronic devices on which the semiconductor packages are mounted are also becoming smaller. In addition, in recent years, in order to reduce the thickness of the semiconductor package, a semiconductor package having a penetrating portion formed on a circuit board and a semiconductor chip mounted therein has been manufactured.
이러한 반도체패키지(100')로서 도1을 참조하여 그 구조를 설명하면 다음과 같다.The structure of the semiconductor package 100 'will be described with reference to FIG.
도시된 바와 같이 상면에 다수의 입출력패드(4')가 형성되어 있는 반도체칩(2')이 구비되어 있고, 상기 반도체칩(2')의 외주연으로는 그 반도체칩(2')이 위치할 수 있도록 관통부(27')가 형성된 회로기판(20')이 위치되어 있다. 상기 회로기판(20')은 수지층(21')을 기본층으로 하여 그 상면에 다수의 본드핑거(22') 및 볼랜드(23')로 이루어진 회로패턴이 형성되어 있고, 상기 회로패턴의 표면은 본드핑거(22') 및 볼랜드(23')가 상부 방향으로 오픈되도록커버커트(24')가 코팅되어 있다. 상기 반도체칩(2')의 입출력패드(4')와 상기 회로기판(20')의 본드핑거(22')는 전기적으로 접속되도록 도전성와이어(30')에 의해 상호 접속되어 있다. 또한, 상기 회로기판(20')의 관통부(27') 내측에 위치된 반도체칩(2'), 도전성와이어(30') 등을 외부 환경으로부터 보호할 수 있도록 봉지재(40')가 충진되어 있으며, 마지막으로 상기 회로기판(20')의 볼랜드(23')에는 각각 도전성볼(50')이 융착되어 차후 마더보드에 실장 가능한 형태로 되어 있다.As shown in the drawing, a semiconductor chip 2 'having a plurality of input / output pads 4' is formed on an upper surface thereof, and the semiconductor chip 2 'is positioned at an outer circumference of the semiconductor chip 2'. The circuit board 20 'having the through portion 27' is located thereon. The circuit board 20 'is formed of a resin layer 21' as a base layer, and a circuit pattern formed of a plurality of bond fingers 22 'and borland 23' is formed on an upper surface thereof, and the surface of the circuit pattern is formed. The cover cut 24 ′ is coated so that the silver bond finger 22 ′ and the ball land 23 ′ open upward. The input / output pads 4 'of the semiconductor chip 2' and the bond fingers 22 'of the circuit board 20' are connected to each other by conductive wires 30 'so as to be electrically connected. In addition, the encapsulant 40 'is filled to protect the semiconductor chip 2', the conductive wire 30 ', and the like located inside the through part 27' of the circuit board 20 'from the external environment. Finally, the conductive balls 50 'are fused to the ball lands 23' of the circuit board 20 'so that they can be mounted on the motherboard later.
그러나, 이러한 종래의 반도체패키지는 회로기판의 관통부에 단 한 개의 반도체칩만을 탑재함으로써, 그 반도체패키지의 고밀도화, 고기능화 및 고용량화에 한계가 있는 문제점이 있다.However, such a conventional semiconductor package has a problem in that only one semiconductor chip is mounted in the penetrating portion of the circuit board, thereby limiting the density, high functionality and high capacity of the semiconductor package.
더욱이, 상기 회로기판의 관통부에 탑재되는 반도체칩이 메모리칩(예를 들면, Flash 메모리 또는 SRAM 등등)일 경우에는, 다수의 반도체패키지를 마더보드에 실장하여야 함으로써 그 실장밀도를 극히 저하시키는 문제점이 있다.Furthermore, in the case where the semiconductor chip mounted on the penetrating portion of the circuit board is a memory chip (for example, a flash memory or an SRAM, etc.), it is necessary to mount a plurality of semiconductor packages on the motherboard, thereby greatly reducing the mounting density thereof. There is this.
또한, 최근의 반도체패키지는 특별한 사용자를 위해 개발된 주문형 반도체칩(ASIC; Application Specific Integrated Circuit)과 메모리용 반도체칩을 동시에 패키징한 반도체패키지를 요구하고 있으나, 이러한 요구에 부응하지 못하는 실정이다.In addition, recent semiconductor packages require a semiconductor package that simultaneously packaged an application specific integrated circuit (ASIC) developed for a particular user and a semiconductor chip for a memory, but does not meet these requirements.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 회로기판의 관통부에 다수의 반도체칩을 적층한 채 탑재함으로써 고밀도화, 고기능화 및 고용량화한 반도체패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a semiconductor package having high density, high functionality, and high capacity by mounting a plurality of semiconductor chips stacked on the penetrating portion of a circuit board.
더불어, 본 발명의 다른 목적은 상기와 같이 고밀도화, 고기능화 및 고용량화한 반도체패키지의 제조 방법을 제공하는데 있다.In addition, another object of the present invention is to provide a method for manufacturing a semiconductor package having a high density, high functionality and high capacity as described above.
도1은 종래의 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package.
도2a 내지 도2c는 본 발명에 의한 반도체패키지를 도시한 단면도이다.2A to 2C are cross-sectional views showing a semiconductor package according to the present invention.
도3a 내지 도3g는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 단면도이다.3A to 3G are cross-sectional views illustrating a method for manufacturing a semiconductor package according to the present invention.
도4a 내지 도4g는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 단면도이다.4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
101, 102, 103; 본 발명에 의한 반도체패키지101, 102, 103; Semiconductor package according to the present invention
1,2,3,4; 제1,2,3,4반도체칩 1a,2a,3a,4a; 입출력패드1,2,3,4; First, second, third, and fourth semiconductor chips 1a, 2a, 3a, and 4a; I / O pad
10; 회로기판 11; 수지층10; Circuit board 11; Resin layer
12; 본드핑거 13; 볼랜드12; Bondfinger 13; Borland
14; 도전성비아홀 15; 커버코트14; Conductive via holes 15; Cover coat
16; 관통부 17; 댐16; Penetration 17; dam
20; 도전성와이어 31,32; 제1,2봉지재20; Conductive wires 31,32; First and second encapsulation material
40; 도전성볼40; Conductive ball
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 중앙부에 관통부가 형성된 수지층을 중심으로, 상기 관통부 외주연의 수지층 상,하면에는 외측으로 오픈된 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀에 의해 상호 연결되어 있는 회로기판과; 상기 관통부에 상,하 방향으로 적층되어 위치되며, 각각의 일면에는 다수의 입출력패드가 형성된 적어도 2개 이상의 반도체칩과; 상기 각 반도체칩의 입출력패드와 회로기판의 각 본드핑거를 접속하는 도전성와이어와; 상기 각 반도체칩, 도전성와이어 및 관통부를 포함하는 회로기판의 일정 영역을 봉지하는 봉지재와; 상기 회로기판의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention has a circuit pattern including a bond finger and a ball land that are opened outwardly on the bottom and bottom surfaces of the resin layer of the outer periphery of the resin layer, with the through portion formed at the center thereof. And circuit patterns formed on the upper and lower surfaces of the circuit board are interconnected by conductive via holes; At least two semiconductor chips stacked on the penetrating portion in an up and down direction, each of which has a plurality of input / output pads; Conductive wires connecting the input / output pads of the semiconductor chips and the bond fingers of the circuit boards; An encapsulant for encapsulating a predetermined area of the circuit board including the semiconductor chip, the conductive wire, and the through part; It characterized in that it comprises a plurality of conductive balls fused to the ball land of the circuit board.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 중앙부에 관통부가 형성된 수지층을 중심으로, 상기 관통부 외주연의 수지층 상,하면에는 외측으로 오픈된 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀에 의해 상호 연결되어 있는 회로기판과; 상기 회로기판의 관통부 내측에 위치되어 있되, 다수의 입출력패드가 하방을 향하는 제1반도체칩과; 상기 제1반도체칩의 상면에 접착되어 있되, 다수의 입출력패드가 상방을 향하여 형성된 제2반도체칩과; 상기 제1,2반도체칩의 입출력패드와 회로기판의 상,하면에 형성된 본드핑거를 각각 접속하는 다수의 도전성와이어와; 상기 제1반도체칩 및 관통부를 포함하는 회로기판의 하면 일정영역을 봉지하는 제1봉지재와; 상기 제2반도체칩 및 관통부를 포함하는 회로기판의 상면 일정영역을 봉지하는 제2봉지재와; 상기 회로기판의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In addition, in order to achieve the above object, the semiconductor package according to the present invention includes a bond finger and a ball land that are opened outwardly on the lower and upper surfaces of the resin layer of the outer periphery of the resin layer with a through portion formed in a central portion thereof. Circuit patterns are formed, and the upper and lower circuit patterns are connected to each other by conductive via holes; A first semiconductor chip positioned inside the through part of the circuit board and having a plurality of input / output pads facing downward; A second semiconductor chip attached to an upper surface of the first semiconductor chip and having a plurality of input / output pads facing upwards; A plurality of conductive wires respectively connecting the input / output pads of the first and second semiconductor chips and bond fingers formed on upper and lower surfaces of the circuit board; A first encapsulation material encapsulating a predetermined region of a lower surface of the circuit board including the first semiconductor chip and the through part; A second encapsulation material encapsulating a predetermined region of an upper surface of the circuit board including the second semiconductor chip and the through part; It characterized in that it comprises a plurality of conductive balls fused to the ball land of the circuit board.
여기서, 상기 제2반도체칩의 상면에는 제3반도체칩이 더 부착되고, 상기 제3반도체칩은 도전성와이어에 의해 회로기판의 본드핑거에 접속된다.Here, a third semiconductor chip is further attached to the upper surface of the second semiconductor chip, and the third semiconductor chip is connected to the bond finger of the circuit board by conductive wires.
또한, 상기 제1반도체칩의 하면에는 제4반도체칩이 더 부착되고, 상기 제4반도체칩은 도전성와이어에 의해 회로기판의 본드핑거에 접속된다.In addition, a fourth semiconductor chip is further attached to the lower surface of the first semiconductor chip, and the fourth semiconductor chip is connected to the bond finger of the circuit board by conductive wires.
또한, 상기 제1봉지재는 액상봉지재이고, 제2봉지재는 에폭시몰딩컴파운드로 함이 바람직하다.In addition, the first encapsulating material is a liquid encapsulating material, it is preferable that the second encapsulating material is an epoxy molding compound.
또한, 상기 회로기판의 상면으로서 관통부의 외주연에는 제2반도체칩을 제1반도체칩에 접착시키는 접착제가 흘러 넘치지 않토록 일정 높이의 댐을 더 형성함이 바람직하다.In addition, it is preferable that a dam having a predetermined height is further formed on the outer circumference of the penetrating portion as an upper surface of the circuit board so that an adhesive for adhering the second semiconductor chip to the first semiconductor chip does not overflow.
또한 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 중앙부에 관통부가 형성된 수지층을 중심으로, 상기 관통부 외주연의 수지층 상,하면에는 외측으로 오픈된 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀에 의해 상호 연결되어 있는 회로기판을 제공하는 단계와; 상기 회로기판의 관통부 내측에 다수의 입출력패드가 하방을 향하여 형성된 제1반도체칩을 위치시키고, 상기 제1반도체칩의 입출력패드와 회로기판의 본드핑거를 도전성와이어로 상호 접속시키는 단계와; 상기 제1반도체칩및 관통부를 포함하는 회로기판의 하면 일정 영역을 봉지재로 봉지하는 제1봉지 단계와; 상기 제1반도체칩의 상면에 입출력패드가 상방을 향하여 형성된 제2반도체칩을 접착시키고, 상기 제2반도체칩의 입출력패드와 회로기판의 본드핑거를 도전성와이어로 상호 접속시키는 단계와; 상기 제2반도체칩 및 관통부를 포함하는 회로기판의 상면 일정 영역을 봉지재로 봉지하는 제2봉지 단계와; 상기 회로기판의 볼랜드에 다수의 도전성볼을 융착하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object is centered around the resin layer formed in the penetrating portion in the center, the bond finger and the ball land opened on the outer surface on the bottom of the outer periphery of the penetrating portion Providing a circuit board including a circuit pattern, wherein the upper and lower circuit patterns are interconnected by conductive via holes; Positioning a first semiconductor chip having a plurality of input / output pads facing downwards in a through portion of the circuit board, and interconnecting the input / output pad of the first semiconductor chip and the bond finger of the circuit board with conductive wires; A first encapsulation step of encapsulating a predetermined area of a lower surface of the circuit board including the first semiconductor chip and the through part with an encapsulant; Adhering a second semiconductor chip having an input / output pad facing upward on an upper surface of the first semiconductor chip, and interconnecting a bond finger of the input / output pad of the second semiconductor chip and a circuit board with conductive wires; A second encapsulation step of encapsulating a predetermined region of the upper surface of the circuit board including the second semiconductor chip and the through part with an encapsulant; And fusion bonding a plurality of conductive balls to the ball lands of the circuit board.
여기서, 상기 회로기판의 관통부에 제1반도체칩을 위치시키는 단계는 적어도 2개 이상의 반도체칩을 적층한 채로 위치시킬 수 있다.Here, in the step of placing the first semiconductor chip in the penetrating portion of the circuit board, at least two or more semiconductor chips may be placed in a stack.
또한, 상기 제2반도체칩을 접착시키는 단계는 적어도 2개 이상의 반도체칩을 적층한 채로 접착시킬 수도 있다.In addition, the bonding of the second semiconductor chip may be performed while stacking at least two semiconductor chips.
또한, 상기 회로기판의 관통부에 제1반도체칩을 위치시키는 단계후에 또다른 반도체칩을 상기 제1반도체칩의 하면에 부착시킬 수도 있다.In addition, another semiconductor chip may be attached to the lower surface of the first semiconductor chip after the step of placing the first semiconductor chip in the penetrating portion of the circuit board.
또한, 상기 제2반도체칩을 접착시키는 단계후에 또다른 반도체칩을 상기 제2반도체칩의 상면에 부착시킬 수도 있다.In addition, after the step of adhering the second semiconductor chip, another semiconductor chip may be attached to the upper surface of the second semiconductor chip.
상기한 목적을 달성하기 위해 본 발명에 의한 또 다른 반도체패키지의 제조 방법은 중앙부에 관통부가 형성된 수지층을 중심으로, 상기 관통부 외주연의 수지층 상,하면에는 외측으로 오픈된 본드핑거 및 볼랜드를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀에 의해 상호 연결되어 있는 회로기판을 제공하는 단계와; 상기 회로기판의 관통부 상면에 상방을 향해 적어도 한 개 이상의 반도체칩을 접착시키고, 상기 반도체칩의 입출력패드와 회로기판의본드핑거를 도전성와이어로 상호 접속시키는 단계와; 상기 회로기판의 관통부 상면 및 상기 반도체칩을 봉지재로 봉지하는 제1봉지 단계와; 상기 반도체칩의 하면인 회로기판의 관통부 내측에 다수의 입출력패드가 하방을 향하여 형성된 적어도 한 개 이상의 반도체칩을 위치시키고, 상기 반도체칩의 입출력패드와 회로기판의 본드핑거를 도전성와이어로 상호 접속시키는 단계와; 상기 반도체칩 및 관통부를 포함하는 회로기판의 하면 일정 영역을 봉지재로 봉지하는 제2봉지 단계와; 상기 회로기판의 볼랜드에 다수의 도전성볼을 융착하는 단계를 포함하여 이루어진 것을 특징으로 한다.Another method of manufacturing a semiconductor package according to the present invention in order to achieve the above object is a bond finger and a borland opened outward on the bottom and the bottom of the resin layer of the outer periphery of the resin layer formed around the center portion of the through portion Providing a circuit board including a circuit pattern, wherein the upper and lower circuit patterns are interconnected by conductive via holes; Bonding at least one semiconductor chip upwardly on an upper surface of the through part of the circuit board, and interconnecting the input / output pad of the semiconductor chip and the bond finger of the circuit board with conductive wires; A first encapsulation step of encapsulating the upper surface of the through part of the circuit board and the semiconductor chip with an encapsulant; Place at least one semiconductor chip formed with a plurality of input / output pads facing downward inside the through part of the circuit board, which is a lower surface of the semiconductor chip, and interconnect the bond fingers of the input / output pad of the semiconductor chip and the circuit board with conductive wires. Making a step; A second encapsulation step of encapsulating a predetermined area of a lower surface of the circuit board including the semiconductor chip and the through part with an encapsulant; And fusion bonding a plurality of conductive balls to the ball lands of the circuit board.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 회로기판의 관통부에 다수의 반도체칩이 상,하방향으로 적층된 채 탑재됨으로써, 그 반도체패키지의 고밀도화, 기능화 및 고용량화를 구현할 수 있게 된다.As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, a plurality of semiconductor chips are mounted in the penetrating portion of the circuit board in the vertical direction, thereby realizing high density, functionalization and high capacity of the semiconductor package. It becomes possible.
더욱이, 상기 반도체칩이 메모리용 반도체칩일 경우에는 상기 반도체패키지의 용량을 최소의 면적하에서 최대로 확보할 수 있게 된다.In addition, when the semiconductor chip is a semiconductor chip for memory, the capacity of the semiconductor package can be secured to the maximum under a minimum area.
더불어, 주문형 반도체칩과 메모리용 반도체칩을 동시에 탑재할 수 있게 되므로, 대부분의 전기적 기능을 하나의 반도체패키지로서 해결할 수 있는 가능성이 있다.In addition, since the on-demand semiconductor chip and the memory semiconductor chip can be mounted at the same time, there is a possibility that most electrical functions can be solved as one semiconductor package.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 내지 도2c는 본 발명에 의한 반도체패키지(101,102,103)를 도시한 단면도이다.2A to 2C are cross-sectional views showing semiconductor packages 101, 102 and 103 according to the present invention.
먼저 도2a에 도시된 바와 같이, 반도체칩과 마더보드 사이에서 신호 전달 기능을 갖는 회로기판(10)이 구비되어 있다. 상기 회로기판(10)은 중앙부에 관통부(16)가 형성된 수지층(11)을 중심으로, 상기 관통부(16)의 외주연인 수지층(11)의 상,하면에 다수의 본드핑거(12) 및 볼랜드(13)를 포함하는 회로패턴이 형성되어 있다. 이를 좀더 자세히 설명하면, 수지층(11)의 상면에는 본드핑거(12)를 갖는 회로패턴이 형성되고, 수지층(11)의 하면에는 본드핑거(12) 및 볼랜드(13)를 갖는 회로패턴이 형성되어 있다. 또한, 상기 수지층(11)의 상,하면에 형성된 회로패턴은 도전성비아홀(14)에 의해 상호 접속되어 있다. 또한, 상기 수지층(11) 상,하면에는 상기 회로패턴중 본드핑거(12) 및 볼랜드(13)가 외측으로 오픈된 채 일정 두께의 커버코트(15)가 코팅되어 그 회로패턴을 외부 환경으로부터 보호할 수 있도록 되어 있다.First, as shown in FIG. 2A, a circuit board 10 having a signal transfer function between a semiconductor chip and a motherboard is provided. The circuit board 10 has a plurality of bond fingers 12 formed on the upper and lower surfaces of the resin layer 11, which is the outer circumference of the through portion 16, centering on the resin layer 11 having the through portion 16 formed at a central portion thereof. ) And a ball land 13 are formed. In more detail, a circuit pattern having a bond finger 12 is formed on an upper surface of the resin layer 11, and a circuit pattern having a bond finger 12 and a ball land 13 is formed on a lower surface of the resin layer 11. Formed. In addition, circuit patterns formed on the upper and lower surfaces of the resin layer 11 are interconnected by conductive via holes 14. In addition, a cover coat 15 having a predetermined thickness is coated on the resin layer 11 while the bond finger 12 and the ball land 13 of the circuit patterns are opened outward, and the circuit pattern is removed from the external environment. It is intended to protect.
상기 회로기판(10)의 관통부(16) 내측에는 다수의 입출력패드(1a)가 하방을 향하여 형성된 제1반도체칩(1)이 위치되어 있다.The first semiconductor chip 1 having a plurality of input / output pads 1a facing downward is positioned inside the through part 16 of the circuit board 10.
상기 제1반도체칩(1)의 상면에는 접착제에 의해 제2반도체칩(2)이 접착되어 있다. 상기 제2반도체칩(2)은 상방을 향하여 다수의 입출력패드(2a)가 형성되어 있다.The second semiconductor chip 2 is bonded to the upper surface of the first semiconductor chip 1 with an adhesive. The second semiconductor chip 2 is provided with a plurality of input / output pads 2a facing upward.
또한, 상기 회로기판(10)의 관통부(16) 외주연인 상면에는 상기 제2반도체칩(2)을 제1반도체칩(1)에 접착시키는 접착제가 본드핑거(12)를 오염시키지 않토록 일정 높이의 댐(17)이 형성되어 있다. 상기 댐(17)은 통상적인 커버코트재질과 동일한 것으로 형성함이 바람직하다.In addition, an adhesive for adhering the second semiconductor chip 2 to the first semiconductor chip 1 on the outer circumferential edge of the penetrating portion 16 of the circuit board 10 is fixed so as not to contaminate the bond finger 12. The dam 17 of height is formed. The dam 17 is preferably formed of the same material as a conventional cover coat material.
또한, 상기 제2반도체칩(2)의 상면에는 그 제2반도체칩(2)의 크기보다 작은 크기를 갖는 제3반도체칩(3)이 부착될 수 있지만, 이것으로 본 발명을 한정하는 것은 아니다. 물론, 상기 제3반도체칩(3)의 상면에는 다수의 입출력패드(3a)가 형성되어 있다.In addition, a third semiconductor chip 3 having a size smaller than that of the second semiconductor chip 2 may be attached to an upper surface of the second semiconductor chip 2, but the present invention is not limited thereto. . Of course, a plurality of input / output pads 3a are formed on the top surface of the third semiconductor chip 3.
상기 제1,2,3반도체칩(1,2,3)의 각 입출력패드(1a,2a,3a)는 회로기판(10)의 상,하면에 형성된 본드핑거(12)에 알루미늄와이어 또는 골드와이어와 같은 도전성와이어(20)에 의해 상호 접속되어 있다. 즉, 제1반도체칩(1)의 입출력패드(1a)는 회로기판(10)의 하면에 형성된 본드핑거(12)와 접속되어 있고, 제2,3반도체칩(2,3)의 입출력패드(2a,3a)는 회로기판(10)의 상면에 형성된 본드핑거(12)와 접속되어 있다.Each of the input / output pads 1a, 2a, 3a of the first, second, and third semiconductor chips 1, 2, and 3 is formed of aluminum wire or gold wire on the bond fingers 12 formed on the upper and lower surfaces of the circuit board 10. The conductive wires 20 are connected to each other by the same. That is, the input / output pad 1a of the first semiconductor chip 1 is connected to the bond finger 12 formed on the bottom surface of the circuit board 10, and the input / output pads of the second and third semiconductor chips 2 and 3 ( 2a and 3a are connected to the bond fingers 12 formed on the upper surface of the circuit board 10.
상기 제1,2,3반도체칩(1,2,3) 및 관통부(16)를 포함하는 회로기판(10)의 상,하면 일정 영역은 봉지재로 봉지되어 있다. 이를 좀더 자세히 설명하면, 상기 제1반도체칩(1) 및 관통부(16) 내측을 포함하는 회로기판(10)의 하면 일정 영역(볼랜드(13)를 침범하지 않는 범위)은 제1봉지재(31) 바람직하기로는 액상봉지재로 봉지되어 있다. 그러나 여기서 상기 제1봉지재(31)를 액상봉지재로 한정하는 것은 아니다. 또한, 상기 제2,3반도체칩(2,3) 및 관통부(16)를 포함하는 회로기판(10)의 상면 일정 영역은 제2봉지재(32) 바람직하로는 에폭시몰딩컴파운드로 봉지되어 있다. 그러나 여기서 상기 제2봉지재(32)를 에폭시몰딩컴파운드로 한정하는 것은 아니다.The upper and lower surfaces of the circuit board 10 including the first, second and third semiconductor chips 1, 2 and 3 and the penetrating portion 16 are encapsulated with an encapsulant. In more detail, the lower surface of the circuit board 10 including the first semiconductor chip 1 and the penetrating portion 16 (the range that does not invade the borland 13) is defined by the first encapsulant ( 31) It is preferably encapsulated with a liquid encapsulant. However, the first encapsulant 31 is not limited to the liquid encapsulant. In addition, a predetermined region of the upper surface of the circuit board 10 including the second and third semiconductor chips 2 and 3 and the penetrating portion 16 is encapsulated with a second encapsulant 32, preferably an epoxy molding compound. . However, the second encapsulant 32 is not limited to the epoxy molding compound.
여기서, 도2b의 반도체패키지(102)에서와 같이 상기 제2봉지재(32)는 회로기판(10)의 상면 전체를 봉지할 수도 있으나, 이를 한정하는 것은 아니다.Here, the second encapsulant 32 may encapsulate the entire upper surface of the circuit board 10 as in the semiconductor package 102 of FIG. 2B, but is not limited thereto.
마지막으로, 상기 회로기판(10)의 볼랜드(13) 즉, 회로기판(10)의 하면에 형성된 볼랜드(13)에는 솔더볼과 같은 도전성볼(40)이 융착되어 있음으로써, 이 도전성볼(40)이 마더보드의 소정 패턴에 융착되어 실장 가능하게 되어 있다.Finally, the conductive balls 40 such as solder balls are fused to the ball lands 13 of the circuit board 10, that is, the ball lands 13 formed on the bottom surface of the circuit board 10. The motherboard is fused to a predetermined pattern and can be mounted.
한편, 도2c의 반도체패키지(103)에서와 같이 상기 제1반도체칩(1)의 하면에는 제4반도체칩(4)이 부착될 수 있으나, 여기서 이를 한정하는 것은 아니다. 상기 제4반도체칩(4) 역시 하방을 향하여 다수의 입출력패드(4a)가 형성되어 있으며, 이 입출력패드(4a)는 도전성와이어(20)에 의해 회로기판(10)의 하면에 형성된 본드핑거(12)에 연결된다.Meanwhile, as shown in the semiconductor package 103 of FIG. 2C, a fourth semiconductor chip 4 may be attached to the bottom surface of the first semiconductor chip 1, but is not limited thereto. The fourth semiconductor chip 4 also has a plurality of input / output pads 4a facing downward, and the input / output pads 4a are bonded fingers formed on the bottom surface of the circuit board 10 by the conductive wires 20. 12).
도3a 내지 도3g는 본 발명에 의한 반도체패키지(101)의 제조 방법을 도시한 단면도이다.3A to 3G are sectional views showing the manufacturing method of the semiconductor package 101 according to the present invention.
먼저 도3a에 도시된 바와 같이 중앙부에 관통부(16)가 형성된 수지층(11)을 중심으로, 상기 관통부(16) 외주연의 수지층(11) 상,하면에는 본드핑거(12) 및 볼랜드(13)를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀(14)에 의해 상호 연결되어 있는 회로기판(10)을 제공한다.First, as shown in FIG. 3A, the bond finger 12 and the upper and lower surfaces of the resin layer 11 of the outer periphery of the penetrating portion 16 are formed around the resin layer 11 having the penetrating portion 16 formed at the center thereof. A circuit pattern including a ball land 13 is formed, and the upper and lower circuit patterns provide a circuit board 10 interconnected by conductive via holes 14.
이때, 상기 관통부(16)의 상면에는 그 관통부(16)를 폐쇄하는 필름(18)을 접착함으로써, 차후 반도체칩(1,2,3)이 용이하게 안착 또는 접착되도록 할 수 있다. 또한, 상기 관통부(16)의 외주연 근방인 회로기판(10)의 상면에는 일정높이의 댐(17)을 형성하여 차후 접착제가 본드핑거(12)를 오염시키기 않토록 함이 바람직하다.In this case, the upper surface of the through part 16 may be adhered to the film 18 which closes the through part 16, so that the semiconductor chips 1, 2, and 3 may be easily seated or adhered. In addition, it is preferable that a dam 17 having a predetermined height is formed on the upper surface of the circuit board 10 near the outer periphery of the penetrating portion 16 to prevent the adhesive from contaminating the bond finger 12.
이어서, 도3b에 도시된 바와 같이 회로기판(10)의 관통부(16) 내측에 제1반도체칩(1)을 접착시키고, 이어서 도전성와이어(20)를 이용하여 회로기판(10) 하면에 형성된 본드핑거(12)와 접속한다.Subsequently, as illustrated in FIG. 3B, the first semiconductor chip 1 is bonded to the inside of the through part 16 of the circuit board 10, and then formed on the bottom surface of the circuit board 10 using the conductive wires 20. It is connected to the bond finger 12.
이때, 상기 제1반도체칩(1)의 하면에는 또다른 반도체칩(도시되지 않음)을 접착시켜 일체화한 후 탑재할 수도 있고, 상기 제1반도체칩(1)을 탑재한 후, 그 제1반도체칩(1)의 하면에 다른 반도체칩을 접착시킬 수도 있다.At this time, another semiconductor chip (not shown) may be bonded and integrated on the bottom surface of the first semiconductor chip 1, or after mounting the first semiconductor chip 1, the first semiconductor chip may be mounted. Another semiconductor chip may be bonded to the lower surface of the chip 1.
이어서, 도3c에 도시된 봐와 같이 상기 제1반도체칩(1) 및 관통부(16)를 포함하는 회로기판(10)의 하면 일정 영역을 제1봉지재(31)로 봉지한다. 이때, 상기 제1봉지재(31)는 액상봉지재를 이용함이 바람직하지만 이것으로 한정하는 것은 아니다.Subsequently, as shown in FIG. 3C, a predetermined region of the lower surface of the circuit board 10 including the first semiconductor chip 1 and the penetrating portion 16 is sealed with the first encapsulant 31. At this time, the first encapsulant 31 is preferably a liquid encapsulant, but is not limited thereto.
이어서, 도3d에 도시된 바와 같이 상기 제1반도체칩(1)의 상면에 입출력패드(2a)가 상방을 향하여 형성된 제2반도체칩(2)을 접착제를 이용하여 접착시킨다.Subsequently, as illustrated in FIG. 3D, the second semiconductor chip 2 having the input / output pad 2a facing upward is adhered to the upper surface of the first semiconductor chip 1 using an adhesive.
이때 상기 제2반도체칩(2)의 상면에는 제3반도체칩(3)이 접착된 상태로서, 상기 제2,3반도체칩(2,3)을 일체화하여 접착시킬 수 있다. 또한, 상기 제2반도체칩(2)을 제1반도체칩(1)의 상면에 접착시키고, 상기 제2반도체칩(2)의 상면에 제3반도체칩(3)을 접착시킬 수도 있다.In this case, the third semiconductor chip 3 is bonded to the upper surface of the second semiconductor chip 2, and the second and third semiconductor chips 2 and 3 may be integrally bonded to each other. In addition, the second semiconductor chip 2 may be bonded to the upper surface of the first semiconductor chip 1, and the third semiconductor chip 3 may be attached to the upper surface of the second semiconductor chip 2.
계속해서, 도3e에 도시된 바와 같이 상기 제2반도체칩(2)(및 제3반도체칩(3))의 입출력패드(2a)와 회로기판(10) 상면에 형성된 본드핑거(12)를 도전성와이어(20)를 이용하여 상호 접착시킨다.Subsequently, as illustrated in FIG. 3E, the bond fingers 12 formed on the upper and lower surfaces of the input / output pad 2a and the circuit board 10 of the second semiconductor chip 2 (and the third semiconductor chip 3) are electrically conductive. The wires 20 are bonded to each other using the wires 20.
이어서, 상기 관통부(16)의 상면에 위치된 제2반도체칩(2) 및 제3반도체칩(3)을 제2봉지재(32)로 봉지한다. 여기서, 상기 제2봉지재(32)는 에폭시몰딩컴파운드가 바람직하지만 이것으로만 본 발명을 한정하는 것은 아니다.Subsequently, the second semiconductor chip 2 and the third semiconductor chip 3 positioned on the upper surface of the through part 16 are encapsulated with the second encapsulant 32. Here, the second encapsulant 32 is preferably an epoxy molding compound, but this does not limit the present invention.
마지막으로, 도3g에 도시된 바와 같이 상기 회로기판(10)의 볼랜드(13)에 솔더볼과 같은 도전성볼(40)을 융착시킴으로써, 이 반도체패키지(101)가 마더보드에 실장 가능한 형태가 되도록 한다.Finally, as shown in FIG. 3G, the conductive balls 40 such as solder balls are fused to the ball lands 13 of the circuit board 10 so that the semiconductor package 101 can be mounted on the motherboard. .
도4a 내지 도4g는 본 발명에 의한 반도체패키지(101)의 다른 제조 방법을 도시한 단면도이다.4A to 4G are cross-sectional views showing another manufacturing method of the semiconductor package 101 according to the present invention.
먼저 도4a에 도시된 바와 같이, 중앙부에 관통부(16)가 형성된 수지층(11)을 중심으로, 상기 관통부(16) 외주연의 수지층(11) 상,하면에는 외측으로 오픈된 본드핑거(12) 및 볼랜드(13)를 포함하는 회로패턴이 형성되어 있고, 상기 상,하면의 회로패턴은 도전성비아홀(14)에 의해 상호 연결되어 있는 회로기판(10)을 제공한다.First, as shown in FIG. 4A, a bond is opened outwardly on the lower and upper surfaces of the resin layer 11 of the outer periphery of the through portion 16, centering on the resin layer 11 having the through portion 16 formed at the center thereof. A circuit pattern including a finger 12 and a ball land 13 is formed, and the upper and lower circuit patterns provide a circuit board 10 interconnected by conductive via holes 14.
이어서, 도4b에 도시된 바와 같이 상기 회로기판(10)의 관통부(16)를 포함하는 회로기판(10)의 상면에 제2,3반도체칩(2,3)을 접착시키고, 상기 제2,3반도체칩(2,3)의 입출력패드(2a,3a)와 회로기판(10)의 본드핑거(12)를 도전성와이어(20)로 상호 접속시킨다.Subsequently, as shown in FIG. 4B, the second and third semiconductor chips 2 and 3 are bonded to the upper surface of the circuit board 10 including the penetrating portion 16 of the circuit board 10. The input / output pads 2a and 3a of the three semiconductor chips 2 and 3 and the bond fingers 12 of the circuit board 10 are interconnected by conductive wires 20.
이어서, 도4c에 도시된 바와 같이 상기 관통부(16)의 상면 일정영역과 제2,3반도체칩(2,3)을 봉지재(제2봉지재(32))로 봉지한다.Subsequently, as shown in FIG. 4C, a predetermined region of the upper surface of the penetrating portion 16 and the second and third semiconductor chips 2 and 3 are encapsulated with an encapsulant (second encapsulant 32).
이어서, 도4d에 도시된 바와 같이 상기 제2,3반도체칩(2,3)의 하면인 회로기판(10)의 관통부(16) 내측에 다수의 입출력패드(1a)가 하방을 향하여 형성된 제1반도체칩(1)(또는 제1반도체칩(1) 하면에 제4반도체칩(도시되지 않음)이 부착된 것)을 부착시키고, 상기 제1반도체칩(1)의 입출력패드(1a)와 회로기판(10)의 본드핑거(12)를 도전성와이어(20)로 상호 접속시킨다.Subsequently, as illustrated in FIG. 4D, a plurality of input / output pads 1a are formed downward in the penetrating portion 16 of the circuit board 10, which is a lower surface of the second and third semiconductor chips 2 and 3. A first semiconductor chip 1 (or a fourth semiconductor chip (not shown) is attached to the bottom surface of the first semiconductor chip 1), and an input / output pad 1a of the first semiconductor chip 1 The bond fingers 12 of the circuit board 10 are interconnected by conductive wires 20.
이어서, 도4e에 도시된 바와 같이 상기 관통부(16) 및 제1반도체칩(1)을 포함하는 일정 영역을 봉지재(제2봉지재(32))로 봉지한다.Subsequently, as shown in FIG. 4E, a predetermined region including the penetrating portion 16 and the first semiconductor chip 1 is sealed with an encapsulant (second encapsulant 32).
마지막으로, 상기 회로기판(10)의 볼랜드(13)에 다수의 도전성볼(40)을 융착하여, 마더보드에 실장 가능한 형태가 되도록 한다.Finally, a plurality of conductive balls 40 are fused to the ball lands 13 of the circuit board 10 so as to be mounted on the motherboard.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 회로기판의 관통부에 다수의 반도체칩이 상,하방향으로 적층된채 탑재됨으로써, 그 반도체패키지의 고밀도화, 기능화 및 고용량화를 구현할 수 있는 효과가 있다.Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, a plurality of semiconductor chips are mounted in the penetrating portion of the circuit board in the vertical direction, thereby realizing high density, functionalization and high capacity of the semiconductor package. It works.
더욱이, 상기 반도체칩이 메모리용 반도체칩일 경우에는 상기 반도체패키지의 용량을 최소의 면적하에서 최대로 확보할 수 있는 효과가 있다.Furthermore, when the semiconductor chip is a memory semiconductor chip, there is an effect of ensuring the maximum capacity of the semiconductor package under a minimum area.
더불어, 주문형 반도체칩과 메모리용 반도체칩을 동시에 탑재할 수 있게 되므로, 대부분의 전기적 기능을 하나의 반도체패키지로서 해결할 수 있는 효과가 있다.In addition, since the on-demand semiconductor chip and the memory semiconductor chip can be mounted at the same time, most electrical functions can be solved as a single semiconductor package.
Claims (12)
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| JP2000246332A JP2001077301A (en) | 1999-08-24 | 2000-08-15 | Semiconductor package and its manufacturing method |
| US09/648,284 US6798049B1 (en) | 1999-08-24 | 2000-08-24 | Semiconductor package and method for fabricating the same |
| US10/600,931 US6982488B2 (en) | 1999-08-24 | 2003-06-20 | Semiconductor package and method for fabricating the same |
| US11/129,596 US7211900B2 (en) | 1999-08-24 | 2005-05-13 | Thin semiconductor package including stacked dies |
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| KR (1) | KR100411808B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08321565A (en) * | 1995-05-25 | 1996-12-03 | Hitachi Ltd | Semiconductor device |
| KR100197876B1 (en) * | 1996-04-01 | 1999-06-15 | 김규현 | Semiconductor package and method of manufacturing the same |
| JPH11204720A (en) * | 1998-01-14 | 1999-07-30 | Sharp Corp | Semiconductor device and its manufacture |
| KR19990080278A (en) * | 1998-04-15 | 1999-11-05 | 최완균 | Multi-chip package |
-
1999
- 1999-12-30 KR KR10-1999-0065926A patent/KR100411808B1/en active IP Right Grant
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08321565A (en) * | 1995-05-25 | 1996-12-03 | Hitachi Ltd | Semiconductor device |
| KR100197876B1 (en) * | 1996-04-01 | 1999-06-15 | 김규현 | Semiconductor package and method of manufacturing the same |
| JPH11204720A (en) * | 1998-01-14 | 1999-07-30 | Sharp Corp | Semiconductor device and its manufacture |
| KR19990080278A (en) * | 1998-04-15 | 1999-11-05 | 최완균 | Multi-chip package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010058576A (en) | 2001-07-06 |
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