KR100623317B1 - Semiconductor package - Google Patents

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KR100623317B1
KR100623317B1 KR1020000062950A KR20000062950A KR100623317B1 KR 100623317 B1 KR100623317 B1 KR 100623317B1 KR 1020000062950 A KR1020000062950 A KR 1020000062950A KR 20000062950 A KR20000062950 A KR 20000062950A KR 100623317 B1 KR100623317 B1 KR 100623317B1
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South Korea
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semiconductor chip
substrate
input
circuit pattern
semiconductor
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KR1020000062950A
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Korean (ko)
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KR20020032065A (en
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신원선
장상재
허영욱
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020000062950A priority Critical patent/KR100623317B1/en
Publication of KR20020032065A publication Critical patent/KR20020032065A/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

이 발명은 반도체패키지에 관한 것으로, 센터패드형(Center Pad Type)과 엣지패드형(Edge Pad Type) 반도체칩을 혼합하여 스택하거나 또는 센터패드형 반도체칩끼리 스택할 수 있는 동시에, 다양한 크기의 반도체칩을 스택할 수 있도록, 대략 평면인 제1면과 제2면을 가지고, 상기 제1면 중앙에는 다수의 입출력패드가 형성된 제1반도체칩과; 대략 평면인 제1면과 제2면을 가지고, 상기 제1면 또는 제2면중 어느 한면에 다수의 입출력패드가 형성되어 있으며, 상기 제1면이 상기 제1반도체칩의 제2면에 접착된 제2반도체칩과; 수지층에 다수의 도전성 회로패턴이 형성되어 대략 평면인 제1면과 제2면을 이루고, 상기 제2면에는 상기 제1반도체칩의 제1면이 접착되어 있으며, 상기 제1반도체칩의 입출력패드와 간섭하지 않토록 중앙에 관통공이 형성된 섭스트레이트와; 상기 제1반도체칩 및 제2반도체칩의 입출력패드와 상기 섭스트레이트의 회로패턴을 전기적으로 접속시키는 전기적 접속수단과; 상기 섭스트레이트의 관통공 및 섭스트레이트의 제2면, 제1반도체칩, 제2반도체칩 및 전기적 접속수단을 봉지하는 봉지재와; 상기 섭스트레이트의 제1면에 형성된 회로패턴에 융착된 다수의 도전성단자를 포함하여 이루어진 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, wherein a center pad type and an edge pad type semiconductor chip can be mixed and stacked, or a center pad type semiconductor chip can be stacked and a semiconductor of various sizes A first semiconductor chip having a first plane and a second plane which are substantially planar, and having a plurality of input / output pads formed at the center of the first surface so as to stack the chips; The first and second surfaces are substantially planar, and a plurality of input / output pads are formed on either one of the first and second surfaces, and the first surface is bonded to the second surface of the first semiconductor chip. A second semiconductor chip; A plurality of conductive circuit patterns are formed on the resin layer to form a substantially planar first surface and a second surface, wherein the first surface of the first semiconductor chip is bonded to the second surface, and the input and output of the first semiconductor chip are A substrate having a through hole formed in the center thereof so as not to interfere with the pad; Electrical connection means for electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit pattern of the substrate; An encapsulant for encapsulating the through-hole of the substrate and the second surface of the substrate, the first semiconductor chip, the second semiconductor chip, and the electrical connection means; And a plurality of conductive terminals fused to a circuit pattern formed on the first surface of the substrate.

Description

반도체패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

도1은 종래의 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package.

도2a 내지 도2d는 본 발명에 의한 센터패드형과 엣지패드형 반도체칩이 스택(Stack)된 반도체패키지를 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a semiconductor package in which a center pad type and an edge pad type semiconductor chip according to the present invention are stacked.

도3a 내지 도3d는 본 발명에 의한 센터패드형 반도체칩이 스택된 반도체패키지를 도시한 단면도이다.3A to 3D are cross-sectional views illustrating a semiconductor package in which a center pad semiconductor chip according to the present invention is stacked.

도4a 및 도4b는 본 발명에 의한 센터패드형과 엣지패드형 반도체칩이 스택된 또다른 반도체패키지를 도시한 단면도이다.4A and 4B are cross-sectional views showing another semiconductor package in which a center pad type and an edge pad type semiconductor chip according to the present invention are stacked.

도5a 내지 도5j는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 상태도이다.5A to 5J are state diagrams illustrating a method of manufacturing a semiconductor package according to the present invention.

도6a 내지 도6d는 본 발명에 의한 반도체패키지의 제조 방법중 다른 방법을 도시한 상태도이다.6A to 6D are state diagrams showing another method of the method for manufacturing a semiconductor package according to the present invention.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

101~110; 본 발명에 의한 반도체패키지.101-110; Semiconductor package according to the present invention.

1; 제1반도체칩 1a,2a,10a; 제1면One; First semiconductor chip 1a, 2a, 10a; Front page

1b,2b,10b; 제2면 1c,2c; 입출력패드1b, 2b, 10b; Second page 1c, 2c; I / O pad

2; 제2반도체칩 3; 접착층2; Second semiconductor chip 3; Adhesive layer

10; 섭스트레이트10; Substrate

11; 수지층 12; 회로패턴11; Resin layer 12; Circuit pattern

12a; 본드핑거 12b; 랜드12a; Bondfinger 12b; rand

14; 커버코트 15a, 15b; 관통공, 제2관통공14; Covercoats 15a, 15b; Through hole, second through hole

20; 접속수단 30; 신호전달부재20; Connection means 30; Signal transmission member

32;회로패턴 33;커버코트32; circuit pattern 33; cover coat

40; 봉지재 50; 도전성단자40; Encapsulant 50; Conductive Terminal

본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 센터패드형(Center Pad Type)과 엣지패드형(Edge Pad Type) 반도체칩을 혼합하여 스택하거나 또는 센터패드형 반도체칩끼리 스택할 수 있는 동시에, 다양한 크기의 반도체칩을 스택할 수 있는 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and in more detail, a center pad type and an edge pad type semiconductor chip may be mixed and stacked or center pad type semiconductor chips may be stacked. The present invention relates to a semiconductor package that can stack semiconductor chips of various sizes.

통상 반도체패키지는 반도체칩을 외부 환경으로부터 안전하게 보호함은 물론, 그 반도체칩과 마더보드(Mother Board)와의 전기적 신호가 용이하게 교환되도록 한 것을 말한다.In general, the semiconductor package not only protects the semiconductor chip from the external environment, but also means that the electrical signal between the semiconductor chip and the motherboard is easily exchanged.

최근에는 상기한 반도체패키지 내부에 다수의 반도체칩을 적층함으로써 고기능화를 구현한 적층형 반도체패키지가 출시되고 있으며, 이러한 종래의 통상적인 적층형 반도체패키지(100')를 도1에 도시하였다.Recently, a multilayer semiconductor package having high functionality by stacking a plurality of semiconductor chips inside the semiconductor package has been released. Such a conventional multilayer semiconductor package 100 'is shown in FIG.

도시된 바와 같이 통상 수지층(18')을 중심으로 상,하면에 본드핑거(20a') 및 랜드(20b')를 갖는 회로패턴(20')이 형성되어 있고, 상기 회로패턴(20')의 표면은 커버코트(23')로 코팅된 회로기판(16')이 구비되어 있다.As illustrated, circuit patterns 20 'having bond fingers 20a' and lands 20b 'are formed on upper and lower surfaces of the resin layer 18', and the circuit patterns 20 'are formed. The surface of the circuit board 16 'is coated with a cover coat 23'.

또한, 상기 회로기판(16')의 상면 중앙부에는 제1반도체칩(2')이 접착층(3')에 의해 접착되어 있고, 상기 제1반도체칩(2')의 상면에는 제2반도체칩(6')이 접착층(3')으로 접착되어 있다. 물론, 상기 제1반도체칩(2') 및 제2반도체칩(6')의 상면 둘레에는 다수의 입출력패드(4',8')가 형성되어 있다(이러한 반도체칩을 통상 엣지패드형 반도체칩이라 함). 상기 제1반도체칩(2') 및 제2반도체칩(6')의 입출력패드(4',8')는 각각 회로기판(16')에 형성된 회로패턴(20')중 본드핑거(20a')에 도전성와이어(60')로 본딩되어 있다. 또한, 제1반도체칩(2'), 제2반도체칩(6'), 도전성와이어(60') 및 회로기판(16')의 상면은 봉지재(40')로 봉지되어 있다. 상기 회로기판(16')의 하면에 형성된 회로패턴(20')중 랜드(20b')에는 다수의 도전성볼(50')이 융착되어 있으며, 이 도전성볼(50')이 차후 마더보드의 소정 패턴에 본딩된다. 도면중 미설명 부호 20c'는 도전성 비아홀이다.In addition, the first semiconductor chip 2 'is bonded to the center portion of the upper surface of the circuit board 16' by the adhesive layer 3 ', and the second semiconductor chip 2 is attached to the upper surface of the first semiconductor chip 2'. 6 ') is bonded by the adhesive layer 3'. Of course, a plurality of input / output pads 4 'and 8' are formed around the upper surfaces of the first semiconductor chip 2 'and the second semiconductor chip 6' (these semiconductor chips are typically edge pad type semiconductor chips). ). The I / O pads 4 'and 8' of the first semiconductor chip 2 'and the second semiconductor chip 6' are bonded fingers 20a 'of the circuit patterns 20' formed on the circuit board 16 ', respectively. Is bonded to the conductive wire 60 '. In addition, the upper surface of the first semiconductor chip 2 ', the second semiconductor chip 6', the conductive wire 60 ', and the circuit board 16' is sealed with an encapsulant 40 '. A plurality of conductive balls 50 'are fused to the lands 20b' of the circuit pattern 20 'formed on the bottom surface of the circuit board 16', and the conductive balls 50 'are subsequently formed on the motherboard. Bonded to the pattern. In the figure, reference numeral 20c 'denotes a conductive via hole.

이러한 반도체패키지(100')는 제1반도체칩(2') 및 제2반도체칩(6')의 전기적 신호가 도전성와이어(60'), 회로기판(16')의 본드핑거(20a'), 도전성 비아홀(20c'), 랜드 (20b') 및 도전성볼(50')을 통해서 마더보드와 교환되며, 두개의 반도체칩이 적층된 상태이므로 반도체패키지가 고용량, 고기능화되고 또한 실장밀도를 높일 수 있는 장점이 있다.In the semiconductor package 100 ', the electrical signals of the first semiconductor chip 2' and the second semiconductor chip 6 'are transmitted to the conductive wire 60', the bond finger 20a 'of the circuit board 16', It is exchanged with the motherboard through the conductive via hole 20c ', the land 20b' and the conductive ball 50 ', and since the two semiconductor chips are stacked, the semiconductor package can have high capacity, high functionality and high mounting density. There is an advantage.

그러나, 상기 제1반도체칩 및 제2반도체칩은 모두 엣지패드형 반도체칩으로서 센터패드형과 혼합하여 스택할 수 없고, 또한 상기한 구조에서는 다수의 센터패드형 반도체칩을 스택할 수 없는 문제점이 있다. 즉, 회로 설계상 센터패드형 반도체칩으로 제조할 수 밖에 없는 경우가 있는데, 이러한 센터패드형 반도체칩은 스택형 반도체패키지에 전혀 탑재할 수 없는 한계가 있다.However, both the first semiconductor chip and the second semiconductor chip are edge pad type semiconductor chips, which cannot be mixed with the center pad type, and cannot stack a plurality of center pad type semiconductor chips in the above structure. have. In other words, the circuit design has to be manufactured with a center pad type semiconductor chip, but such a center pad type semiconductor chip cannot be mounted in a stack type semiconductor package at all.

또한, 상기 제1반도체칩의 입출력패드에 본딩되는 도전성와이어와의 접촉을 피하기 위해, 상기 제2반도체칩의 넓이 또는 부피가 상기 제1반도체칩의 넓이 또는 부피보다 반듯이 작아야 하는 단점이 있다. 즉, 상기 제2반도체칩의 부피가 제1반도체칩의 부피와 같거나 클 경우에는 그 제2반도체칩의 저면과 도전성와이어가 상호 쇼트됨으로써 제1반도체칩의 전기적 기능이 마비되는 문제가 있어, 반듯이 그 제2반도체칩의 크기가 제1반도체칩의 크기보다 작아야 한다.In addition, in order to avoid contact with conductive wires bonded to the input / output pads of the first semiconductor chip, the width or volume of the second semiconductor chip must be less than the width or volume of the first semiconductor chip. That is, when the volume of the second semiconductor chip is equal to or larger than the volume of the first semiconductor chip, the bottom surface of the second semiconductor chip and the conductive wire are shorted to each other, thereby causing paralysis of the electrical function of the first semiconductor chip. On the contrary, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip.

이러한 문제들은 동일한 크기의 반도체칩을 다수 적층하여야 하는 메모리 반도체패키지(예를 들면 다수의 DRAM, ASIC, Flash 또는 SRAM을 적층한 반도체패키지)에 적용할 수 없어, 패키징할 수 있는 반도체칩의 종류를 극히 제한시키고 있다.These problems cannot be applied to a memory semiconductor package (for example, a semiconductor package in which a plurality of DRAMs, ASICs, Flashes, or SRAMs are stacked) in which multiple semiconductor chips of the same size must be stacked. It is extremely limited.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 센터패드형과 엣지패드형 반도체칩을 혼합하여 스택할 수 있는 반도체패키지를 제공하는데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, to provide a semiconductor package that can be stacked by stacking a center pad type and an edge pad type semiconductor chip.

본 발명의 다른 목적은 다수의 센터패드형 반도체칩을 스택할 수 있는 반도체패키지를 제공하는데 있다.Another object of the present invention is to provide a semiconductor package capable of stacking a plurality of center pad semiconductor chips.

본 발명의 또다른 목적은 반도체칩의 크기 또는 부피에 제한받지 않고, 다수의 반도체칩을 스택할 수 있는 반도체패키지를 제공하는데 있다.Still another object of the present invention is to provide a semiconductor package capable of stacking a plurality of semiconductor chips without being limited by the size or volume of the semiconductor chip.

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 대략 평면인 제1면과 제2면을 가지고, 상기 제1면 중앙에는 다수의 입출력패드가 형성된 제1반도체칩과; 대략 평면인 제1면과 제2면을 가지고, 상기 제1면 또는 제2면중 어느 한면에 다수의 입출력패드가 형성되어 있으며, 상기 제1면이 상기 제1반도체칩의 제2면에 접착된 제2반도체칩과; 수지층에 다수의 도전성 회로패턴이 형성되어 대략 평면인 제1면과 제2면을 이루고, 상기 제2면에는 상기 제1반도체칩의 제1면이 접착되어 있으며, 상기 제1반도체칩의 입출력패드와 간섭하지 않토록 중앙에 관통공이 형성된 섭스트레이트와; 상기 제1반도체칩 및 제2반도체칩의 입출력패드와 상기 섭스트레이트의 회로패턴을 전기적으로 접속시키는 전기적 접속수단과; 상기 섭스트레이트의 관통공 및 섭스트레이트의 제2면, 제1반도체칩, 제2반도체칩 및 전기적 접속수단을 봉지하는 봉지재와; 상기 섭스트레이트의 제1면에 형성된 회로패턴에 융착된 다수의 도전성단자를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention has a first plane and a second plane which are substantially planar, and a first semiconductor chip having a plurality of input / output pads formed at the center of the first surface; The first and second surfaces are substantially planar, and a plurality of input / output pads are formed on either one of the first and second surfaces, and the first surface is bonded to the second surface of the first semiconductor chip. A second semiconductor chip; A plurality of conductive circuit patterns are formed on the resin layer to form a substantially planar first surface and a second surface, wherein the first surface of the first semiconductor chip is bonded to the second surface, and the input and output of the first semiconductor chip are A substrate having a through hole formed in the center thereof so as not to interfere with the pad; Electrical connection means for electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit pattern of the substrate; An encapsulant for encapsulating the through-hole of the substrate and the second surface of the substrate, the first semiconductor chip, the second semiconductor chip, and the electrical connection means; And a plurality of conductive terminals fused to a circuit pattern formed on the first surface of the substrate.

상기 제2반도체칩은 제2면 가장자리에 다수의 입출력패드가 형성될 수 있다.In the second semiconductor chip, a plurality of input / output pads may be formed at edges of the second surface.

상기 제2반도체칩은 제2면 중앙에 다수의 입출력패드가 형성될 수도 있다.In the second semiconductor chip, a plurality of input / output pads may be formed in the center of the second surface.

또한, 상기 제2반도체칩은 제1면 가장자리에 다수의 입출력패드가 형성될 수도 있다.In addition, a plurality of input / output pads may be formed at the edge of the first surface of the second semiconductor chip.

상기 제1반도체칩 및 제2반도체칩을 섭스트레이트에 접속시키는 전기적 접속수단은 도전성와이어일 수 있다.Electrical connection means for connecting the first semiconductor chip and the second semiconductor chip to the substrate may be a conductive wire.

상기 제1반도체칩과 섭스트레이트를 접속시키는 전기적 접속수단은 상기 섭스트레이트로부터 상기 관통공 내측으로 연장되어 형성된 회로패턴이고, 상기 제2반도체칩과 섭스트레이트를 접속시키는 전기적 접속수단은 도전성와이어일 수 있다.The electrical connection means for connecting the first semiconductor chip and the substrate is a circuit pattern formed extending from the substrate to the inside of the through hole, and the electrical connection means for connecting the second semiconductor chip and the substrate may be conductive wires. have.

상기 섭스트레이트는 상기 제2반도체칩의 가장자리와 대응되는 부분에 또다른 제2관통공이 형성되어 있고, 상기 제2관통공을 통하여서는 회로패턴이 연장되어 상기 제2반도체칩에 전기적으로 접속된 동시에, 상기 섭스트레이트의 관통공을 통하여서도 회로패턴이 연장되어 상기 제1반도체칩에 전기적으로 접속될 수 있다.The second substrate has another second through hole formed at a portion corresponding to an edge of the second semiconductor chip, and a circuit pattern extends through the second through hole to be electrically connected to the second semiconductor chip. In addition, a circuit pattern may be extended through the through hole of the substrate to be electrically connected to the first semiconductor chip.

상기 제2반도체칩은 제2면이 봉지재 외측으로 노출될 수도 있다.A second surface of the second semiconductor chip may be exposed to the outside of the encapsulant.

상기 섭스트레이트의 측단은 상기 섭스트레이트의 제2면과 밀착된 봉지재의 측단이 동일면일 수 있다.The side end of the substrate may have the same side surface as the side end of the encapsulant in close contact with the second surface of the substrate.

상기 섭스트레이트는 상기 섭스트레이트의 제2면과 밀착된 봉지재의 측단으로부터 더 외측으로 연장될 수 있다.The substrates may extend further outwardly from side ends of the encapsulant in close contact with the second surface of the substrates.

상기 섭스트레이트는 수지층을 중심으로, 상기 제1면에는 다수의 랜드를 갖고, 상기 제1면 및 제2면에는 다수의 본드핑거를 갖는 회로패턴을 포함하여 이루어진 인쇄회로기판, 써킷필름 또는 써킷테이프중 어느 하나 일 수 있다.The substrate includes a circuit pattern including a plurality of lands on the first surface and a plurality of bond fingers on the first and second surfaces of the substrate. It can be either tape.

상기 도전성 단자는 도전성볼 또는 도전성패드중 어느 하나 일 수 있다.The conductive terminal may be any one of a conductive ball or a conductive pad.

상기 제2반도체칩은 제2면 중앙 외주연에 회로패턴을 갖는 신호전달부재가 더 접착될 수 있다.The second semiconductor chip may be further bonded to a signal transmission member having a circuit pattern on the outer periphery of the center of the second surface.

상기 신호전달부재는 수지층을 중심으로 그 표면에 회로패턴이 형성될 수 있다.The signal transmission member may have a circuit pattern formed on a surface of the resin layer.

상기 제2반도체칩은 입출력패드가 전기적 접속수단에 의해 의해 상기 신호전달부재의 회로패턴 일단에 접속되고, 상기 회로패턴의 타단도 전기적 접속수단에 의해 섭스트레이트의 회로패턴에 접속될 수 있다.In the second semiconductor chip, an input / output pad may be connected to one end of a circuit pattern of the signal transmission member by an electrical connection means, and the other end of the circuit pattern may be connected to a substrate circuit pattern by an electrical connection means.

또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 수지층을 중심으로 그 표면에는 다수의 도전성 회로패턴이 형성된 섭스트레이트를 제공하는 단계와; 상기 섭스트레이트의 일면에 일정 면적의 접착층을 접착시키는 단계와; 상기 수지층 및 접착층을 일체로 펀칭하여 일정크기의 관통공을 형성하는 단계와; 입출력패드가 서로 반대 방향에 위치하도록 2개의 제1반도체칩 및 제2반도체칩을 접착시킨 채, 상기 제1반도체칩의 입출력패드가 상기 섭스트레이트의 관통공을 통하여 외부로 오픈되도록 접착층에 접착시키는 단계와; 상기 제1반도체칩의 입출력패드를 상기 섭스트레이트의 회로패턴에 관통공을 통하여 전기적 접속수단으로 접속시키는 제1전기적 접속단계와; 상기 섭스트레이트의 관통공 및 접속수단을 봉지재로 봉지하는 제1봉지 단계와; 상기 제2반도체칩의 입출력패드를 상기 섭스트레이트의 회로패턴에 전기적 접속수단으로 접속시키는 제2전기적 접속단계와; 상기 제2반도체칩, 접속수단 및 섭스트레이트의 일면을 봉지재로 봉지하는 제2봉지 단계와; 상기 섭스트레이트의 타면에 위치된 회로패턴에 다수의 도전성볼을 융착하는 단계와; 상기 섭스트레이트 및 봉지재를 소잉하여 낱개의 반도체패키 지로 분리하는 소잉단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention for achieving the above object comprises the steps of providing a substrate having a plurality of conductive circuit patterns formed on the surface of the resin layer; Adhering an adhesive layer having a predetermined area to one surface of the substrate; Punching the resin layer and the adhesive layer integrally to form through holes having a predetermined size; The first semiconductor chip and the second semiconductor chip are bonded to each other so that the input / output pads are located in opposite directions, and the input / output pads of the first semiconductor chip are bonded to the adhesive layer to be opened to the outside through the through holes of the substrate. Steps; A first electrical connection step of connecting the input / output pad of the first semiconductor chip to the circuit pattern of the substrate through an electrical connection means through a through hole; A first encapsulating step of encapsulating the through-hole and the connecting means of the substrate with an encapsulant; A second electrical connection step of connecting the input / output pad of the second semiconductor chip to the circuit pattern of the substrate by electrical connection means; A second encapsulation step of encapsulating one surface of the second semiconductor chip, the connecting means, and the substrate with an encapsulant; Fusing a plurality of conductive balls to a circuit pattern located on the other surface of the substrate; And a sawing step of separating the substrate and the encapsulant into individual semiconductor packages.

상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 섭스트레이트에 관통공을 형성하고, 상기 관통공을 통하여 센터패드형인 제1반도체칩의 입출력패드가 오픈되도록 하고, 상기 제1반도체칩의 입출력패드가 형성되지 않은 면에는 엣지패드형인 제2반도체칩을 접착시킴으로써 센터패드형 및 엣지패드형 반도체칩을 혼합하여 스택할 수 있게 된다.According to the semiconductor package according to the present invention as described above, through holes are formed in the substrate, and through the through holes, the input / output pads of the first semiconductor chip of the center pad type are opened, and the input / output pads of the first semiconductor chip are opened. The center pad and edge pad semiconductor chips may be mixed and stacked by adhering the second semiconductor chip, which is an edge pad type, to a surface on which is not formed.

또한, 상기 센터패드형 제1반도체칩의 일면에 또다른 센터패드형 제2반도체칩을 접착시킬 수 있음으로써 센터패드형 반도체칩끼리도 스택할 수 있게 된다.In addition, by attaching another center pad type second semiconductor chip to one surface of the center pad type first semiconductor chip, the center pad type semiconductor chips can also be stacked.

또한, 입출력패드가 형성되지 않은 반도체칩의 일면에 센터패드형 또는 엣지패드형의 다른 반도체칩을 자유롭게 접착시킬 수 있음으로써 반도체칩의 크기 또는 부피에 제한받지 않고, 다수의 반도체칩을 스택할 수 있게 된다.In addition, it is possible to freely adhere the center pad type or the edge pad type other semiconductor chips to one surface of the semiconductor chip on which the input / output pad is not formed, thereby stacking a plurality of semiconductor chips without being limited by the size or volume of the semiconductor chip. Will be.

또한, 전기적 접속수단으로서 도전성와이어 또는 회로패턴을 선택적으로 이용할 수 있음으로써, 반도체칩과 섭스트레이트의 사이의 전기적 연결이 보다 용이해진다.In addition, by selectively using conductive wires or circuit patterns as the electrical connection means, electrical connection between the semiconductor chip and the substrate becomes easier.

또한, 상기 전기적 접속수단으로서 회로패턴만을 이용했을 경우에는 반도체칩의 일면을 봉지재 외측으로 오픈시킬 수 있어 방열성능을 향상시킬 수 있게 된다.In addition, when only the circuit pattern is used as the electrical connection means, one surface of the semiconductor chip can be opened to the outside of the encapsulant, thereby improving heat dissipation performance.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

먼저, 도2a 내지 도2d는 본 발명에 의한 센터패드형과 엣지패드형 반도체칩이 스택(Stack)된 반도체패키지(101,102,103,104)를 도시한 단면도이다.First, FIGS. 2A to 2D are cross-sectional views illustrating semiconductor packages 101, 102, 103, and 104 in which a center pad type and an edge pad type semiconductor chip are stacked.

도시된 바와 같이, 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제1면(1a) 중앙에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)(센터패드형)이 구비되어 있다.As shown, the first semiconductor chip 1 (1) having a substantially planar first surface 1a and a second surface 1b and having a plurality of input / output pads 1c formed in the center of the first surface 1a ( Center pad type).

또한, 대략 평면인 제1면(2a)과 제2면(2b)을 가지고, 상기 제2면(2b)의 가장 자리에는 다수의 입출력패드(2c)가 형성된 제2반도체칩(2)(엣지패드형)이 접착층(3)이 개재된 채, 상기 제1반도체칩(1)의 제2면(1b)에 접착되어 있다.In addition, a second semiconductor chip 2 (edge) having an approximately planar first surface 2a and a second surface 2b, and having a plurality of input / output pads 2c formed at the edges of the second surface 2b. Pad type) is bonded to the second surface 1b of the first semiconductor chip 1 with the adhesive layer 3 interposed therebetween.

상기와 같이 제1반도체칩(1) 및 제2반도체칩(2)의 입출력패드(1c,2c)는 그 형성 방향이 서로 반대이므로, 상기 제2반도체칩(2)의 크기 또는 부피는 제1반도체칩(1)의 크기 또는 부피에 제한 받지 않고 자유롭게 결정될 수 있다.As described above, since the formation directions of the input / output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 are opposite to each other, the size or volume of the second semiconductor chip 2 is equal to or greater than that of the first semiconductor chip 1 and the second semiconductor chip 2. It can be freely determined without being limited to the size or volume of the semiconductor chip (1).

계속해서, 상기 제1반도체칩(1)의 제1면(1a)에는 접착층(3)이 개재된 채 상기 제1반도체칩(1)의 넓이보다 넓은 섭스트레이트(10)가 접착되어 있다.Subsequently, a substrate 10 that is wider than the width of the first semiconductor chip 1 is bonded to the first surface 1a of the first semiconductor chip 1 with the adhesive layer 3 interposed therebetween.

상기 섭스트레이트(10)는 수지층(11)을 중심으로 그 표면에 도전성 회로패턴(12)이 형성되어 있으며, 상기 회로패턴(12)은 커버코트(14)에 의해 부분적으로 코팅되어 있다. 즉, 상기 회로패턴(12)은 크게 본드핑거(12a)와 랜드(12b)를 포함하며, 상기 본드핑거(12a) 및 랜드(12b)가 외측으로 오픈되도록 그 표면이 커버코트(14)에 의해 코팅되어 있다. 이러한 섭스트레이트(10)는 주지된 바와 같이 통상의 인쇄회로기판, 써킷필름 또는 써킷테이프 등이 이용될 수 있으며, 본 발명에서 어느 하나로 한정하는 것은 아니다.The substrate 10 has a conductive circuit pattern 12 formed on the surface of the resin layer 11, and the circuit pattern 12 is partially coated by a cover coat 14. That is, the circuit pattern 12 includes a bond finger 12a and a land 12b largely, and the surface thereof is covered by the cover coat 14 so that the bond finger 12a and the land 12b are opened to the outside. Coated. The substrate 10 may be a conventional printed circuit board, a circuit film or a circuit tape, as is well known, it is not limited to any one in the present invention.

또한, 상기 섭스트레이트(10)는 상기 제1반도체칩(1)의 입출력패드(1c)와 대응되는 위치에 일정크기의 관통공(15a)이 형성되어 있으며, 상기 관통공(15a)의 외주연 표면에는 전술한 본드핑거(12a) 및 랜드(12b)를 포함하는 회로패턴(12)이 형성되어 있다. 물론, 상기 랜드(12b)가 형성된 면의 반대면에도 본드핑거(12a)가 형성되어 있다.In addition, the substrate 10 has a through hole 15a of a predetermined size formed at a position corresponding to the input / output pad 1c of the first semiconductor chip 1, and has an outer circumferential edge of the through hole 15a. The circuit pattern 12 including the above-described bond finger 12a and land 12b is formed on the surface. Of course, the bond finger 12a is formed on the surface opposite to the surface on which the land 12b is formed.

계속해서, 상기 제1반도체칩(1) 및 제2반도체칩(2)의 입출력패드(1c,2c)는 상기 섭스트레트에 형성된 회로패턴(12)중 본드핑거(12a)에 전기적 접속수단(20)으로 각각 접속되어 있다.Subsequently, the input / output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 are electrically connected to the bond fingers 12a of the circuit patterns 12 formed on the substrates. 20), respectively.

즉, 도2a 및 도2b에 도시된 반도체패키지(101,102)에서와 같이 상기 제2반도체칩(2)의 입출력패드(2c)는 골드와이어 또는 알루미늄와이어와 같은 도전성와이어에 의해 섭스트레이트(10)의 제2면(10b)에 형성된 회로패턴(12)중 본드핑거(12a)에 접속되어 있고, 제1반도체칩(1)의 입출력패드(1c) 역시 골드와이어 또는 알루미늄와이어와 같은 도전성와이어에 의해 섭스트레이트(10)의 관통공(15a)을 통과하여 그 섭스트레이트(10)의 제1면(10a)에 형성된 회로패턴(12)중 본드핑거(12a)에 전기적으로 연결되어 있다.That is, as in the semiconductor packages 101 and 102 shown in FIGS. 2A and 2B, the input / output pads 2c of the second semiconductor chip 2 may be formed by the conductive wires such as gold wires or aluminum wires. It is connected to the bond finger 12a of the circuit pattern 12 formed on the second surface 10b, and the input / output pad 1c of the first semiconductor chip 1 is also subtracted by a conductive wire such as gold wire or aluminum wire. It passes through the through hole 15a of the straight 10 and is electrically connected to the bond finger 12a of the circuit pattern 12 formed on the first surface 10a of the substrate 10.

한편, 도2c 및 도2d에 도시된 반도체패키지(103,104)에서와 같이, 상기 섭스트레이트(10)의 회로패턴(12)은 관통공(15a) 내측까지 일정길이 더 연장될 수도 있다. 따라서, 이 경우에는 상기 연장된 회로패턴(12)을 직접 상기 제1반도체칩(1)의 입출력패드(1c)에 갱본딩(Gang Bonding) 또는 탭본딩(TAP Bonding)하여 연결할 수도 있다.Meanwhile, as in the semiconductor packages 103 and 104 illustrated in FIGS. 2C and 2D, the circuit pattern 12 of the substrate 10 may be further extended to a predetermined length to the inside of the through hole 15a. Therefore, in this case, the extended circuit pattern 12 may be directly connected to the input / output pad 1c of the first semiconductor chip 1 by gang bonding or tap bonding.

이어서, 상기 섭스트레이트(10)의 관통공(15a)은 봉지재(40)로 봉지되어, 상기 관통공(15a) 내측의 전기적 접속수단(20) 즉, 도전성와이어 또는 관통공(15ab) 내측으로 연장된 회로패턴(12)이 외부 환경으로부터 보호되도록 되어 있다. 물론, 상기 제1반도체칩(1), 제2반도체칩(2), 상기 제2반도체칩(2)에 접속된 전기적 접속수단(20)과 섭스트레이트(10)의 제2면(10b)도 봉지재(40)로 봉지되어 외부환경으로부터 보호 가능하게 되어 있다. 여기서, 상기 봉지재(40)는 통상적인 에폭시 몰딩 컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top) 등이 이용될 수 있다.Subsequently, the through hole 15a of the substrate 10 is encapsulated with an encapsulant 40 to be electrically connected to the electrical connection means 20 inside the through hole 15a, that is, inside the conductive wire or the through hole 15ab. The extended circuit pattern 12 is to be protected from the external environment. Of course, the electrical connection means 20 and the second surface 10b of the substrate 10 connected to the first semiconductor chip 1, the second semiconductor chip 2, and the second semiconductor chip 2 are also included. It is encapsulated with the encapsulant 40 to be protected from the external environment. In this case, the encapsulant 40 may be a conventional epoxy molding compound or a glop top.

또한, 상기 섭스트레이트(10)의 회로패턴(12)중 랜드(12b)에는 도전성단자(50)가 융착됨으로써 차후 마더보드에 실장가능하게 되어 있다. 즉, 도2a 내지 도2c에 도시된 반도체패키지(101,102,103)에서와 같이 솔더볼 등을 융착하여 도전성단자(50)로 사용하거나, 또는 도2d에 도시된 반도체패키지(104)에서와 같이 제1반도체칩(1)의 입출력패드(1c)가, 섭스트레이트(10)의 관통공(15a) 내측으로 연장 형성된 회로패턴(12)으로 연결된 경우에는 비교적 두께가 작은 솔더패드를 융착하여 도전성단자(50)로 사용할 수 있다.In addition, the conductive terminal 50 is fused to the land 12b of the circuit pattern 12 of the substrate 10 so that it can be mounted on the motherboard later. That is, as in the semiconductor packages 101, 102, and 103 shown in FIGS. 2A to 2C, solder balls or the like are fused to be used as the conductive terminals 50, or the first semiconductor chip as in the semiconductor package 104 shown in FIG. 2D. When the input / output pad 1c of (1) is connected to the circuit pattern 12 extending into the through hole 15a of the substrate 10, a relatively small solder pad is fused to the conductive terminal 50. Can be used.

한편, 도2b에 도시된 반도체패키지(102)에서와 같이 상기 섭스트레이트(10)는 그 제2면(10b)에 형성된 봉지재(40)의 측단보다 더 외측으로 연장 형성될 수 있다. 상기와 같이 봉지재(40)의 측단으로 더 연장된 경우에는 그 섭스트레이트(10) 제1면(10a)에 보다 많은 회로패턴(12) 즉, 랜드(12b) 등을 형성할 수 있음으로써, 보다 많은 도전성단자(50)를 확보할 수 있게 된다.Meanwhile, as in the semiconductor package 102 illustrated in FIG. 2B, the substrate 10 may extend outwardly from the side end of the encapsulant 40 formed on the second surface 10b. In the case of extending further to the side end of the encapsulant 40 as described above, more circuit patterns 12, that is, lands 12b or the like may be formed on the first surface 10a of the substrate 10. More conductive terminals 50 can be secured.

도3a 내지 도3d는 본 발명에 의한 센터패드형 반도체칩이 스택된 반도체패키 지(105,106,107,108)를 도시한 단면도이다. 여기서, 상기 도3a 내지 도3d의 반도체패키지(105~108)는 도2a 내지 도2d의 반도체패키지(101~104)와 유사하므로, 그 차이점만을 설명하기로 한다.3A to 3D are cross-sectional views showing semiconductor packages 105, 106, 107 and 108 in which a center pad semiconductor chip according to the present invention is stacked. Here, since the semiconductor packages 105 to 108 of FIGS. 3A to 3D are similar to the semiconductor packages 101 to 104 of FIGS. 2A to 2D, only the differences will be described.

우선, 제2반도체칩(2)은 제2면(1b) 중앙에 다수의 입출력패드(2c)가 형성되어 있으며(센터패드형), 상기 입출력패드(2c)의 외주연인 제2면(2b)에는 신호전달부재(30)가 접착층(3)에 의해 접착되어 있다. 상기 신호전달부재(30)는 다수의 도전성 회로패턴(32)을 포함하며, 그 단부를 제외한 면은 커버코트(33)로 코팅될 수 있다. 또한, 상기 회로패턴(32)은 수지층(도시되지 않음)상에 형성될 수도 있으며, 이러한 신호전달부재(30)는 통상적인 인쇄회로기판, 써킷필름 또는 써킷테이프 등이 이용될 수도 있다.First, the second semiconductor chip 2 has a plurality of input / output pads 2c formed in the center of the second surface 1b (center pad type), and the second surface 2b which is the outer circumference of the input / output pad 2c. The signal transmission member 30 is adhered by the adhesive layer 3. The signal transmission member 30 includes a plurality of conductive circuit patterns 32, and the surface except for the end thereof may be coated with a cover coat 33. In addition, the circuit pattern 32 may be formed on a resin layer (not shown), and the signal transmission member 30 may use a conventional printed circuit board, a circuit film or a circuit tape.

상기 제2반도체칩(2)의 입출력패드(2c)는 도전성와이어와 같은 전기적 접속수단(20)에 의해 상기 신호전달부재(30)의 회로패턴(12) 일단에 접속되어 있고, 또한 상기 신호전달부재(30)의 회로패턴(12) 타단도 역시 도전성와이어와 같은 전기적 접속수단(20)에 의해 섭스트레이트(10)의 회로패턴(12)중 본드핑거(12a)에 연결되어 있다.The input / output pad 2c of the second semiconductor chip 2 is connected to one end of the circuit pattern 12 of the signal transmission member 30 by an electrical connection means 20 such as a conductive wire. The other end of the circuit pattern 12 of the member 30 is also connected to the bond finger 12a of the circuit pattern 12 of the substrate 10 by an electrical connection means 20 such as a conductive wire.

또한, 도3a 및 도3b에 도시된 반도체패키지(105,106)에서와 같이 상기 제1반도체칩(1)의 입출력패드(1c)는 전술한 바와 같이 도전성와이어와 같은 전기적 접속수단(20)에 의해 섭스트레이트(10)의 관통공(15a)을 통하여 그 외주연의 본드핑거(12a)에 접속되거나 또는 관통공(15a) 내측으로 연장된 회로패턴(12)에 의해 직접 접속될 수도 있다.In addition, as in the semiconductor packages 105 and 106 shown in FIGS. 3A and 3B, the input / output pad 1c of the first semiconductor chip 1 is subtracted by electrical connection means 20 such as conductive wires as described above. It may be connected to the bond finger 12a of the outer periphery through the through hole 15a of the straight 10, or may be directly connected by a circuit pattern 12 extending into the through hole 15a.

더불어, 도3c에 도시된 반도체패키지(107)에서와 같이 섭스트레이트(10)는 그 섭스트레이트(10)의 제2면(10b)에 형성된 봉지재(40)보다 더 외측으로 연장됨으로써 보다 많은 도전성단자(50)를 구비할 수도 있다.In addition, as in the semiconductor package 107 shown in FIG. 3C, the substrate 10 extends more outwardly than the encapsulant 40 formed on the second surface 10b of the substrate 10. The terminal 50 may be provided.

또한, 도3d에 도시된 반도체패키지(108)에서와 같이 상기 제2반도체칩(2)의 입출력패드(2c)는 도전성와이어와 같은 전기적 접속수단(20)에 의해 직접 상기 섭스트레이트(10)의 본드핑거(12a)에 접속될 수도 있다. 이때는 상기 전기적 접속수단(20)의 길이가 길어지게 됨으로, 상기 접속수단(20)이 제2반도체칩(2)의 제2면(2b)에 접촉하거나 또는 상호 쇼트되지 않토록 주의할 필요가 있다.In addition, as in the semiconductor package 108 shown in FIG. 3D, the input / output pad 2c of the second semiconductor chip 2 is directly connected by the electrical connection means 20 such as conductive wires. It may be connected to the bond finger 12a. In this case, since the length of the electrical connecting means 20 is increased, it is necessary to be careful that the connecting means 20 does not contact or short-circuit with the second surface 2b of the second semiconductor chip 2. .

도4a 및 도4b는 본 발명에 의한 센터패드형과 엣지패드형 반도체칩이 스택된 또다른 반도체패키지(109,110)를 도시한 단면도이다. 여기서도, 도2a 내지 도2d에 도시된 반도체패키지(101~104)와 다른 차이점을 위주로 설명하기로 한다.4A and 4B are cross-sectional views illustrating another semiconductor package 109 and 110 in which a center pad type and an edge pad type semiconductor chip according to the present invention are stacked. Here, the differences from the semiconductor packages 101 to 104 shown in FIGS. 2A to 2D will be mainly described.

도시된 바와 같이 제2반도체칩(2)은 제1면(2a)의 가장자리에 다수의 입출력패드(2c)가 형성되어 있다.(엣지패드형) 물론, 상기 제2반도체칩(2)의 입출력패드(2c)와 간섭하지 않토록, 제1반도체칩(1)의 크기 또는 부피는 상기 제2반도체칩(2)의 크기 또는 부피보다 작게 되어 있다.As illustrated, the second semiconductor chip 2 has a plurality of input / output pads 2c formed at the edge of the first surface 2a. (Edge pad type) Of course, the input / output of the second semiconductor chip 2 is provided. The size or volume of the first semiconductor chip 1 is smaller than the size or volume of the second semiconductor chip 2 so as not to interfere with the pad 2c.

또한, 상기 제1반도체칩(1)의 제1면(1a)에 접착층(3)으로 접착된 섭스트레이트(10)는 상기 제2반도체칩(2)의 측단과 대응되는 영역에 또다른 제2관통공(15b)이 형성되어 있다. 상기 제2관통공(15b)의 내측으로는 회로패턴(12)이 연장 형성되어 있으며, 이 회로패턴(12)은 상기 제2반도체칩(2)의 입출력패드(2c)에 전기적으로 접속되어 있다. 즉, 상기 회로패턴(12)이 직접 전기적 접속수단(20)이 되는 것이 다. 물론, 상기 접속수단(20) 역시 갱본딩이나 탭본딩 등에 의해 접속이 이루어진다.In addition, the substrate 10 bonded to the first surface 1a of the first semiconductor chip 1 with the adhesive layer 3 may have a second second portion in a region corresponding to the side end of the second semiconductor chip 2. The through hole 15b is formed. A circuit pattern 12 extends inside the second through hole 15b, and the circuit pattern 12 is electrically connected to an input / output pad 2c of the second semiconductor chip 2. . That is, the circuit pattern 12 is a direct electrical connection means 20. Of course, the connection means 20 is also connected by gang bonding or tap bonding.

또한, 도4b에 도시된 반도체패키지(110)에서와 같이, 상기 제2반도체칩(2)의 제2면(2b)은 봉지재(40) 외측으로 노출됨으로써, 방열성능이 극대화될 수도 있다.In addition, as in the semiconductor package 110 illustrated in FIG. 4B, the second surface 2b of the second semiconductor chip 2 is exposed to the outside of the encapsulant 40, thereby maximizing heat dissipation performance.

도5a 내지 도5j는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 상태도이다. 여기서는 편의상 도2a에 도시된 반도체패키지(101)의 제조 방법을 위주로 설명한다.5A to 5J are state diagrams illustrating a method of manufacturing a semiconductor package according to the present invention. For convenience, the manufacturing method of the semiconductor package 101 shown in FIG. 2A will be described mainly.

1. 섭스트레이트(10) 제공 단계로서, 수지층(11)을 중심으로 그 표면에는 다수의 도전성 회로패턴(12)이 형성된 섭스트레이트(10)를 제공한다.(도5a 참조)1. As a step of providing a substrate 10, a substrate 10 having a plurality of conductive circuit patterns 12 formed on the surface of the resin layer 11 is provided (see FIG. 5A).

즉, 수지층(11)을 기본층으로 그 표면에는 본드핑거(12a) 및 랜드(12b)를 포함하는 다수의도전성 회로패턴(12)이 형성되어 있고, 상기 본드핑거(12a) 및 랜드(12b)를 제외한 회로패턴(12) 및 수지층(11)은 커버코트(14)로 코팅된 섭스트레이트(10)를 제공한다. 이러한 섭스트레이트(10)는 통상적인 인쇄회로기판, 써킷필름 또는 써킷테이프 등을 이용할 수 있다.That is, a plurality of conductive circuit patterns 12 including bond fingers 12a and lands 12b are formed on the surface of the resin layer 11 as a base layer, and the bond fingers 12a and lands 12b are formed. The circuit pattern 12 and the resin layer 11 except for) provide the substrate 10 coated with the cover coat 14. The substrate 10 may use a conventional printed circuit board, a circuit film or a circuit tape.

2. 접착층 접착 단계로서, 상기 섭스트레이트(10)의 일면에 일정 면적을 갖는 접착층(3)을 접착시킨다. 이러한 접착층(3)으로서는 양면 접착테이프가 바람직하다.(도5b 참조)2. Adhesive layer As an adhesive step, the adhesive layer 3 having a predetermined area is adhered to one surface of the substrate 10. As such an adhesive layer 3, a double-sided adhesive tape is preferable. (See Fig. 5B.)

3. 관통공(15a) 형성 단계로서, 상기 섭스트레이트(10) 및 접착층(3)을 일체로 펀칭하여 일정 크기를 갖는 관통공(15a)을 형성한다.(도5c 참조)3. As the through hole 15a is formed, the substratum 10 and the adhesive layer 3 are integrally punched to form a through hole 15a having a predetermined size (see Fig. 5C).

4. 반도체칩 접착 단계로서, 입출력패드(1c,2c)가 서로 반대 방향에 위치하 도록 제1반도체칩(1) 및 제2반도체칩(2)을 접착시킨 채, 상기 제1반도체칩(1)의 입출력패드(1c)가 상기 섭스트레이트(10)의 관통공(15a)을 통하여 외부로 오픈되도록 상기 접착층(3)에 접착시킨다. 즉, 제1반도체칩(1)은 중앙에 입출력패드(1c)가 형성된 센터패드형 반도체칩을 구비하고, 제2반도체칩(2)은 가장자리에 입출력패드(2c)가 형성된 엣지패드형 반도체칩을 구비하여 상기와 같은 공정을 따른다.(도5d 참조)4. A semiconductor chip bonding step, wherein the first semiconductor chip 1 is bonded to the first semiconductor chip 1 and the second semiconductor chip 2 such that the input / output pads 1c and 2c are located in opposite directions. ) Is bonded to the adhesive layer 3 so that the input / output pad 1c of the c) is opened to the outside through the through hole 15a of the substrate 10. That is, the first semiconductor chip 1 includes a center pad type semiconductor chip having an input / output pad 1c formed at the center thereof, and the second semiconductor chip 2 has an edge pad type semiconductor chip having an input / output pad 2c formed at an edge thereof. It is equipped with the same process as described above (see Figure 5d).

5. 제1전기적 접속단계로서, 상기 제1반도체칩(1)의 입출력패드(1c)와 섭스트레이트(10)의 회로패턴(12)을 도전성와이어와 같은 전기적 접속수단(20)을 이용하여 상호 연결시킨다. 이때, 상기 전기적 접속수단(20)은 섭스트레이트(10)의 관통공(15a)을 통과한다. 물론, 상기 도전성와이어 대신 상기 관통공(15a) 내측으로 회로패턴(12)을 연장 형성하고, 이 회로패턴(12)을 상기 제1반도체칩(10)의 입출력패드(1c)에 접속시킬 수도 있다.(도5e 참조)5. As a first electrical connection step, the input / output pad 1c of the first semiconductor chip 1 and the circuit pattern 12 of the substrate 10 are mutually connected using an electrical connection means 20 such as conductive wire. Connect In this case, the electrical connection means 20 passes through the through hole 15a of the substrate 10. Of course, the circuit pattern 12 may be extended to the inside of the through hole 15a instead of the conductive wire, and the circuit pattern 12 may be connected to the input / output pad 1c of the first semiconductor chip 10. (See Figure 5e)

6. 제1봉지 단계로서, 상기 섭스트레이트(10)의 관통공(15a) 및 접속수단(20)을 에폭시 몰딩 컴파운드 또는 글럽탑과 같은 봉지재(40)를 이용하여 봉지한다.(도5f)6. As a first encapsulation step, the through hole 15a and the connecting means 20 of the substrate 10 are encapsulated using an encapsulant 40 such as an epoxy molding compound or a glove top (FIG. 5F).

7. 제2전기적 접속단계로서, 상기 제2반도체칩(2)의 입출력패드(2c)와 상기 섭스트레이트(10)의 본드핑거(12a)를 도전성와이어와 같은 전기적 접속수단(20)으로 상호 연결한다.(도5g 참조)7. As a second electrical connection step, the input and output pads 2c of the second semiconductor chip 2 and the bond fingers 12a of the substrate 10 are interconnected by electrical connection means 20 such as conductive wires. (See Fig. 5g).

8. 제2봉지 단계로서, 상기 제2반도체칩(2), 접속수단(20) 및 섭스트레이트(10)의 일면을 에폭시 몰딩 컴파운드 또는 글럽탑과 같은 봉지재(40) 를 이용하여 봉지한다.(도5h 참조)8. As a second encapsulation step, one surface of the second semiconductor chip 2, the connecting means 20 and the substrate 10 is encapsulated using an encapsulant 40 such as an epoxy molding compound or a glove top. (See Fig. 5h)

9. 도전성단자(50) 형성 단계로서, 솔더볼 또는 솔더패드와 같은 도전성단자(50)를 섭스트레이트(10)의 랜드(12b)에 형성하여 마더보드에 실장 가능한 형태가 되도록 한다.(도5i 참조)9. In the step of forming the conductive terminal 50, a conductive terminal 50 such as solder balls or solder pads is formed on the land 12b of the substrate 10 so as to be mounted on the motherboard (see FIG. 5I). )

10. 소잉 단계로서, 상기 섭스트레이트(10) 및 봉지재(40)를 일체로 소잉하여 낱개의 반도체패키지가 되도록 한다.10. As a sawing step, the substrate 10 and the encapsulant 40 are sawed integrally to form a single semiconductor package.

여기서, 상기 5 내지 8의 단계는 도6a 내지 도6d에 도시된 바와 같이 변형되어 작업될 수도 있다.Here, the steps 5 to 8 may be modified and work as shown in FIGS. 6A to 6D.

즉, 제2반도체칩(2)의 입출력패드(2c)와 섭스트레이트(10)의 본드핑거(12a)를 먼저 도전성와이어와 같은 전기적 접속수단(20)으로 상호 접속한다.(도6a 참조)In other words, the input / output pads 2c of the second semiconductor chip 2 and the bond fingers 12a of the substrate 10 are first interconnected by electrical connection means 20 such as conductive wires (see Fig. 6A).

이어서, 상기 제1반도체칩(1), 제2반도체칩(2), 접속수단(20) 및 섭스트레이트(10)의 일면을 봉지재(40)로 봉지한다.(도6b 참조)Subsequently, one surface of the first semiconductor chip 1, the second semiconductor chip 2, the connecting means 20, and the substrate 10 is sealed with an encapsulant 40 (see Fig. 6B).

계속해서, 상기 제1반도체칩(1)의 입출력패드(1c)와 섭스트레이트(10)의 관통공(15a) 외주연에 위치한 본드핑거(12a)를 도전성와이어로 상호 접속한다.(도6c 참조)Subsequently, the input / output pad 1c of the first semiconductor chip 1 and the bond finger 12a located at the outer periphery of the through hole 15a of the substrate 10 are interconnected with conductive wires (see Fig. 6C). )

마지막으로, 상기 섭스트레이트(10)의 관통공(15a), 제1반도체칩(1)의 입출력패드(1c) 및 그것에 연결된 전기적 접속수단(20)을 봉지재(40)로 봉지한다.(도6d 참조)Finally, the through hole 15a of the substrate 10, the input / output pad 1c of the first semiconductor chip 1, and the electrical connection means 20 connected thereto are encapsulated with the encapsulant 40. See 6d)

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러 가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서, 본 발명에 의한 반도체패키지에 의하면, 섭스트레이트에 관통공을 형성하고, 상기 관통공을 통하여 센터패드형인 제1반도체칩의 입출력패드가 오픈되도록 하고, 상기 제1반도체칩의 입출력패드가 형성되지 않은 면에는 엣지패드형인 제2반도체칩을 접착시킴으로써 센터패드형 및 엣지패드형 반도체칩을 혼합하여 스택할 수 있는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, a through hole is formed in the substrate, and the input / output pad of the first semiconductor chip having a center pad type is opened through the through hole, and the input / output pad of the first semiconductor chip is formed. By bonding the second semiconductor chip, which is an edge pad type, to the non-surface, the center pad type and the edge pad type semiconductor chips may be mixed and stacked.

또한, 상기 센터패드형 제1반도체칩의 일면에 또다른 센터패드형 제2반도체칩을 접착시킬 수 있음으로써 센터패드형 반도체칩끼리도 스택할 수 있는 효과가 있다.In addition, by attaching another center pad type second semiconductor chip to one surface of the center pad type first semiconductor chip, the center pad type semiconductor chips may also be stacked.

또한, 입출력패드가 형성되지 않은 반도체칩의 일면에 센터패드형 또는 엣지패드형의 다른 반도체칩을 자유롭게 접착시킬 수 있음으로써 반도체칩의 크기 또는 부피에 제한받지 않고, 다수의 반도체칩을 스택할 수 있는 효과가 있다.In addition, it is possible to freely adhere the center pad type or the edge pad type other semiconductor chips to one surface of the semiconductor chip on which the input / output pad is not formed, thereby stacking a plurality of semiconductor chips without being limited by the size or volume of the semiconductor chip. It has an effect.

또한, 전기적 접속수단으로서 도전성와이어 또는 회로패턴을 선택적으로 이용할 수 있음으로써, 반도체칩과 섭스트레이트의 사이의 전기적 연결이 보다 용이해지는 효과가 있다.In addition, since the conductive wire or the circuit pattern can be selectively used as the electrical connection means, there is an effect that the electrical connection between the semiconductor chip and the substrate is easier.

또한, 상기 전기적 접속수단으로서 회로패턴만을 이용했을 경우에는 반도체칩의 일면을 봉지재 외측으로 오픈시킬 수 있어 방열성능을 향상시킬 수 있다.In addition, when only the circuit pattern is used as the electrical connection means, one surface of the semiconductor chip can be opened to the outside of the encapsulant, thereby improving heat dissipation performance.

Claims (16)

평평한 제1면과 이것의 반대면으로서 평평한 제2면을 갖고, 상기 제1면 중앙에는 다수의 입출력패드가 형성된 제1반도체칩과,A first semiconductor chip having a flat first surface and a flat second surface as an opposite surface thereof, and having a plurality of input / output pads formed at the center of the first surface; 평평한 제1면과 이것의 반대면으로서 평평한 제2면을 갖고, 상기 제2면 중앙에 다수의 입출력패드가 형성되며, 자신의 제1면이 상기 제1반도체칩의 제2면에 접착된 제2반도체칩과,A flat first surface and a flat second surface as an opposite surface thereof, and a plurality of input / output pads are formed in the center of the second surface, and the first surface thereof is bonded to the second surface of the first semiconductor chip. 2 semiconductor chip, 평평한 제1면과 이것의 반대면인 제2면을 갖는 수지층에 다수의 도전성 회로패턴이 형성되고, 상기 제2면에는 상기 제1반도체칩의 제1면이 접착되며, 상기 제1반도체칩의 입출력패드와 간섭하지 않토록 중앙에 관통공이 형성된 섭스트레이트와,A plurality of conductive circuit patterns are formed on a resin layer having a first flat surface and a second surface opposite thereto, wherein a first surface of the first semiconductor chip is bonded to the second surface, and the first semiconductor chip Substrate with a through hole formed in the center so as not to interfere with the input / output pad of the 상기 섭스트레이트의 관통공을 관통하여 상기 제1반도체칩의 입출력패드와 상기 섭스트레이트의 회로패턴을 접속시키는 다수의 전기적 접속수단과,A plurality of electrical connection means penetrating through the through holes of the substrate to connect the input / output pad of the first semiconductor chip and the circuit pattern of the substrate; 상기 섭스트레이트의 관통공 및 섭스트레이트의 제2면, 제1반도체칩, 제2반도체칩 및 전기적 접속수단을 봉지하는 봉지재와,An encapsulant for encapsulating the through hole of the substrate and the second surface of the substrate, the first semiconductor chip, the second semiconductor chip, and the electrical connection means; 상기 섭스트레이트의 회로패턴에 융착된 다수의 도전성단자를 포함하고,It includes a plurality of conductive terminals fused to the circuit pattern of the substrate, 상기 제2반도체칩은 자신의 제2면 중앙 외측에 다수의 회로패턴을 갖는 신호전달부재가 접착되고, 상기 신호전달부재는 수지층을 중심으로 그 표면에 도전성 회로패턴이 형성되며, 상기 제2반도체칩의 입출력패드가 전기적 접속수단에 의해 상기 신호전달부재의 회로패턴 일단에 접속되고, 상기 신호전달부재의 회로패턴 타단도 전기적 접속수단에 의해 상기 섭스트레이트의 회로패턴에 접속된 것을 특징으로 하는 반도체패키지.The second semiconductor chip has a signal transmission member having a plurality of circuit patterns bonded to the outside of the center of the second surface of the second semiconductor chip, and the signal transmission member has a conductive circuit pattern formed on the surface of the resin layer. The input / output pad of the semiconductor chip is connected to one end of the circuit pattern of the signal transmission member by an electrical connection means, and the other end of the circuit pattern of the signal transmission member is also connected to the substrate circuit pattern by an electrical connection means. Semiconductor Package. 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 평평한 제1면과 이것의 반대면으로서 평평한 제2면을 갖고, 상기 제1면 중앙에는 다수의 입출력패드가 형성된 제1반도체칩과,A first semiconductor chip having a flat first surface and a flat second surface as an opposite surface thereof, and having a plurality of input / output pads formed at the center of the first surface; 평평한 제1면과 이것의 반대면으로서 평평한 제2면을 갖고, 상기 제2면에 다수의 입출력패드가 형성되어 있으며, 자신의 제1면이 상기 제1반도체칩의 제2면에 접착된 제2반도체칩과,A first flat surface and a flat second surface as an opposite surface thereof, a plurality of input / output pads formed on the second surface, and a first surface of which is adhered to the second surface of the first semiconductor chip; 2 semiconductor chip, 평평한 제1면과 이것의 반대면인 제2면을 갖는 수지층에 다수의 도전성 회로패턴이 형성되고, 상기 제2면에는 상기 제1반도체칩의 제1면이 접착되며, 상기 제1반도체칩의 입출력패드와 간섭하지 않도록 중앙에 제1관통공이 형성된 섭스트레이트와,A plurality of conductive circuit patterns are formed on a resin layer having a first flat surface and a second surface opposite thereto, wherein a first surface of the first semiconductor chip is bonded to the second surface, and the first semiconductor chip Substrate formed with a first through-hole in the center so as not to interfere with the input and output pad of the, 상기 제1반도체칩 및 제2반도체칩의 입출력패드와 상기 섭스트레이트의 회로패턴을 전기적으로 접속시키는 다수의 전기적 접속수단과,A plurality of electrical connection means for electrically connecting the input / output pads of the first semiconductor chip and the second semiconductor chip and the circuit pattern of the substrate; 상기 섭스트레이트의 제1관통공 및 섭스트레이트의 제2면, 제1반도체칩, 제2반도체칩 및 전기적 접속수단을 봉지하는 봉지재와,An encapsulant for encapsulating the first through-hole of the substrate and the second surface of the substrate, the first semiconductor chip, the second semiconductor chip and the electrical connection means; 상기 섭스트레이트에 형성된 회로패턴에 융착된 다수의 도전성단자를 포함하고,It includes a plurality of conductive terminals fused to the circuit pattern formed on the substrate, 상기 제2반도체칩은 상기 제1반도체칩의 폭보다 더 큰 폭을 갖는 동시에, 상기 제1반도체칩의 외측으로 소정 길이 연장된 제2반도체칩의 제1면 내주연에 다수의 입출력패드가 형성되고, The second semiconductor chip has a width larger than that of the first semiconductor chip, and a plurality of input / output pads are formed on an inner circumference of the first surface of the second semiconductor chip extending a predetermined length outward of the first semiconductor chip. Become, 상기 섭스트레이트는 상기 제2반도체칩의 가장자리와 대응되는 부분에 또다른 제2관통공이 형성되고, 상기 제2관통공을 관통해서는 전기적 접속수단으로서 회로패턴이 연장되어 상기 제2반도체칩의 입출력패드에 전기적으로 접속된 동시에, 상기 섭스트레이트의 제1관통공을 관통해서도 전기적 접속수단으로서 회로패턴이 연장되어 상기 제1반도체칩의 입출력패드에 전기적으로 접속된 것을 특징으로 하는 반도체패키지.The second substrate has another second through hole formed at a portion corresponding to the edge of the second semiconductor chip, and a circuit pattern is extended as an electrical connection means through the second through hole, thereby providing an input / output pad of the second semiconductor chip. And a circuit pattern extending as an electrical connection means and electrically connected to an input / output pad of the first semiconductor chip, while being electrically connected to the first through hole of the substrate. 제 7 항에 있어서, 상기 제2반도체칩은 제2면이 봉지재 외측으로 노출된 것을 특징으로 하는 반도체패키지.8. The semiconductor package of claim 7, wherein the second semiconductor chip has a second surface exposed to the outside of the encapsulant. 제 7 항에 있어서, 상기 섭스트레이트의 측면은 상기 섭스트레이트의 제2면과 밀착된 봉지재의 측면과 동일면인 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 7, wherein a side of the substrate is flush with a side of an encapsulant in close contact with the second surface of the substrate. 제 1 항에 있어서, 상기 섭스트레이트는 상기 섭스트레이트의 제2면과 밀착된 봉지재의 측면으로부터 외측으로 소정 길이 더 연장되어 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein the substrates are further extended outward from a side surface of the encapsulant in close contact with the second surface of the substrates. 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990080278A (en) * 1998-04-15 1999-11-05 최완균 Multi-chip package
KR20000040586A (en) * 1998-12-18 2000-07-05 윤종용 Multi chip package having printed circuit substrate
US6118176A (en) * 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
KR20000061707A (en) * 1999-03-30 2000-10-25 김영환 A Package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990080278A (en) * 1998-04-15 1999-11-05 최완균 Multi-chip package
KR20000040586A (en) * 1998-12-18 2000-07-05 윤종용 Multi chip package having printed circuit substrate
KR20000061707A (en) * 1999-03-30 2000-10-25 김영환 A Package
US6118176A (en) * 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame

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