KR20020029251A - Semiconductor package and its manufacturing method - Google Patents
Semiconductor package and its manufacturing method Download PDFInfo
- Publication number
- KR20020029251A KR20020029251A KR1020000060105A KR20000060105A KR20020029251A KR 20020029251 A KR20020029251 A KR 20020029251A KR 1020000060105 A KR1020000060105 A KR 1020000060105A KR 20000060105 A KR20000060105 A KR 20000060105A KR 20020029251 A KR20020029251 A KR 20020029251A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- input
- photoresist
- semiconductor
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 다수의 반도체칩을 적층한 적층형 반도체패키지 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a stacked semiconductor package in which a plurality of semiconductor chips are stacked and a method of manufacturing the same.
통상 반도체패키지는 반도체칩을 외부 환경으로부터 안전하게 보호함은 물론, 그 반도체칩과 마더보드(Mother Board)와의 전기적 신호가 용이하게 교환되도록 한 것을 말한다.In general, the semiconductor package not only protects the semiconductor chip from the external environment, but also means that the electrical signal between the semiconductor chip and the motherboard is easily exchanged.
최근에는 상기한 반도체패키지 내부에 다수의 반도체칩을 적층함으로써 고기능화를 구현한 적층형 반도체패키지가 출시되고 있으며, 이러한 종래의 통상적인 적층형 반도체패키지(100')를 도1에 도시하였다.Recently, a multilayer semiconductor package having high functionality by stacking a plurality of semiconductor chips inside the semiconductor package has been released. Such a conventional multilayer semiconductor package 100 'is shown in FIG.
도시된 바와 같이 통상 수지층(18')을 중심으로 상,하면에 본드핑거(20a') 및 볼랜드(20b')를 갖는 회로패턴(20')이 형성되어 있고, 상기 회로패턴(20')의 표면은 커버코트(23')로 코팅된 회로기판(16')이 구비되어 있다. 또한, 상기 회로기판(16')의 상면 중앙부에는 제1반도체칩(2')이 접착층에 의해 접착되어 있고, 상기제1반도체칩(2')의 상면에는 제2반도체칩(6')이 접착층으로 접착되어 있다. 물론, 상기 제1반도체칩(2') 및 제2반도체칩(6')의 상면에는 다수의 입출력패드(4',8')가 형성되어 있다. 상기 제1반도체칩(2') 및 제2반도체칩(6')의 입출력패드(4',8')는 각각 회로기판(16')에 형성된 회로패턴(20')중 본드핑거(20a')에 도전성와이어(60')로 본딩되어 있다. 또한, 제1반도체칩(2'), 제2반도체칩(6'), 도전성와이어(60') 및 회로기판(16')의 상면은 봉지재(40')로 봉지되어 있다. 상기 회로기판(16')의 하면에 형성된 회로패턴(20')중 볼랜드(20b')에는 다수의 도전성볼(50')이 융착되어 있으며, 이 도전성볼(50')이 차후 마더보드의 소정 패턴에 본딩된다. 도면중 미설명 부호 20c'는 도전성 비아홀이다.As shown, a circuit pattern 20 'having a bond finger 20a' and a borland 20b 'is formed on the upper and lower surfaces of the resin layer 18', and the circuit pattern 20 'is formed. The surface of the circuit board 16 'is coated with a cover coat 23'. In addition, the first semiconductor chip 2 'is bonded to the center of the upper surface of the circuit board 16' by an adhesive layer, and the second semiconductor chip 6 'is attached to the upper surface of the first semiconductor chip 2'. It is bonded by an adhesive layer. Of course, a plurality of input / output pads 4 'and 8' are formed on the upper surfaces of the first semiconductor chip 2 'and the second semiconductor chip 6'. The I / O pads 4 'and 8' of the first semiconductor chip 2 'and the second semiconductor chip 6' are bonded fingers 20a 'of the circuit patterns 20' formed on the circuit board 16 ', respectively. Is bonded to the conductive wire 60 '. In addition, the upper surface of the first semiconductor chip 2 ', the second semiconductor chip 6', the conductive wire 60 ', and the circuit board 16' is sealed with an encapsulant 40 '. A plurality of conductive balls 50 'are fused to the ball lands 20b' among the circuit patterns 20 'formed on the bottom surface of the circuit board 16', and the conductive balls 50 'are subsequently fixed on the motherboard. Bonded to the pattern. In the figure, reference numeral 20c 'denotes a conductive via hole.
이러한 반도체패키지(100')는 제1반도체칩(2') 및 제2반도체칩(6')의 전기적 신호가 도전성와이어(60'), 회로기판(16')의 본드핑거(20a'), 도전성 비아홀(20c'), 볼랜드 (20b') 및 도전성볼(50')을 통해서 마더보드와 교환되며, 두개의 반도체칩이 적층된 상태이므로 반도체패키지가 고용량, 고기능화되고 또한 실장밀도를 높일 수 있는 장점이 있다.In the semiconductor package 100 ', the electrical signals of the first semiconductor chip 2' and the second semiconductor chip 6 'are transmitted to the conductive wire 60', the bond finger 20a 'of the circuit board 16', It is exchanged with the motherboard through the conductive via hole 20c ', the borland 20b', and the conductive ball 50 ', and since the two semiconductor chips are stacked, the semiconductor package can have high capacity, high functionality, and high mounting density. There is an advantage.
그러나, 상기 제1반도체칩의 입출력패드에 본딩되는 도전성와이어와의 접촉을 피하기 위해, 상기 제2반도체칩의 넓이 또는 부피가 상기 제1반도체칩의 넓이 또는 부피보다 반듯이 작아야 하는 단점이 있다. 즉, 상기 제2반도체칩의 부피가 제1반도체칩의 부피와 같거나 클 경우에는 그 제2반도체칩의 저면과 도전성와이어가 상호 쇼트됨으로써 제1반도체칩의 전기적 기능이 마비되는 문제가 있어, 반듯이 그 제2반도체칩의 크기가 제1반도체칩의 크기보다 작아야 한다.However, in order to avoid contact with conductive wires bonded to the input / output pads of the first semiconductor chip, an area or volume of the second semiconductor chip must be smaller than the width or volume of the first semiconductor chip. That is, when the volume of the second semiconductor chip is equal to or larger than the volume of the first semiconductor chip, the bottom surface of the second semiconductor chip and the conductive wire are shorted to each other, thereby causing paralysis of the electrical function of the first semiconductor chip. On the contrary, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip.
이러한 문제는 동일한 크기의 반도체칩을 다수 적층하여야 하는 메모리 반도체패키지(예를 들면 다수의 DRAM을 적층한 반도체패키지)에 적용할 수 없어, 패키징할 수 있는 반도체칩의 종류를 극히 제한시키고 있다.Such a problem cannot be applied to a memory semiconductor package (for example, a semiconductor package in which a plurality of DRAMs are stacked) in which a plurality of semiconductor chips of the same size must be stacked, thereby limiting the types of semiconductor chips that can be packaged.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 동일하거나 또는 더 큰 크기의 반도체칩을 적층할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, to provide a semiconductor package and a method of manufacturing the same or larger semiconductor chips can be stacked.
도1은 종래의 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor package.
도2는 본 발명에 의한 반도체패키지를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package according to the present invention.
도3a 및 도3b는 본 발명의 구체적인 실시예를 도시한 단면도이다.3A and 3B are cross-sectional views showing specific embodiments of the present invention.
도4a 내지 도4g는 본 발명에 의한 반도체패키지의 제조 방법을 설명하기 위한 설명도이다.4A to 4G are explanatory views for explaining a method for manufacturing a semiconductor package according to the present invention.
도5a 내지 도5c는 본 발명에 의한 반도체패키지의 제조 방법중 웨이퍼 상에 포토레지스트를 형성한 후 소잉하는 상태를 도시한 설명도이다.5A to 5C are explanatory views showing a state of sawing after forming a photoresist on a wafer in the method of manufacturing a semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100, 101,102; 본 발명에 의한 반도체패키지100, 101,102; Semiconductor package according to the present invention
1; 제1반도체칩1a,2a,11a,70a; 제1면One; First semiconductor chips 1a, 2a, 11a, 70a; Front page
1b,2b,11b,70b; 제2면1c,2c; 입출력패드1b, 2b, 11b, 70b; Second surface 1c, 2c; I / O pad
2; 제2반도체칩3; 스터드범프2; Second semiconductor chip 3; Stud bump
10; 인쇄회로기판11; 수지층10; A printed circuit board 11; Resin layer
12; 회로패턴12a; 본드핑거12; Circuit pattern 12a; Bondfinger
12b; 볼랜드13; 비아홀12b; Borland 13; Via Hole
14; 커버코트20; 포토레지스트14; Cover coat 20; Photoresist
40; 접속수단50; 봉지재40; Connecting means 50; Encapsulant
60; 도전성볼70; 리드60; Conductive ball 70; lead
71a; 랜드71b; 본드핑거71a; Land 71b; Bondfinger
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성된 제1반도체칩과; 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성되어 있으며, 상기 제1면이 상기 제1반도체칩의 제2면과 마주하여 위치된 제2반도체칩과; 상기 제1반도체칩의 제1면에 접착되어 있으며, 상기 제1반도체칩 및 제2반도체칩의 입출력패드와 전기적 접속수단(도전성와이어)에 의해 연결되고, 마더보드에 실장 가능한 섭스트레이트와; 상기 제1반도체칩의 제2면과 상기 제2반도체칩의 제1면 사이에 접착되고, 두께는 상기 제1반도체칩의 입출력패드에 연결된 전기적 접속수단의 루프 하이트보다 두껍게 형성된 포토레지스트와; 상기 제1반도체칩, 제2반도체칩, 전기적 접속수단 및 섭스트레이트의 일면을 봉지하는 봉지재를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention has a first plane and a second surface which are substantially planar, and the second surface comprises: a first semiconductor chip having a plurality of input / output pads; A second semiconductor chip having a first surface and a second surface that are substantially planar, and having a plurality of input / output pads formed on the second surface, wherein the first surface is positioned to face the second surface of the first semiconductor chip. and; A substrate that is adhered to the first surface of the first semiconductor chip, is connected to the input / output pads of the first semiconductor chip and the second semiconductor chip by electrical connection means (conductive wires), and is mountable on the motherboard; A photoresist bonded between the second surface of the first semiconductor chip and the first surface of the second semiconductor chip, wherein the photoresist is thicker than the loop height of the electrical connection means connected to the input / output pad of the first semiconductor chip; It characterized in that it comprises a first semiconductor chip, a second semiconductor chip, an electrical connection means and an encapsulant for sealing one surface of the substrate.
상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖는 수지층을 중심으로,상기 제1면에는 볼랜드를 갖고 상기 제2면에는 본드핑거를 갖는 회로패턴을 포함하여 이루어진 인쇄회로기판, 써킷필름 또는 서킷테이프중 어느 하나일 수 있다.The substrate includes a circuit pattern having a first planar surface and a second surface having a substantially planar surface, the circuit pattern including a ball land on the first surface and a bond finger on the second surface. It can be either film or circuit tape.
여기서, 상기 볼랜드에는 도전성볼이 더 융착됨이 바람직하다.Here, it is preferable that the conductive ball is further fused to the ball land.
상기 섭스트레이트는 대략 평면인 제1면과 제2면을 갖고, 상기 제1면에는 봉지재 외부로 노출된 랜드가 형성되고, 상기 제2면에는 반도체칩과 전기적 접속수단으로 접속되는 본드핑거를 갖는 다수의 리드일 수도 있다.The substrate has a first plane and a second plane that are substantially planar, and lands exposed to the outside of the encapsulant are formed on the first surface, and bond fingers connected to the semiconductor chip and the electrical connection means are formed on the second surface. It may be a plurality of leads having.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 제조 방법은 섭스트레이트로서 인쇄회로기판, 써킷필름, 써킷테이프 또는 리드 중 어느 하나를 선택하여 제공하는 단계와; 상기 섭스트레이트의 중앙에, 대략 평면인 제1면과 제2면을 가지고, 상기 제2면에는 다수의 입출력패드가 형성되어 있으며, 상기 입출력패드를 제외한 제2면에는 일정 두께의 포토레지스트가 형성된 제1반도체칩을 접착층으로 접착시키는 단계와; 상기 제1반도체칩의 입출력패드와 섭스트레이트를 전기적 접속수단으로 본딩시키는 단계와; 상기 포토레지스트에, 대략 평면인 제1면과 제2면을 가지며, 상기 제2면에는 다수의 입출력패드가 형성된 제2반도체칩을 접착시키는 단계와; 상기 제2반도체칩의 입출력패드와 섭스트레이트를 전기적 접속수단으로 본딩시키는 단계와; 상기 제1반도체칩, 제2반도체칩, 전기적 접속수단 및 섭스트레이트를 봉지재로 봉지하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a semiconductor package according to the present invention to achieve the above object comprises the step of providing any one of a printed circuit board, circuit film, circuit tape or lead as a substrate; In the center of the substrate, the first and second surfaces are substantially planar, and a plurality of input / output pads are formed on the second surface, and a photoresist having a predetermined thickness is formed on the second surface except the input / output pad. Bonding the first semiconductor chip to an adhesive layer; Bonding the input and output pads and the substrate of the first semiconductor chip with electrical connection means; Bonding a second semiconductor chip to the photoresist, the second semiconductor chip having a first planar surface and a second surface, the second surface having a plurality of input / output pads formed thereon; Bonding the input and output pads and the substrate of the second semiconductor chip with electrical connection means; And sealing the first semiconductor chip, the second semiconductor chip, the electrical connection means, and the substrate with an encapsulant.
상기 제1반도체칩은 다수의 반도체칩이 스크라이브 라인을 따라 대략 바둑판 모양으로 형성된 웨이퍼를 제공하는 단계와; 상기 반도체칩의 입출력패드를 제외한 반도체칩 표면에 소정두께의 포토레지스트를 형성하는 단계와; 상기 웨이퍼에서 상기 포토레지스트를 갖는 각각의 반도체칩을 블레이드로 소잉하는 단계에 의해 제공됨이 바람직하다.The first semiconductor chip comprises: providing a wafer in which a plurality of semiconductor chips are formed in a substantially checkered shape along a scribe line; Forming a photoresist having a predetermined thickness on a surface of the semiconductor chip other than the input / output pad of the semiconductor chip; It is preferably provided by sawing each semiconductor chip with said photoresist in said wafer into a blade.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 제1반도체칩과 제2반도체칩 사이에 전기적 접속수단의 루프 하이트보다 두꺼운 포토레지스트를 개재함으로써, 하부에 위치되는 제1반도체칩의 입출력패드와 섭스트레이트 사이를 연결한 전기적 접속수단과 제2반도체칩의 제2면이 상호 간섭하거나 쇼트되지 않고 또한 그 접속수단의 파손을 방지하게 된다.According to the semiconductor package according to the present invention and the manufacturing method as described above, the first semiconductor chip located below by interposing a photoresist thicker than the loop height of the electrical connection means between the first semiconductor chip and the second semiconductor chip. The electrical connection means connected between the input and output pads of the substrate and the second surface of the second semiconductor chip do not interfere with each other or are short-circuited and prevent the connection means from being damaged.
더불어, 동일한 크기의 반도체칩을 다수 적층할 수 있음으로써, 고용량 고기능의 반도체패키지를 제공하게 되고, 또한 섭스트레이트의 패턴 설계 자유도도 높아진다.In addition, by stacking a large number of semiconductor chips of the same size, it is possible to provide a high-capacity, high-performance semiconductor package, and also to increase the degree of freedom of pattern design of the substrate.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2는 본 발명에 의한 반도체패키지(100)를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor package 100 according to the present invention.
도시된 바와 같이, 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)의 주연 근처에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)이 구비되어 있다.As illustrated, the first semiconductor chip 1 has a first plane 1a and a second plane 1b that are substantially planar, and a plurality of input / output pads 1c are formed near the periphery of the second surface 1b. ) Is provided.
또한, 상기 제1반도체칩(1)의 제2면(1b)에는 입출력패드(1c)를 제외한 전영역에 일정두께의 포토레지스트(20)(Photo Resist)가 형성되어 있다. 상기 포토레지스트(20)의 두께는 하기할 전기적 접속수단(예를 들면, 도전성와이어)의 루프하이트(대략 1~5mil 이내)보다 크게 되도록 함이 바람직하다.In addition, a photoresist 20 having a predetermined thickness is formed on the second surface 1b of the first semiconductor chip 1 except for the input / output pad 1c. The thickness of the photoresist 20 is preferably larger than the loop height (about 1 to 5 mils) of the electrical connection means (for example, conductive wire) to be described below.
상기 포토레지스트(20)는 주지된 바와 같이 감광성 수지로서, 구성성분은 Polymer, Solvent, Sensitizer 등으로 이루어져 있으며, 접착성질이 있어, 상기 제1반도체칩(1)의 제2면(1b)에 용이하게 접착된다.As is well known, the photoresist 20 is a photosensitive resin. The photoresist 20 includes a polymer, a solvent, a sensitizer, and the like. Is bonded.
계속해서, 대략 평면인 제1면(2a)과 제2면(2b)을 가지고, 상기 제2면(2b)의 주연 근처에는 다수의 입출력패드(2c)가 형성되어 있으며, 상기 제1면(2a)이 상기 포토레지스트(20)와 접착된 제2반도체칩(2)이 구비되어 있다.Subsequently, the first surface 2a and the second surface 2b are substantially planar, and a plurality of input / output pads 2c are formed near the periphery of the second surface 2b, and the first surface ( 2a) is provided with a second semiconductor chip 2 bonded to the photoresist 20.
여기서, 상기 제2반도체칩(2)의 크기 또는 부피는 상기 제1반도체칩(1)의 크기 또는 부피와 같거나, 크거나 또는 작을 수 있다. 즉, 어떠한 크기의 제2반도체칩(2)도 상기 포토레지스트(20)상에 접착될 수 있다.Here, the size or volume of the second semiconductor chip 2 may be equal to, larger or smaller than the size or volume of the first semiconductor chip 1. That is, the second semiconductor chip 2 of any size may be bonded onto the photoresist 20.
계속해서, 상기 제1반도체칩(1)의 제1면(1a)에는 접착층으로 섭스트레이트(10)가 접착되어 있는데, 상기 섭스트레이트(10)로서는 인쇄회로기판, 써킷필름, 써킷테이프 도는 리드프레임등이 가능하다.Subsequently, the substrate 10 is bonded to the first surface 1a of the first semiconductor chip 1 by an adhesive layer. The substrate 10 includes a printed circuit board, a circuit film, a circuit tape, or a lead frame. Etc. are possible.
또한, 상기 제1반도체칩(1), 제2반도체칩(2), 전기적 접속수단(40)과 상기 섭스트레이트(10)의 일면은 에폭시 몰딩 컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top)과 같은 봉지재(50)로 봉지되어 상기의 것들이 외부환경으로부터 보호되도록 되어 있다.In addition, one surface of the first semiconductor chip 1, the second semiconductor chip 2, the electrical connection means 40 and the substratum 10 may be formed of an epoxy molding compound or a glop top. Encapsulated with an encapsulant 50 such as to protect the above from the external environment.
도3a 및 도3b는 본 발명의 구체적 실시예에 의한 반도체패키지(101,102)를 도시한 단면도이다.3A and 3B are cross-sectional views illustrating semiconductor packages 101 and 102 according to a specific embodiment of the present invention.
먼저 도2의 반도체패키지(101)를 참조하면, 대략 평면인 제1면(1a)과제2면(1b)을 가지고, 상기 제2면(1b)의 주연 근처에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)이 구비되어 있다.First, referring to the semiconductor package 101 of FIG. 2, the first and second surfaces 1a and 1b are substantially planar, and a plurality of input / output pads 1c are disposed near the periphery of the second surface 1b. The first semiconductor chip 1 formed is provided.
또한, 상기 제1반도체칩(1)의 제2면(1b)에는 입출력패드(1c)를 제외한 전영역에 일정두께의 포토레지스트(20)(Photo Resist)가 형성되어 있다. 상기 포토레지스트(20)의 두께는 하기할 전기적 접속수단의 루프하이트(대략 1~5mil 이내)보다 두껍께 되도록 형성함이 바람직하다.In addition, a photoresist 20 having a predetermined thickness is formed on the second surface 1b of the first semiconductor chip 1 except for the input / output pad 1c. The thickness of the photoresist 20 is preferably formed to be thicker than the loop height (about 1-5 mils or less) of the electrical connection means to be described below.
상기 포토레지스트(20)는 주지된 바와 같이 감광성 수지로서, 구성성분은 Polymer, Solvent, Sensitizer 등으로 이루어져 있으며, 접착성질이 있어, 상기 제1반도체칩(1)의 제2면(1b)에 용이하게 접착된다.As is well known, the photoresist 20 is a photosensitive resin. The photoresist 20 includes a polymer, a solvent, a sensitizer, and the like. Is bonded.
계속해서, 대략 평면인 제1면(2a)과 제2면(2b)을 가지고, 상기 제2면(2b)의 주연 근처에는 다수의 입출력패드(2c)가 형성되어 있으며, 상기 제1면(2a)이 상기 포토레지스트(20)와 접착된 제2반도체칩(2)이 구비되어 있다.Subsequently, the first surface 2a and the second surface 2b are substantially planar, and a plurality of input / output pads 2c are formed near the periphery of the second surface 2b, and the first surface ( 2a) is provided with a second semiconductor chip 2 bonded to the photoresist 20.
여기서, 상기 제2반도체칩(2)의 크기 또는 부피는 상기 제1반도체칩(1)의 크기 또는 부피와 같거나, 크거나 또는 작을 수 있다. 즉, 어떠한 크기의 제2반도체칩(2)도 상기 포토레지스트(20)상에 접착될 수 있다.Here, the size or volume of the second semiconductor chip 2 may be equal to, larger or smaller than the size or volume of the first semiconductor chip 1. That is, the second semiconductor chip 2 of any size may be bonded onto the photoresist 20.
계속해서, 상기 제1반도체칩(1)의 제1면(1a)에는 접착층으로 섭스트레이트가 접착되어 있는데, 도면에서는 상기 섭스트레이트의 한 예로서 인쇄회로기판(10)이 도시되어 있다.Subsequently, the substrate is bonded to the first surface 1a of the first semiconductor chip 1 by an adhesive layer. In the drawing, the printed circuit board 10 is shown as an example of the substrate.
상기 섭스트레이트는 대략 평면인 제1면(11a)과 제2면(11b)을 갖는 수지층(11)을 중심으로, 상기 제1면(11a)에는 볼랜드(12b)를 갖고 상기 제2면(11b)에는 본드핑거(12a)를 갖는 회로패턴(12)이 형성되어 있다. 상기 회로패턴(12)은 주지된 바와 같이 구리박막(Cu Foil)이며, 이러한 구조는 인쇄회로기판(10)뿐만 아니라, 써킷필름 또는 써킷테이프도 가능하다. 여기서, 상기 섭스트레이트로서 인쇄회로기판, 써킷필름, 또는 써킷테이프 모두 가능하며, 어느 하나로 한정하는 것은 아니다.The substrate has a resin layer 11 having a first plane 11a and a second plane 11b that are substantially planar, and has a ball land 12b on the first plane 11a and the second plane ( 11b), a circuit pattern 12 having a bond finger 12a is formed. The circuit pattern 12 is a copper foil (Cu Foil), as is well known, this structure may be a circuit film or a circuit tape as well as the printed circuit board 10. Here, the substrate may be a printed circuit board, a circuit film, or a circuit tape, but is not limited thereto.
또한, 상기 인쇄회로기판(10)은 상기 수지층(11)의 제1면(11a)과 제2면(11b)에 형성된 회로패턴(12)이 도전성 비아홀(13)에 의해 상호 연결되어 있으며, 상기 볼랜드(12b) 및 본드핑거(12a)를 제외한 회로패턴(12) 및 수지층(11) 표면은 커버코트(14)로 코팅되어 있다. 상기 커버코트(14)는 통상적인 절연성 고분자 수지이다.In addition, the printed circuit board 10 has circuit patterns 12 formed on the first and second surfaces 11a and 11b of the resin layer 11 connected to each other by conductive via holes 13. The surface of the circuit pattern 12 and the resin layer 11 except for the borland 12b and the bond finger 12a is coated with a cover coat 14. The cover coat 14 is a conventional insulating polymer resin.
또한, 상기 제1반도체칩(1) 및 제2반도체칩(2)의 입출력패드(1c,2c)는 상기 인쇄회로기판(10)의 본드핑거(12a)와 전기적 접속수단(40)에 의해 상호 본딩되어 있다. 상기 접속수단(40)은 통상적인 골드와이어(Au Wire) 또는 알루미늄와이어(Al Wire)와 같은 도전성와이어이다.In addition, the input and output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 are mutually connected by the bond fingers 12a of the printed circuit board 10 and the electrical connection means 40. Bonded The connection means 40 is a conductive wire such as a conventional gold wire (Au Wire) or aluminum wire (Al Wire).
이와 같이 전기적 접속수단(40)의 루프 하이트를 작게 형성하는 방법은 통상적인 리버스 와이어 본딩(Reverse Wire Bonding), 엣지 본딩(Wedge Bonding) 방법 등을 사용함으로써 가능하다.Thus, the method of forming the loop height of the electrical connection means 40 small is possible by using the conventional reverse wire bonding, an edge bonding method, or the like.
상기 리버스 와이어 본딩 방법의 일례를 간단히 설명하면 다음과 같다.An example of the reverse wire bonding method is briefly described as follows.
먼저, 제1반도체칩(1) 또는 제2반도체칩(2)의 입출력패드(1c,2c)상에 먼저 전기적 접속수단(40)으로 스터드범프(3)(Stud Bump, 대략 볼(Ball) 모양)를 형성한후, 그 접속수단(40)의 단부를 끊는다. 이어서 접속수단(40)의 일단을 섭스트레이트(10)의 본드핑거(12a)에 접속(First Bonding)하고, 그 타단을 제1반도체칩(1) 또는 제2반도체칩(2)의 입출력패드(2c)상에 형성된 스터드범프(3)에 스티치 본딩(Stitch bonding, Second Bonding이라고도 함)한다. 이러한 리버스 와이어 본딩은 종래와 마찬가지로 써모소닉 Au 볼 본딩(Thermosonic Au Ball Bonding, 본딩시 초음파 에너지와 동시에 본딩하고자 하는 영역에 열을 주어 본딩하는 방법)시 사용되는 캐필러리를 이용한다.First, on the input / output pads 1c and 2c of the first semiconductor chip 1 or the second semiconductor chip 2, the stud bump 3 is formed into the stud bumps 3 by the electrical connection means 40. ), The end of the connecting means 40 is cut off. Next, one end of the connecting means 40 is first bonded to the bond finger 12a of the substrate 10, and the other end thereof is an input / output pad of the first semiconductor chip 1 or the second semiconductor chip 2. Stitch bonding (also called Stitch bonding, Second Bonding) is performed on the stud bump 3 formed on 2c). The reverse wire bonding uses a capillary used during thermosonic Au ball bonding (a method of bonding heat by bonding heat to an area to be bonded simultaneously with ultrasonic energy during bonding).
또한, 상기 리버스 와이어 본딩 대신에 상기 접속수단(40)의 단부를 제1반도체칩(1) 또는 제2반도체칩(2)의 입출력패드(1c,2c)상에 엣지(Wedge) 또는 리본(Ribbon) 본딩하여 접속하는 방법도 있다. 상기 엣지 또는 리본 본딩 방법은 주지된 바와 같이 종래의 울트라소닉 Al 엣지 본딩(Ultrasonic Al Wedge Bonding, 엣지에 초음파 진동 에너지만을 주어 그 마찰열로 본딩하는 방법으로서 제1,2본딩 영역 모두 엣지 형태로 형성됨)에 사용되는 엣지를 이용한다.In addition, instead of the reverse wire bonding, an end portion of the connecting means 40 is edged or ribboned on the input / output pads 1c and 2c of the first semiconductor chip 1 or the second semiconductor chip 2. ) There is also a method of bonding and connecting. The edge or ribbon bonding method is conventionally known as Ultrasonic Al Wedge Bonding (Ultrasonic Al Wedge Bonding, a method of bonding only the ultrasonic vibration energy to the edge and bonding the frictional heat to the first and second bonding areas are formed in the edge shape) Use the edge used for.
이러한 본딩 방법에 의해 상기 접속수단(40)의 루프 하이트는 최대 5mil에서 최소 1mil(1mil=0.0254mm)까지 형성 가능하다. 따라서, 상기 포토레지스트(20)의 두께는 최소 1mil까지도 가능하다.By this bonding method, the loop height of the connecting means 40 can be formed from a maximum of 5 mils to a minimum of 1 mil (1 mil = 0.0254 mm). Therefore, the thickness of the photoresist 20 may be at least 1 mil.
물론, 상기 리버스 와이어 본딩, 엣지 본딩, 리본 본딩 및 탭 본딩 방법 외에 종래의 노말 와이어 본딩(Normal Wire Bonding) 방법도 사용할 수 있는데, 상기와 같은 노말 와이어 본딩 방법을 이용했을 경우에는 상기 포토레지스트(20)의 두께를 더욱 엄격히 제어해야 한다. 이때 바람직한 포토레지스트(20)의 두께는 전술한 바와 같이 대략 5mil 이내가 된다.Of course, in addition to the reverse wire bonding, edge bonding, ribbon bonding, and tab bonding methods, a conventional normal wire bonding method may also be used. When the normal wire bonding method is used, the photoresist 20 ) The thickness of the control should be tighter. At this time, the thickness of the preferred photoresist 20 is within about 5 mil as described above.
또한, 상기 제1반도체칩(1), 제2반도체칩(2), 전기적 접속수단(40)과 상기 인쇄회로기판(10)의 일면은 에폭시 몰딩 컴파운드(Epoxy Molding Compound) 또는 글럽탑(Glop Top)과 같은 봉지재(50)로 봉지되어 상기의 것들이 외부환경으로부터 보호되도록 되어 있다.In addition, one surface of the first semiconductor chip 1, the second semiconductor chip 2, the electrical connection means 40 and the printed circuit board 10 may be formed of an epoxy molding compound or a glop top. It is encapsulated with an encapsulant 50 such as) so that the above are protected from the external environment.
마지막으로, 상기 인쇄회로기판(10)의 볼랜드(12b)에는 솔더볼과 같은 도전성볼(60)이 융착되어 차후 마더보드(Mother Board)에 실장 가능하게 되어 있다.Finally, conductive balls 60, such as solder balls, are fused to the ball lands 12b of the printed circuit board 10 to be mounted on a motherboard later.
계속해서, 도3의 반도체패키지(102)에서와 같이 섭스트레이트로서 다수의 리드(70)가 이용될 수도 있다. 즉, 대략 평면인 제1면(70a)과 제2면(70b)을 갖고, 상기 제1면(70a)에는 봉지재(50) 외부로 노출된 랜드(71a)가 형성되고, 상기 제2면(70b)에는 제1반도체칩(1) 및 제2반도체칩(2)과 전기적 접속수단(40)으로 접속되는 본드핑거(71b)를 갖는 구리(Cu) 또는 철(Fe) 계열의 리드(70)일 수도 있다.Subsequently, a plurality of leads 70 may be used as the substrate as in the semiconductor package 102 of FIG. That is, the first surface 70a and the second surface 70b which are substantially planar, and the land 71a exposed to the outside of the encapsulant 50 are formed on the first surface 70a, and the second surface is formed. A copper (Cu) or iron (Fe) series lead 70 having a bond finger 71b connected to the first semiconductor chip 1 and the second semiconductor chip 2 by an electrical connection means 40 is formed in the 70b. )
여기서, 상기 랜드(71a)를 제외한 리드(70)의 제1면(70a)은 화학용액에 의한 부분 에칭 또는 할프 에칭(Half Etching)에 의해 그 두께가 더 얇게 되어 있음으로써 상기 랜드(71a)만이 봉지재(50) 외측으로 노출되고, 나머지 부분은 봉지재(50) 내측에 위치하게 된다. 따라서 상기 리드(70)는 봉지재(50)로부터 쉽게 이탈되거나 빠지지 않게 된다.Here, the first surface 70a of the lead 70 except for the land 71a is thinner by partial etching or half etching with a chemical solution, so that only the land 71a is formed. The encapsulant 50 is exposed to the outside, and the remaining part is positioned inside the encapsulant 50. Therefore, the lead 70 is not easily separated or removed from the encapsulant 50.
도4a 내지 도4g는 본 발명에 의한 반도체패키지의 제조 방법을 설명하기 위한 설명도이다.4A to 4G are explanatory views for explaining a method for manufacturing a semiconductor package according to the present invention.
1. 섭스트레이트 제공 단계로서, 인쇄회로기판(10), 써킷필름, 써킷테이프또는 리드(70) 중 어느 하나를 선택하여 섭스트레이트로서 제공한다. 이하에서는 상기 인쇄회로기판(10)을 예로 하여 설명하지만, 이것만으로 본 발명을 한정하는 것은 아니다.(도4a 참조)1. As a substrate providing step, any one of the printed circuit board 10, the circuit film, the circuit tape or the lead 70 is selected and provided as a substrate. Hereinafter, the printed circuit board 10 will be described as an example, but the present invention is not limited only to this. (See Fig. 4A.)
상기 인쇄회로기판(10)은 전술한 바와 같이 대략 평면인 제1면(11a)과 제2면(11b)을 갖는 수지층(11)을 중심으로, 상기 제1면(11a)에는 볼랜드(12b)를 제2면(11b)에는 본드핑거(12a)를 갖는 회로패턴(12)이 형성되어 있고, 상기 볼랜드(12b) 및 본드핑거(12a)를 제외한 나머지 회로패턴(12) 및 수지층(11)의 표면은 커버코트(14)로 코팅되어 있다.As described above, the printed circuit board 10 has a resin layer 11 having a first plane 11a and a second plane 11b that are substantially planar, and a ball land 12b on the first surface 11a. The circuit pattern 12 having the bond finger 12a is formed on the second surface 11b, and the remaining circuit patterns 12 and the resin layer 11 except for the borland 12b and the bond finger 12a are formed. The surface of) is coated with a cover coat 14.
2. 제1반도체칩 접착 단계로서, 상기 인쇄회로기판(10)에서 수지층(11)의 제2면(11b) 중앙부에 접착층을 개재하여 대략 평면인 제1면(1a)과 제2면(1b)을 가지고, 상기 제2면(1b)에는 다수의 입출력패드(1c)가 형성된 제1반도체칩(1)을 접착한다. 이때, 상기 입출력패드(1c)를 제외한 제2면(1b) 전체에는 일정두께의 포토레지스트(20)가 미리 도포된 제1반도체칩(1)을 이용한다. 바람직하기로 상기 포토레지스트(20)의 두께는 대략 1~5mil 사이로 형성된 것이 적당하다.2. A first semiconductor chip bonding step, wherein the first surface 1a and the second surface of the printed circuit board 10 which are substantially planar through an adhesive layer in the center of the second surface 11b of the resin layer 11 ( 1b), the first semiconductor chip 1 having a plurality of input / output pads 1c formed thereon is bonded to the second surface 1b. In this case, the first semiconductor chip 1 to which the photoresist 20 having a predetermined thickness is coated in advance is used for the entire second surface 1b except for the input / output pad 1c. Preferably, the thickness of the photoresist 20 is suitably formed between about 1 to 5 mils.
이와 같이 포토레지스트(20)가 형성된 반도체칩의 제조 방법을 도5a 내지 도5c를 참조하여 간단히 설명하면 다음과 같다.A method of manufacturing a semiconductor chip in which the photoresist 20 is formed as described above will be briefly described with reference to FIGS. 5A to 5C.
먼저 도5a에 도시된 바와 같이 웨이퍼(w)의 전면(f)에는 다수의 반도체칩(c)이 스크라이브 라인(s, Scribe Line)을 경계로 하여 대략 바둑판 모양으로 형성되어 있다. 통상 이러한 웨이퍼(w)는 상기 스크라이브 라인(s)을 따라 다이아몬드 블레이드(b)로 소잉되어 낱개의 반도체칩(c)으로 분리된다.First, as illustrated in FIG. 5A, a plurality of semiconductor chips c are formed in a substantially checkerboard shape on the front surface f of the wafer w with the scribe line s as a boundary. Typically, such a wafer w is sawed with a diamond blade b along the scribe line s and separated into individual semiconductor chips c.
그러나 본 발명은 먼저 도5b에 도시된 바와 같이 웨이퍼(w)의 각 반도체칩(c) 표면에 일정두께의 포토레지스트(20)를 형성한다. 이러한 포토레지스트(20)의 형성 방법은 통상 스크린 프린팅 방법을 이용하거나 또는 웨이퍼 전면 전체에 포토레지스트(20)를 도포한 후 상기 스크라이브 라인(s)에 해당하는 영역을 노광하여 제거함으로써 형성 가능하다.However, in the present invention, as shown in FIG. 5B, a photoresist 20 having a predetermined thickness is formed on the surface of each semiconductor chip c of the wafer w. The photoresist 20 may be formed by using a screen printing method or by applying the photoresist 20 to the entire surface of the wafer and then exposing and removing a region corresponding to the scribe line s.
계속해서, 도5c에 도시된 바와 같이 다이아몬드 블레이드(b)를 이용하여, 상기 웨이퍼(w)의 각 스크라이브 라인(s)을 따라 소잉함으로써 낱개의 반도체칩(c)을 얻게 된다.Subsequently, as shown in Fig. 5C, by using the diamond blade b, sawing along each scribe line s of the wafer w yields a single semiconductor chip c.
3. 전기적 접속 단계로서, 상기 제1반도체칩(1)의 입출력패드(1c)와 인쇄회로기판(10)의 본드핑거(12a)를 전기적 접속수단(30)으로 접속한다. 여기서 상기 전기적 접속수단(30)은 골드와이어 또는 알루미늄와이어와 같은 도전성와이어이다.(도4c 참조)3. In the electrical connection step, the input / output pad 1c of the first semiconductor chip 1 and the bond finger 12a of the printed circuit board 10 are connected to the electrical connection means 30. The electrical connection means 30 is a conductive wire such as a gold wire or an aluminum wire (see FIG. 4C).
또한 상기 접속 방법은 전술한 스터드 범프를 이용한 리버스 와이어 본딩, 엣지 본딩, 리본 본딩 등을 이용함으로써, 그 루프 하이트를 대략 1~5mil 사이가 되도록 함이 바람직하다. 물론, 통상적인 노말 와이어 본딩 방법도 사용할 수 있다.In addition, the connection method preferably uses reverse wire bonding, edge bonding, ribbon bonding, etc. using the stud bumps described above, so that the loop height is between about 1 to 5 mils. Of course, conventional normal wire bonding methods can also be used.
4. 제2반도체칩 접착 단계로서, 상기 포토레지스트(20)에, 대략 평면인 제1면(2a)과 제2면(2b)을 가지고 상기 제2면(2b)에는 다수의 입출력패드(2c)가 형성된 제2반도체칩(2)을 접착한다.(도4d 참조)4. A second semiconductor chip bonding step, wherein the photoresist 20 has a first plane 2a and a second plane 2b which are substantially planar, and a plurality of input / output pads 2c on the second surface 2b. Is bonded to the second semiconductor chip 2 (see FIG. 4D).
5. 전기적 접속 단계로서, 상기 제2반도체칩(2)의 입출력패드(2c)와 인쇄회로기판(10)의 본드핑거(12a)를 전기적 접속수단(30)으로 본딩한다.(도4e 참조)5. In the electrical connection step, the input / output pad 2c of the second semiconductor chip 2 and the bond finger 12a of the printed circuit board 10 are bonded with the electrical connection means 30 (see Fig. 4e).
6. 봉지 단계로서, 상기 제1반도체칩(1), 제2반도체칩(2), 전기적 접속수단(30) 및 인쇄회로기판(10)을 봉지재(50)로 봉지한다.(도4f 참조)6. In the encapsulation step, the first semiconductor chip 1, the second semiconductor chip 2, the electrical connection means 30 and the printed circuit board 10 are encapsulated with an encapsulant 50 (see Fig. 4f). )
7. 도전성볼 융착 단계로서, 상기 인쇄회로기판(10)의 볼랜드(12b)에 솔더볼과 같은 도전성볼(60)을 융착하여 마더보드에 실장 가능한 형태가 되도록 한다.(도4g 참조)7. As a conductive ball fusion step, the conductive ball 60 such as solder ball is fused to the ball land 12b of the printed circuit board 10 so as to be mountable on the motherboard (see Fig. 4g).
만약, 상기 섭스트레이트로서 인쇄회로기판(10), 써킷필름 또는 써킷테이프를 이용하지 않고 리드(70)를 이용했을 경우에는 물론, 상기 도전성볼(60) 융착 단계가 생략될 수도 있다.If the lead 70 is used without using the printed circuit board 10, the circuit film, or the circuit tape as the substrate, the fusion step of the conductive balls 60 may be omitted.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 제1반도체칩과 제2반도체칩 사이에 전기적 접속수단의 루프 하이트보다 두꺼운 포토레지스트가 개재됨으로써, 하부에 위치되는 제1반도체칩의 입출력패드와 섭스트레이트 사이를 연결하는 전기적 접속수단과 제2반도체칩의 제2면이 상호 간섭하거나 쇼트되지 않고 또한 그 접속수단의 파손을 방지하는 효과가 있다.Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, the photoresist thicker than the loop height of the electrical connection means is interposed between the first semiconductor chip and the second semiconductor chip, whereby the input and output of the first semiconductor chip located below The electrical connecting means connecting the pad and the substrate and the second surface of the second semiconductor chip do not interfere or short circuit with each other, and there is an effect of preventing breakage of the connecting means.
더불어, 다양한 크기의 반도체칩을 다수 적층할 수 있음으로써, 고용량 고기능의 반도체패키지를 제공하게 되고, 또한 섭스트레이트의 패턴 설계 자유도도 높아지는 효과가 있다.In addition, by stacking a plurality of semiconductor chips of various sizes, it is possible to provide a high-capacity and high-performance semiconductor package, and also has the effect of increasing the degree of freedom in pattern design of the substrate.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000060105A KR20020029251A (en) | 2000-10-12 | 2000-10-12 | Semiconductor package and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000060105A KR20020029251A (en) | 2000-10-12 | 2000-10-12 | Semiconductor package and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020029251A true KR20020029251A (en) | 2002-04-18 |
Family
ID=19693197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000060105A KR20020029251A (en) | 2000-10-12 | 2000-10-12 | Semiconductor package and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020029251A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020056283A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Structure of stack type muli chip semiconductor package and manufacture method the same |
| KR20030027413A (en) * | 2001-09-28 | 2003-04-07 | 삼성전자주식회사 | Multi chip package having spacer that is inserted between chips and manufacturing method thereof |
| KR20030083306A (en) * | 2002-04-20 | 2003-10-30 | 삼성전자주식회사 | A memory card |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323060A (en) * | 1993-06-02 | 1994-06-21 | Micron Semiconductor, Inc. | Multichip module having a stacked chip arrangement |
| JPH1027880A (en) * | 1996-07-09 | 1998-01-27 | Sumitomo Metal Mining Co Ltd | Semiconductor device |
| JPH1070232A (en) * | 1996-07-26 | 1998-03-10 | Honeywell Inc | Chip stack and arrangement for fixing capacitor |
| JPH11204720A (en) * | 1998-01-14 | 1999-07-30 | Sharp Corp | Semiconductor device and its manufacture |
| KR19990069438A (en) * | 1998-02-09 | 1999-09-06 | 김영환 | Chip stack package |
-
2000
- 2000-10-12 KR KR1020000060105A patent/KR20020029251A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323060A (en) * | 1993-06-02 | 1994-06-21 | Micron Semiconductor, Inc. | Multichip module having a stacked chip arrangement |
| JPH1027880A (en) * | 1996-07-09 | 1998-01-27 | Sumitomo Metal Mining Co Ltd | Semiconductor device |
| JPH1070232A (en) * | 1996-07-26 | 1998-03-10 | Honeywell Inc | Chip stack and arrangement for fixing capacitor |
| JPH11204720A (en) * | 1998-01-14 | 1999-07-30 | Sharp Corp | Semiconductor device and its manufacture |
| KR19990069438A (en) * | 1998-02-09 | 1999-09-06 | 김영환 | Chip stack package |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020056283A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Structure of stack type muli chip semiconductor package and manufacture method the same |
| KR20030027413A (en) * | 2001-09-28 | 2003-04-07 | 삼성전자주식회사 | Multi chip package having spacer that is inserted between chips and manufacturing method thereof |
| KR20030083306A (en) * | 2002-04-20 | 2003-10-30 | 삼성전자주식회사 | A memory card |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100260997B1 (en) | Semiconductor package | |
| US6982488B2 (en) | Semiconductor package and method for fabricating the same | |
| KR100716871B1 (en) | Carrier frame for semiconductor package and semiconductor package using it and its manufacturing method | |
| JP2003078106A (en) | Chip-stacked package and its manufacturing method | |
| KR20020015214A (en) | Semiconductor package | |
| KR20020029251A (en) | Semiconductor package and its manufacturing method | |
| KR100549311B1 (en) | Semiconductor package | |
| KR100600176B1 (en) | Semiconductor package | |
| KR100646468B1 (en) | Semiconductor package | |
| KR100610916B1 (en) | Semiconductor package | |
| KR100549312B1 (en) | Semiconductor package and its manufacturing method | |
| KR100610917B1 (en) | Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same | |
| KR100381839B1 (en) | Semiconductor package | |
| KR100623317B1 (en) | Semiconductor package | |
| KR100600213B1 (en) | Semiconductor package | |
| KR100633884B1 (en) | Manufacturing method of semiconductor package | |
| KR100352115B1 (en) | Semiconductor package | |
| KR940006578B1 (en) | Semicondoctor package and manufacturing method thereof | |
| KR100520602B1 (en) | Stacking structure of semiconductor chip | |
| KR100369387B1 (en) | semiconductor package and its manufacturing method | |
| KR100501878B1 (en) | Semiconductor package | |
| KR20020020088A (en) | semiconductor package and its manufacturing method | |
| KR100406447B1 (en) | semiconductor package and its manufacturing method | |
| KR20000074351A (en) | semi-conductor package and manufacturing method thereof | |
| KR20010058580A (en) | semiconductor package and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |