JPH1070232A - Chip stack and arrangement for fixing capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize effective fixing and connection of a decoupling capacitor while suppressing the effect of propagation delay and a transmission line by providing a planar spacer bonded through a bonding pad on a first die and secured through an adhesive layer, and a second die to be secured to the planar spacer. SOLUTION: A part of a semiconductor package 14 includes a die fixing face 16 and a bonding pad 18. A chip 20 includes a wire bonding pad 26. Electrical connection is made between the chip 20 and the package 14 through the wire bonding pad 26 and a thin wire 28 having a wire bond connection at the package bonding pad 18. A spacer 30 is then bonded to a surface 24 through a nonconductive adhesive layer 36 and a chip 40 is bonded to the surface 34 of the spacer 30 through an adhesive layer 38. Electrical connection between the chip 40 and the package 14 is made through the thin wire 28 wire bonded to a die bond pad 46 through the package bonding pad 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (IC).
It relates to assemblies, and more particularly to stack arrangements for semiconductor dies or chips.

[0002]

2. Description of the Related Art Semiconductor technology has shown a dramatic trend toward higher speeds and higher densities of integrated circuits with the overall reduction in device size. Generally, integrated circuit chips are assembled in integrated circuit packages that provide electrical connections from external systems to the integrated circuit. Without the attendant improvements in IC packaging, many of the advantages of high device speed will be lost due to interconnect propagation delays and the effects of transmission lines on integrated circuit packages and circuit board assemblies.

[0003] Many IC applications require a decoupling capacitor. One example of such an application is that some IC devices need to be insensitive to impact from ionizing radiation. The basic effect of ionizing radiation is the generation of electron-hole pairs in the semiconductor material. In the case of an IC having a supply voltage and a ground voltage, the effect of the irradiation is that a large current occurs between the supply voltage and the ground voltage in the chip. Another effect is that current from the power supply encounters inductance in the connecting leads from the power supply. As a result, the on-chip voltage is essentially reduced. The solution is to place a capacitor across the IC power supply so that it is charged to the chip supply voltage.
Is to be placed as close as possible to

[0004]

Accordingly, the propagation delay is small, the influence of the transmission line is small, the effective attachment and connection of the decoupling capacitor is possible, and the chip packaging density is increased. There is a need to provide a packaging arrangement that allows more IC functions to be implemented per unit volume of space.

[0005]

The present invention comprises, in a first aspect, a first die secured to a die attach surface, a wire extending from a bonding pad on the first die to an external bonding pad. A bond, a planar spacer at least partially bonded by a bonding pad on the first die and in a space secured by an adhesive layer, a spacer having a thickness away from a wire bond connected to the first die These and other needs are addressed by providing a chip stack arrangement that includes a second die secured to the second die and wire bonds extending from pads on the second die to external bonding pads.

In a second aspect, the spacer is integral with the second die.

In a third aspect, a spacer has an outer layer and a central layer, both having electrically connected surfaces.
The second die is secured by a conductive bonding material. The wire bonds connect the conductive surface of the outer layer to a reference voltage.

In a fourth aspect, a conductive spacer is used for mounting and connecting a capacitor. A capacitor having opposing conductive surfaces for electrical connection has one surface directly attached to the conductive surface of the spacer and a wire bond connection made to the other surface. When using an elongated capacitor with opposing conductive ends, an additional dielectric layer was provided on the conductive surface of the spacer, a metal layer was provided on the surface of the dielectric layer, the capacitor was mounted and connected by a conductive material. Provide an opening that extends into the metal / dielectric layer.

[0009]

DETAILED DESCRIPTION OF THE INVENTION The chip stack arrangement is shown generally at 10 in the drawings. As shown in FIG. 1, a portion of a semiconductor package 14 includes a die attach surface 16 for receiving a semiconductor die or chip, and a package or substrate 1.
4 on the bonding pad 18. First chip 20 is mounted on surface 16 by conventional means. Chip 20 includes surfaces 22, 24, and wire bonding pads 26 for making electrical connections around surface 24. Package 14 is chip 20
Or package 14 may be part of a multi-chip module. Package or substrate 14 includes bonding pads 18 for making electrical connections to package conductive paths (not shown). Chip 20 and package 1
The electrical connection between 4 is made by a thin wire 28 having a wire bond connection at the wire bond pad 26 and the package bond pad 18. For example, aluminum or gold wire can be used, wedge bonding or ball bonding can be used. Automatic tape bonding (TAB) can also be used.

Further, the arrangement 10 is arranged such that the surface 24 of the chip 20
And a flat plate spacer 30 having a lower surface 32 adhered thereto. In addition, the spacer 30 includes the upper surface 34, and various materials and configurations are possible depending on applications. Materials such as silicon have good thermal conductivity for heat dissipation and match the coefficients of thermal expansion of chips 20 and 40. In addition, the silicon can be easily machined, so that the thickness can be properly controlled to obtain precise spacing. In FIG.
The spacers 30 are made of silicon and have flat plate dimensions, or the surface 24 of the chip 20 within an area defined at least in part by the bonding pads 26.
It has a plane size that fits properly on top. A spacer size of about 40 mils smaller than the overlying chip has been found to be sufficient for the prototype. In FIG. 1, generally, after making a wire bond connection to chip 20, spacer 30 is adhered to surface 24 using a non-conductive adhesive layer 36. It is desirable to use epoxy as the adhesive. Next, the chip 40 is bonded onto the surface 34 of the spacer 30 by an adhesive layer 38 such as epoxy.
Chip 40 includes surface 42 and wire bond pads 46.
And a surface 44 having Chip 40 and package 14
The electrical connection between is made by a thin wire 28 with a wire bond connection between the die bond pad 46 and the package bond pad 18. The thickness 48 of the spacer 30 is selected such that the surface 42 of the chip 40 is more than the highest point of the wire bond connection 28 from the surface 24 of the chip 20 so as to provide sufficient spacing for wire bonds. In the case of memory chips, it is common to be able to bond several pads of each chip to the pads on the package in parallel, ie, combine the same pad function of both chips at the package bond pad.
This statement, except for the chip select pad or chip enable pad, which is usually separated or adhered to its only package or substrate pad,
This applies to all chip pads of the memory chip. Although only two chips are shown in FIG. 1, additional chip levels can be added by gluing additional spacers 30 onto surface 44 of chip 40.

FIG. 1 shows a separation spacer. Another arrangement is to incorporate the function of the spacer 30 on the back of the active chip, such as the chip 40 of FIG. The isolation or spacer function can be achieved by chemical etching or mechanical sawing of the back side of the wafer 39 as shown in FIG. In either case, the back side of wafer 39 must have about 0.040 inch channels removed on both sides of wafer street 41. The channel depth is
Determined by the spacing required for wire bonding. 0.008
It has been found that a depth of inches is sufficient for a prototype. FIG. 2 shows a cross-sectional view of the active chip 43 (size ratio is not constant) including the active die surface 47, the area of silicon removal by chemical etching or mechanical sawing 45, the back surface or the mounting surface 49.

Certain types of integrated circuits (ICs) require that the backside of the chip be connected to ground or Vss. Die mounting surface 16a and package bonding pad 1
FIG. 4 shows a first alternative embodiment of the arrangement 10 including a package or substrate 14a having the same.

The spacer 50 shown in FIG. 4b includes an extended bottom or outer layer or shelf 52 having a surface 53 for attaching a wire bond, and a contact with the bottom of the top chip and relative to the wire bond loop height. And two horizontal or horizontal surfaces of the upper inner layer 54 having a spacing surface 55. In one indicated design, the bottom layer 52 generally has a thickness 56 of at least 0.002 inches, the top layer 54 is recessed from the bottom layer 52 by about 0.020 inches, and the surface of the top layer 54 55 has a height above surface 53 of about 0.006 inches. Spacer 50 may be of various materials. The spacer 50 may be made of a conductive material such as aluminum. Alternatively, the spacer 50 may be made of a non-conductive material, metallize at least a portion of the surfaces 53 and 55 and electrically interconnect the metallized portions, for example, by a metallized surface 59 joining them. You can also. The spacer 50 may be made of a silicon material and the faces 53, 55 and 59 may be coated with a wire bondable metal such as aluminum or gold.

As shown in FIG. 4c, the spacer 50 may be comprised of two separate pieces of aluminum, for example, joined by a conductive epoxy. For example,
The lower piece 66 is about 0.002 inches thick and the upper piece 68 is about 0.006 inches thick.

The advantages of silicon spacers are that they are good thermal conductors, are compatible with the thermal expansion of the die, and are easy to machine by chemical or mechanical means. Other materials, such as SiC, AlN, CuW, are examples of other materials that have high thermal conductivity and reasonable thermal compatibility with silicon.

The use of the spacer 50 will be described below. Die 20a is attached to surface 16a by conventional means. An electrical connection is made between the chip 20a and the package 14a by a thin wire 28a having a Vdd or signal wire bond connection at the die bond pad 26a and the package bond pad 18a. Next, the conductive spacer 50 is bonded onto the upper surface 24a of the die 20a with a conductive adhesive or a non-conductive adhesive. Examples of non-conductive materials include non-conductive epoxy or polyimide. These bonding chemistries often include electrically insulating and thermally conductive materials such as alumina, diamond or aluminum nitride. Examples of conductive adhesives include metal-loaded epoxy or polyimide. Next, electrical connection is made by the thin wire 28a which has been wire-bonded at the surface 53 of the spacer 50 and the package bond pad 19. Alternatively, a wire bond can be created between surface 53 and a ground pad on die 20a. Power supply (V
dd) or signal connections can be made by pads such as 18a. Next, the upper die or the second die 40 a is bonded to the surface 55 of the spacer 50. Chip 4
An electrical connection between the back surface of Oa, ie, surface 42a, and surface 55 of spacer 50 requires a conductive adhesive or bonding material. By gluing additional spacers and active chips on top of chips that have already made wire bond connections, additional chip levels can be added to the stack.

It is often necessary to connect a capacitor to the IC chip. In the conductive spacer 50, the capacitors can be mounted on a single chip or on a stack of chips. For example, in FIG. 5, capacitor 60 is a large area capacitor with power and ground connections to two large surfaces 61 and 62. As shown in FIG. 5, the connection of chip 20b to package 14b, the attachment and connection of spacer 50a to chip 20b, and the attachment and connection of chip 40b are the same as those described for the same components in FIG. . The conductive spacer 50b is bonded to the chip 40b with a conductive adhesive or a non-conductive adhesive. Wire bond connections are made from the surface 53 of the spacer 50b to the ground pad on the chip 40b. Alternatively, surface 53 can be connected directly to ground (Vss) pad 19b on package 14b. Next, the capacitor 60 is placed so that the bottom surface 61 is in electrical contact with the top surface of the spacer 50b and is effectively grounded.
Is adhered to the spacer 50b by a conductive adhesive. A power (Vdd) connection from a power pad on chip 40b or power pad 18b on package 14b to surface 62 of capacitor 60 is made by wire bonding.

FIG. 6 shows another embodiment with a capacitor mounting configuration in which a separate capacitor 70 has a conductive end 72 for connection to ground and a conductive end 74 for connection to a power supply.
And FIG. For example, a type 1206 capacitor can be used. In this embodiment, the assembly process is the same as in FIG. 5 up to the attachment and connection of the second chip 40c. Conductive spacer 80 is a variation of conductive spacer 50 described. The conductive surface 82 is a spacer 50
Corresponds to the conductive surface 53 of FIG. A layer of dielectric material 84, such as a polymer film or a thick dielectric paste, must be adhered or adhered onto surface 82. A thin metal layer or film 86 is then adhered to the top surface of the dielectric layer 84. An opening 88 is then made in the metal layer 86 and the dielectric layer 84 to expose the conductive surface 82 of the spacer 80. The capacitor 70 is bonded to the spacer 80 with a conductive material 90 such as a conductive adhesive or solder, or another conductive material. Next, the end 74 of the capacitor 70 is connected to the conductive surface 82, and the end 72 is connected to the metal layer 86. A wire bond 90 is made between conductive plane 82 and a ground pad on chip 40c, or to a ground pad on package 14c. From the metal layer 86 to the power supply pad on the chip 4c or the package 14c
Create an additional wire bond 94 to the upper power pad.

Those skilled in the art will appreciate that the materials and processes just described can be varied. For example, a metal layer or film 86 may be previously bonded to the dielectric layer 84, such as in a clad flexible polymer film.
As another example, the openings in dielectric layer 84 may be patterned before depositing and patterning metal film 86.

The scope of the invention is indicated by the appended claims rather than by the foregoing description.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a chip stack arrangement according to the present invention.

FIG. 2 is a sectional view of a chip having an integral spacer.

FIG. 3 is a plan view of a part of the back or bottom of a semiconductor wafer used to obtain the chip of FIG. 2;

FIG. 4 is a cross-sectional view of another embodiment of the present invention.

FIG. 5 is a sectional view of another embodiment of the present invention.

FIG. 6 is a sectional view of another embodiment of the present invention.

FIG. 7 is a plan view of the same embodiment as FIG.

[Explanation of symbols]

 Reference Signs List 16 die mounting surface 18 bonding pad 19 package bond pad 20 first chip 22, 24, 42, 44, 61, 62 surface 30 plate spacer 36 non-conductive adhesive layer 38 adhesive layer 90 conductive material 94 wire bond

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ronald J. Jensen United States 55437 Minnesota, Bloomington Oxborough Road 9704 (72) Inventor Charles Jay Sp. Schneider United States 55305 Minnesota, Minnesota Netonka Oakley Drive 2930

Claims (10)

[Claims] A first die fixed to the die mounting surface; a second plurality of bonding pads on the first die from a first plurality of bonding pads external to the first die. A first plurality of thin wires extending to a plurality of bonding pads; a first dimension having a planar dimension at least partially within a space bounded by the first plurality of bonding pads; A flat plate spacer means fixed to the surface of the first die by an adhesive layer; and a surface of the second die opposed to the first die, the first plurality of narrow surfaces being separated from the first die. A second die secured to the spacer means having a thickness that is greater than a highest point of the wire; and a second plurality of bonding pads on the second die and external to the second die. Fourth multiple bondin · Third chip stack arrangement comprising a plurality of thin wires extending to the pad. 2. The chip stack arrangement according to claim 1, wherein said spacer means is silicon, and said second die is fixed to said spacer means by a second adhesive layer. 3. The method of claim 1, wherein said spacer means is integral with said second die, and said spacer is formed by removing a portion of a back surface of a semiconductor wafer. Chip stack layout as described. 4. The spacer means further comprises a first outer layer and a second central layer, wherein the first and second layers have conductive surfaces and are electrically interconnected. Wherein said second die is secured to a surface facing said spacer means by a conductive adhesive material, and comprising means for electrically connecting said conductive surface of said outer layer to a first voltage. The chip stack arrangement of claim 1. 5. The chip stack arrangement according to claim 4, wherein said spacer is silicon and said conductive surface comprises a metal suitable for wire bond connection. 6. The chip stack arrangement according to claim 4, wherein said spacer is aluminum. 7. The chip stack arrangement according to claim 4, wherein said means for electrically connecting is wire bonding means. 8. A second spacer means having a first outer layer and a second central layer secured to the surface of the second die and having a conductive surface and electrically interconnected. Capacitor means having a first conductive surface fixed to the conductive surface of the central layer of the second spacer by a conductive material, and a second conductive surface; and The chip of claim 4, including means for electrically connecting a conductive surface to a first voltage reference, and means for electrically connecting the second conductive surface to a second voltage. -Stack arrangement. 9. A second spacer fixed to the surface of the second die and having a first outer layer and a second central layer having a conductive surface and being electrically interconnected. Means, a dielectric layer fixed to the conductive surface of the second central layer, a conductive layer fixed to the dielectric layer, extending in the conductive surface and in the dielectric layer, Second
An opening for exposing the electrically conductive surface of the central layer, a first conductive end fixed to the conductive surface by a conductive material, and a second conductive end fixed to the conductive layer by a conductive material. Means for electrically connecting the conductive surface of the first outer layer to a first voltage reference; and means for electrically connecting the conductive layer to a second voltage. 5. The chip stack arrangement according to claim 4, comprising: 10. The chip stack arrangement according to claim 9, wherein said dielectric layer and said conductive layer are joined before attaching to said conductive surface of said central layer.