KR20000066816A - Method for manufacturing stacked chip package - Google Patents

Abstract

PURPOSE: A method of making a stacked chip package is provided to realize the stacked chip package using a substrate of a silicon or ceramic material having identical or similar thermal expansion coefficient to a semiconductor chip, as an intermediate insertion material. CONSTITUTION: A method of making a stacked chip package comprises providing an intermediate insertion disk consisting of silicon or ceramic(91a), cutting the intermediate insertion disk into a plurality of individual insertion segments(91c), attaching at a printed circuit board a first chip having electrode pads formed around an edge(92), connecting the electrode pads to the printed circuit board via first bonding wires(93), attaching a second chip at a top of the intermediate insertion segment(95), connecting the electrode pads of the first chip to the printed circuit board via second bonding wires(96), and sealing a resultant structure using a resin(97).

Description

Method for manufacturing stacked chip package

The present invention relates to a method for manufacturing a semiconductor chip package, and more particularly, to a method for manufacturing a laminated chip package in which another semiconductor chip is laminated on a semiconductor chip via an intermediate insert made of silicon or ceramic material.

With the trend toward thinner and shorter electronic devices, high-density and high-mounted packages are becoming important factors, and in the case of computers, large amounts of random access memory (RAM) and fresh memory are increasing as memory capacity increases. Like the Flash Memory, the size of the chip grows naturally, but the package is being studied to be smaller in accordance with the above requirements.

Here, various methods that have been proposed to reduce the size of a package include, for example, a multi chip package (MCP) and a multi chip module (MCM) in which a plurality of chips or packages are mounted. In particular, there are limitations in manufacturing the semiconductor chip and the package because they are mounted in a planar arrangement method on the substrate.

In order to overcome this limitation, a package technology in which a plurality of chips or packages having the same storage capacity are stacked three-dimensionally has been proposed, which is commonly referred to as a "stacked chip package die assembly".

1 is a cross-sectional view showing a laminated chip package 50 according to the prior art. Referring to FIG. 1, a chip on stacked with an intermediate insert 37 interposed between two semiconductor chips 10 and 20 on an upper surface 32a of a printed circuit board 32. A chip on chip (COC) structure is formed. At this time, the lower semiconductor chip 20 (hereinafter, referred to as a “chip to be attached”) is a semiconductor chip in which electrode pads are formed around an edge of an active surface that is an upper surface. The intermediate insert 37 is attached to the region between the electrode pads of the chip 20. Then, a semiconductor chip 10 (hereinafter referred to as "attachment chip") having a size that penetrates the electrode pad of the adhesion chip 20 is attached to the upper surface of the intermediate insert 37.

The adhesion chip 20 and the attachment chip 10 stacked on the upper surface 32a of the printed circuit board 32 are bonded to the substrate pads of the printed circuit board 32 by bonding wires 35 and 36 (bonding wires). 31; electrically connected to the substrate pad, a resin encapsulant 38 is formed on the upper surface 32a of the printed circuit board, and a solder ball 34 used as an external connection terminal is printed. It is attached to a ball pad 33 formed on the lower surface 32b of the circuit board.

Here, the intermediate insert 37 is a thermosetting tape or epoxy adhesive having a predetermined thickness, and the bonding wire 35 drawn from the electrode pad of the adherend chip 20 is attached to the chip 10. The attachment chip 10 having a size that violates the electrode pad of the adherend chip 20 may be stacked on the adherence chip 20 while preventing damage to the bottom surface of the adherence chip 20. The thickness of the intermediate insert 37 is formed thicker than the height to the top of the bonding wire 35 that electrically connects the adherend chip 20 and the printed circuit board 32, and the lower surface of the intermediate insert 37 The area is preferably formed to have an area that can be located in an area between the electrode pads formed around the edge of the adherend chip 20.

However, the stacked chip package 50 having such a structure requires a separate process for inserting the intermediate insert 37 to attach the attachment chip 10 to the upper surface of the adherend chip 20 and an apparatus according thereto. Therefore, it can act as a factor which raises manufacturing cost.

Since the heterogeneous intermediate insert 37 is interposed between the attachment chip 10 and the adhesion chip 20, by thermal deformation due to thermal stress in the reliability test of the package after the laminated chip package 50 is manufactured. Peeling at the interface between the attachment chip 10, the intermediate insert 37, and the adhesion chip 20 may occur.

When the attachment chip 10 is laminated on the adherend chip 20, the first bonding wire 35 drawn from the electrode pad of the adherence chip 20 is formed by the lower surface of the attachment chip 10. In order not to be affected, the adjustment of the thickness of the intermediate insert 37 plays an important factor. However, since the intermediate insert 37 of thermosetting tape or epoxy material is easily deformed by heat or pressure, it is not easy to control the thickness of the intermediate insert.

Accordingly, an object of the present invention is to provide a method of manufacturing a stacked chip package using the substrate of a silicon or ceramic material having the same or similar thermal expansion coefficient as the semiconductor chip as an intermediate insert.

Another object of the present invention is to provide a method for manufacturing a stacked chip package for implementing a stacked chip package using a conventional semiconductor chip package manufacturing apparatus.

It is still another object of the present invention to provide a method of manufacturing a stacked chip package using an intermediate insert having an easy thickness control.

1 is a cross-sectional view showing a laminated chip package according to the prior art,

2 is a process diagram showing an embodiment of the manufacturing method according to the present invention of a laminated chip package including an intermediate insert of silicon material,

3 to 12 are views showing respective steps of the manufacturing method shown in FIG.

3 is a perspective view showing an intermediate insert disc of silicon material,

4 is a perspective view showing the step of attaching the intermediate insert disc to the fixing ring with ring tape,

5 is a perspective view showing the step of cutting the intermediate insert disc into individual intermediate inserts,

FIG. 6 is a perspective view illustrating a state in which a adhered chip is attached to a printed circuit board and a first wire bonded state;

7A and 7B are perspective and cross-sectional views showing the steps of attaching individual intermediate inserts to the adherent chip;

8 is a cross-sectional view showing the step of attaching an attachment chip to an individual intermediate insert;

9 is a cross-sectional view showing a second wire bonding step,

10 is a cross-sectional view showing a step of forming a resin suture;

11 is a cross-sectional view showing a step of forming a solder ball,

12 is a sectional view showing a step of separating into individual stacked chip packages;

13 is a partially cutaway perspective view illustrating a stacked chip package according to another exemplary embodiment of the present disclosure;

14 is a bottom view of the stacked chip package of FIG. 13.

Description of the main parts of the drawing

60, 160: chip 62, 72: electrode pad

64, 164: intermediate insert 66, 75, 76: adhesive layer

70, 170: chipped chip 82, 182: printed circuit board

84 solder ball 85, 86, 185, 186 bonding wire

88, 188: resin sealing portion 100, 200: laminated chip package

In order to achieve the above object, the present invention comprises the steps of (a) preparing an intermediate insert disc made of silicon or ceramic having a predetermined diameter and thickness; (b) cutting the intermediate insert disc into a plurality of individual intermediate inserts; (c) attaching an adhered chip having a plurality of electrode pads around the edge thereof to the printed circuit board; (d) connecting the electrode pad of the adhered chip and the printed circuit board with a first bonding wire; (e) attaching the intermediate insert to a region between electrode pads of the adherend chip; (d) attaching an attachment chip having an area that penetrates the electrode pad of the adherend chip and having a plurality of electrode pads formed on an upper surface thereof, on the upper portion of the intermediate insert; (e) connecting the electrode pad of the skin chip and the printed circuit board with a second bonding wire; And (f) sealing the adhesion chip, the adhesion chip, the intermediate insert, and the first and second bonding wires with a molding resin to form a resin sealing portion. 1 provides a method of manufacturing a laminated chip package, characterized in that the intermediate insert is formed to have a thickness such that the bonding wire can be positioned below the attachment chip.

The manufacturing method according to the invention may further comprise the step of attaching the intermediate insert disc to the retaining ring with ring tape before step (b).

When the height from the upper surface of the adhered chip to the top of the first bonding wire is about 150 μm, the disc of the acid insert of step (a) according to the manufacturing method according to the present invention has a thickness of 90 μm to 120 μm. It is preferable to form.

The intermediate insert disc of step (a) according to the manufacturing method of the present invention is formed with a diameter of 6 inches, 8 inches or 12 inches.

The printed circuit board of step (c) according to the manufacturing method of the present invention has a predetermined thickness, and has an upper surface on which a plurality of substrate pads are electrically connected with an attached chip and an attached chip and first and second bonding wires. And a lower surface on which a plurality of external connection terminals electrically connected to the substrate pads of the upper surface are formed.

The printed circuit board of step (c) according to the manufacturing method of the present invention has a predetermined thickness, and has an upper surface on which a plurality of substrate pads are electrically connected with an attached chip and an attached chip and first and second bonding wires. And a lower surface having a plurality of ball pads electrically connected to the substrate pads on the upper surface. After the step (f), the method may further include forming solder balls on the ball pads of the printed circuit board.

In the step (d) according to the manufacturing method of the present invention, the intermediate insert is preferably attached so as to be separated from the electrode pad of the adherend chip by 0.2 mm to 0.5 mm using a die bonding apparatus.

And, after the step (f) according to the manufacturing method of the present invention further comprises the step of separating into individual stacked chip package.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a process diagram illustrating an embodiment of a method of manufacturing a stacked chip package including an intermediate insert of silicon material in accordance with the present invention. 3 to 12 are views showing respective steps of the manufacturing method shown in FIG. In addition, the same reference numerals refer to the same components throughout the drawings.

The manufacturing process of this embodiment begins with the manufacturing step of the intermediate insert 91. First, an intermediate insert disc 61 having a predetermined diameter d and thickness t as shown in FIG. 3 is prepared (91a). As the intermediate insert disc 61, it is preferable to prepare a disc of silicon or ceramic material having the same or similar thermal expansion coefficient as that of the semiconductor chip, easy to adjust the thickness d, and be formed to have a constant thickness d. In the case of the intermediate insert disc 61 made of a silicon disc, it is a silicon disc that has not undergone a semiconductor manufacturing process. Thus, the intermediate insert disc 61 is a cylindrical ingot having a diameter t of 6 inches, 8 inches or 12 inches, cut into a cutting blade such as a diamond blade to a predetermined thickness d. Meanwhile, the intermediate insert disc 61 is formed to have a thickness t such that the first bonding wire drawn out from the electrode pad of the adherend chip can be positioned below the attachment chip. For example, when the thickness of the adherend chip is 300 μm, the intermediate insert disc 61 is 90 μm to 120 because the height from the top surface of the adherend chip to the top of the first bonding wire is about 150 μm. It is preferable to form in thickness t of micrometer.

Next, as shown in FIG. 4, the step of attaching the intermediate insert disc 61 to the fixing ring 42 with the ring tape 46 proceeds, and the intermediate insert disc 61 is attached to the ring tape 46. (91b). The reason for fixing the intermediate insert disc 61 with the ring tape 46 is that it is not easy to treat it as the intermediate insert disc 61 itself, and the intermediate process of cutting the intermediate insert disc 61 (91c) and the intermediate process subsequent to the intermediate insert disc 61 itself. To smoothly proceed to step 94 of attaching the insert to the adherent chip.

Next, as shown in FIG. 5, the cutting step of the intermediate insert disc 61 proceeds (91c). First, the lower surface of the intermediate insert disk 61 to which the ring tape 46 is attached is turned upside down to face upward, and is then introduced into the next step of cutting. Next, when the cutter 48 cuts the intermediate insert disc 61 into a desired shape, an individual intermediate insert 64 necessary for the manufacture of the laminated chip package is obtained. As the cutting machine 48, a diamond rotary blade is mainly used. That is, the cutting process of the intermediate insert disc 61 is performed using the cutting device of a normal wafer.

At this time, the intermediate insert 64 cuts the intermediate insert disc 61 to have a size enough to be attached to the area between the electrode pads of the adherend chip, and 0.2 mm to 0.5 mm from the electrode pad of the adherend chip. It is desirable to cut to a size that can be attached to a distance.

Next, as shown in FIG. 6, the process 92 of attaching the adherend chip 70 to the printed circuit board 82 and the first wire bonding process 93 proceed in this order.

First, as illustrated in FIGS. 6 and 7B, the adhered chips 70 are attached to the upper surface 82a of the printed circuit board at predetermined intervals 192. The adhered chip 70 is a semiconductor chip in which electrode pads 72 are formed around the edge of the upper surface 74, and has the same structure as a semiconductor chip manufactured by a conventional semiconductor chip manufacturing process. As a chip attaching method, a conventional method is used. For example, after applying an adhesive such as a liquid non-conductive epoxy resin to a chip bonding position of a printed circuit board 82a, pressing the adhered chip 70 and curing it This is used. Meanwhile, in order to realize thinning of the laminated chip package, the thickness of the first adhesive layer 75 after the adhesion of the adherend chip 70 is preferably adjusted to about 30 μm or less.

The printed circuit board 82, as is well known, is a substrate on which a circuit wiring pattern is printed on an insulating plate having a predetermined thickness. As shown in FIG. 7B, the substrate pads 81 of the upper surface 82a of the printed circuit board and the ball pads 83 of the lower surface 82b of the printed circuit board 82 form a predetermined pattern. Are electrically connected to each other through via holes (not shown) passing through). Not only is the printed circuit board 82 already well known, but its structure is not necessary to understand the present invention. Accordingly, the specification and drawings are not disclosed in detail.

As shown in FIG. 6, the printed circuit board 82 has a strip form of two rows so that a plurality of stacked chip packages can be manufactured at the same time. Although not illustrated, the printed circuit board 82 is arranged in a row. Or n-m matrix (n, m: natural number).

Next, after the adhesion chip 70 is attached, the substrate pad 81 of the printed circuit board and the electrode pad 72 of the adhesion chip are connected to each other by the first bonding wire 85 (93). As the first bonding wire 85, a Au wire having a diameter of 1 mil is used, and a conventional wire bonding method using capillary is used. In order to realize thinning of the stacked chip package, the height of the first bonding wire 85 must be properly adjusted. This is because the height of the first bonding wire 85 determines the thickness of the intermediate insert. The height from the upper surface of the adhered chip 70 to the uppermost end of the first bonding wire 85 may be about 100 μm to 150 μm depending on the thickness of the adhered chip 70.

Next, attaching the individual intermediate inserts 64 proceeds as shown in FIGS. 7A and 7B (94). The intermediate insert 64 attaching process proceeds in the same manner as the attaching process of the semiconductor chip using a conventional semiconductor chip attaching equipment. That is, after applying the liquid nonconductive adhesive to the area between the electrode pads 72 of the adherend chip, the intermediate insert 64 is separated from the ring tape 46 to apply the non-conductive adhesive electrode pad of the adherend chip. Pressing in the area between 72 and curing the non-conductive adhesive attaches the intermediate insert 64 to the top surface 74 of the adherend chip. At this time, the cured non-conductive adhesive forms a second adhesive layer 76, and the thickness of the second adhesive layer 76 after the adhesion of the intermediate insert 64 is adjusted to about 30 μm or less in order to realize thinning of the laminated chip package. It is desirable to. 7B is a cross-sectional view taken along a line 7b-7b in FIG. 7A. In the embodiment of the present invention, in consideration of the first bonding wire 85 connected to the electrode pad 72 of the adherend chip, it is attached to the electrode pad 72 of the adherend chip by 0.2 mm to 0.5 mm.

Next, as shown in FIG. 8, the attaching of the attachment chip 60 is performed 95. That is, after applying the liquid adhesive on the intermediate insert 64, the adhesive chip 60 is pressed to the upper surface of the intermediate insert 64, the adhesive is cured to attach the adhesive chip 60. The attachment chip 60 is a semiconductor chip having an area invading the area of the electrode pad 72 of the adherend chip. The attachment chip 60 includes a plurality of electrode pads in order to maintain good wire bonding property with the substrate pad 81 of the printed circuit board. 62 is formed around the edge of the upper surface of the attachment chip 60. At this time, the cured adhesive forms the third adhesive layer 66, and in order to realize thinning of the laminated chip package, the thickness of the third adhesive layer 66 is adjusted to about 30 μm or less after the adhesion of the attachment chip 60. desirable. As the adhesive, any conductive or nonconductive adhesive can be used.

It is preferable to adjust the thicknesses of the second and third adhesive layers 76, 66 and the intermediate insert 64 so that the first bonding wire 85 can be positioned under the attachment chip 60. For example, when the thickness of the adherend chip 70 is 300 μm, the height from the upper surface 74 of the adherend chip to the uppermost end of the first bonding wire 85 is about 150 μm. And 60 μm to 120 μm in consideration of 60 μm that is the sum of the thicknesses of the third adhesive layers 76 and 66, and the thickness of the intermediate insert may be adjusted within a range in which the first bonding wire 85 is not damaged. . For example, the intermediate insert may be formed such that the lower surface of the attachment chip contacts the first bonding wire within a range that does not exert an external force such that the first bonding wire is deformed.

Next, as shown in FIG. 9, the second wire bonding step proceeds (96). That is, the electrode pad 62 of the attachment chip and the substrate pad 81 of the printed circuit board are electrically connected to each other by the second bonding wire 86. Of course, conventional wire bonding methods are used.

10 shows a sealing step of forming a resin sealing portion 88 which is the next manufacturing step (97). The sealing process includes the upper surface 82a of the printed circuit board exposed to the outside, the attachment chip 60 formed on the upper surface 82a, the deposition chip 70, the intermediate insert 64, the first and the second. As a process necessary for protecting the bonding wires 85 and 86, as is well known, the resin encapsulation portion 88 can be formed using a transfer molding method using a molding resin. Molding resins which can preferably be used are epoxy molding compounds (EMC), for example molding takes about 90 seconds at a temperature of 160 ℃ to 175 ℃. Meanwhile, the step of washing the printed circuit board 82 may be further performed before forming the resin encapsulation unit 88. This is to improve the adhesion between the resin encapsulation unit 88 and the printed circuit board 82, and removes the organic substances on the printed circuit board 82 by using a plasma.

11 proceeds to forming the next step, the solder ball 84 (98). After flux is applied to the ball pad 83 formed on the lower surface 82b of the printed circuit board, the spherical solder balls 84 are raised and reflowed to connect the external connection terminals to the lower surface 82b of the printed circuit board. Phosphorous solder ball 84 is formed. In addition, a method of stencil printing a solder paste may be used.

For example, the solder ball 84 may use a product of Alpha Metal having a ratio of 63 (Sn) and lead (Pb) of 63 to 37. The flux may also use WS613 of Alpha Metal. If the flux remains on the printed circuit board 82 after the solder ball 84 is formed, a cleaning step may be added. The washing at this time can be done in an ultrasonic cleaner containing water or another cleaning solution for flushing the flux.

Meanwhile, in the exemplary embodiment of the present invention, the solder ball 84 is formed on the printed circuit board 82 as an external connection terminal. However, as shown in FIGS. 13 and 14, the printed circuit in the manufacturing step of the printed circuit board 182 is performed. A portion of the circuit wiring pattern formed on the lower surface 182a of the substrate may be directly formed by the external connection terminal 183.

As the solder ball 88 is formed, a final step is performed, as shown in FIG. 12, to separate each individual stacked chip package 100 (99). As described above, according to a preferred embodiment of the present invention, several individual stacked chip packages 100 are simultaneously manufactured on one printed circuit board 82. Therefore, in order to obtain the individual laminated chip package 100 after the solder ball 84 is formed, the outer edge of the resin encapsulation portion 88 of the individual laminated chip package is cut by the separating means 47.

The separating means 47 used in this cutting process includes a drill, a rotary blade, or a laser. The drill uses a router bit that rotates at a high speed of more than 25,000 rpm and a dust inhaler to remove dust generated during cutting. The rotary blade uses a diamond rotary blade used in a conventional wafer cutting process, and fixing tapes, water, and the like are further used. Yag laser is used for the laser, and dust generated by laser heat should be removed.

13 is a partially cutaway perspective view illustrating a stacked chip package according to another exemplary embodiment of the present disclosure. 14 is a bottom view of the stacked chip package of FIG. 13.

13 and 14, the stacked chip package 200 according to another exemplary embodiment may include a wiring pattern patterned on the lower surface 182b of the printed circuit board 182 as external connection terminals 183. It is a stacked chip package applied to a leadless grid array (LGA) package. In this case, the external connection terminals 183 are formed along edges of opposite sides of the lower surface 182b of the printed circuit board, and the substrate pad 181 and the lower surface 182b of the upper surface 182a of the printed circuit board are formed. The external connection terminal 183 is electrically connected by the via hole 187. In addition, the configuration of the adherent chip 170, the intermediate insert 164, the attachment chip 160 and the bonding wires 185, 186 on the upper surface 182a of the printed circuit board according to the embodiment of the present invention described above Since it has the same structure as a structure, detailed description is abbreviate | omitted.

Meanwhile, in the exemplary embodiment of the present invention, a stacked chip package having a chip-on-chip structure in which two chips are stacked on a printed circuit board through an intermediate insert made of silicon or ceramic is implemented. A stacked chip package in which more than one chip is stacked can also be implemented.

As described above, the laminated chip package manufactured by the method of the present invention has no difference in terms of its structure from the conventional laminated chip package shown in FIG. However, it can be seen that the material of the intermediate insert and the method of making the intermediate insert are clearly different, and the effect is also large.

Therefore, according to the manufacturing method of the present invention, since the laminated chip package is manufactured by using an intermediate insert that is formed to a desired thickness in advance using a silicon or ceramic substrate, the thickness of the intermediate insert can be easily adjusted.

Since the intermediate insert disc is manufactured in the same form as the semiconductor wafer and the individual intermediate inserts are supplied, the existing semiconductor equipment such as the wafer cutting device and the chip attaching device can be used as it is, thereby reducing the additional cost. to be.

In addition, since the intermediate insert is made of the same silicon material as that of the adhesion chip and the adhesion chip, peeling at the interface due to the difference in the coefficient of thermal expansion can be suppressed in the reliability test after the laminated chip package is manufactured.

Claims (9)

(a) preparing an intermediate insert disc made of silicon or ceramic having a predetermined diameter and thickness; (b) cutting the intermediate insert disc into a plurality of individual intermediate inserts; (c) attaching an adhered chip having a plurality of electrode pads around the edge thereof to the printed circuit board; (d) connecting the electrode pad of the adhered chip and the printed circuit board with a first bonding wire; (e) attaching the cut intermediate insert to a region between electrode pads of the adherend chip; (d) attaching an attachment chip having an area that penetrates the electrode pad of the adherend chip and having a plurality of electrode pads formed on an upper surface thereof, on the upper portion of the intermediate insert; (e) connecting the electrode pad of the skin chip and the printed circuit board with a second bonding wire; And (f) sealing the adherent chip, the adherend chip, the intermediate insert, the first and second bonding wires with a molding resin to form a resin encapsulation portion, and And forming the intermediate insert such that the first bonding wire drawn out from the electrode pad of the adherend chip has a thickness such that the first bonding wire can be positioned under the attachment chip. 2. The method of claim 1, further comprising attaching the intermediate insert disc to the retaining ring with ring tape before step (b). The disc of claim 1, wherein when the height from the upper surface of the adherend chip to the top of the first bonding wire is about 150 μm, the disc of the acid insert of step (a) has a thickness of 90 μm to 120 μm. Method for producing a laminated chip package, characterized in that formed. The method of claim 1, wherein the intermediate insert disc of step (a) is formed with a diameter of 6 inches, 8 inches or 12 inches. The printed circuit board of claim 1, wherein the printed circuit board of step (c) has a predetermined thickness and includes a plurality of substrate pads electrically connected to the adhesion chip and the adhesion chip and the first and second bonding wires. And a bottom surface having a top surface and a plurality of external connection terminals electrically connected to the substrate pads of the top surface. The printed circuit board of claim 1, wherein the printed circuit board of step (c) has a predetermined thickness and includes a plurality of substrate pads electrically connected to the adhesion chip and the adhesion chip and the first and second bonding wires. And a bottom surface having a top surface and a plurality of ball pads electrically connected to the substrate pads of the top surface. The method of claim 6, further comprising forming solder balls on the ball pads of the printed circuit board after the step (f). The method of claim 1, wherein in the step (d), the intermediate insert is attached 0.2 mm to 0.5 mm apart from the electrode pad of the adherend chip by using the die bonding device. The method of claim 1, further comprising the step of separating into individual stacked chip packages after step (f).