KR100520602B1 - Stacking structure of semiconductor chip - Google Patents

Abstract

The present invention relates to a stacking structure of a semiconductor chip, comprising: a substrate having a plurality of circuit patterns formed thereon so as to stack semiconductor chips of various types and sizes while minimizing the overall thickness of the stacked semiconductor chips; A first semiconductor chip bonded to a surface of the substrate and having a first planar surface and a second surface that are substantially planar, and having a plurality of input / output pads formed thereon; A first conductive wire electrically connecting the input / output pad of the first semiconductor chip and the circuit pattern of the substrate; A first adhesive applied to a second surface of the first semiconductor chip at a predetermined thickness; A second adhesive applied to a predetermined thickness on the first adhesive; A second semiconductor chip having a first planar surface and a second surface that is substantially planar, and a plurality of input / output pads are formed on the second surface, and the first surface adhered to the second adhesive; And a second conductive wire connecting the input / output pad of the second semiconductor chip and the circuit pattern of the substrate.

Description

Stacking structure of semiconductor chip

The present invention relates to a stacking structure of a semiconductor chip, and more particularly, to a stacking structure of a semiconductor chip capable of stacking semiconductor chips of various types and sizes while minimizing the overall stack thickness of the stacked semiconductor chips. .

Recently, by stacking a plurality of semiconductor chips, which are the main components of the semiconductor package, attempts to maximize the function and performance of the overall semiconductor package have been made continuously. For example, a combination of a 32MB flash memory chip and a 4MB static RAM (SRAM) chip, a combination of a logic chip and a flash memory chip, or a combination of a digital chip and an analog chip, and a combination of a DSP (Digital Signal Processor) and a flash memory chip. Increasing the multifunctionality and high performance of the semiconductor package. In addition, the semiconductor package in which the semiconductor chip is stacked as described above can satisfy a high memory density while occupying a small volume, and thus, is used in cellular phones, PDAs, camcorders, PCs, routers, and other portable products. Is in.

The stack structure and method of a general semiconductor chip having the above advantages will be described with reference to FIGS. 1A and 1B.

First, as shown in the stacking structure 11 'of FIG. 1A, a second surface is formed at the center of the upper surface of various substrates 7' (for example, a printed circuit board, a circuit film, a circuit tape, a lead frame, etc.). The first surface 1a 'of the first semiconductor chip 1' (edge pad type semiconductor chip) having a plurality of input / output pads 1c 'formed around the edge 1b' is an adhesive 4 '. It is bonded by. In addition, the first surface 2a 'of the second semiconductor chip 2' is bonded to the center of the second surface 2b 'of the first semiconductor chip 1' with an adhesive 4 '. Of course, the second semiconductor chip 2 'is also provided with a plurality of input / output pads 2c' around the second surface 2b '. That is, it is an edge pad type semiconductor chip.

The stack structure 11 ′ of the semiconductor chip as described above may easily bond the first conductive wire 5 ′ to the input / output pad 1 c ′ of the first semiconductor chip 1 ′, or to the first semiconductor chip 1 ′. The size of the second semiconductor chip 2 'is larger than the size of the first semiconductor chip 1' so that the conductive wire 5 'and the second semiconductor chip 2' do not interfere with each other and short. There is a limit that must be small. That is, since the second semiconductor chip 2 'is to be positioned only inside the input / output pad 1c' of the first semiconductor chip 1 ', there is a disadvantage in that a semiconductor chip of the same size cannot be stacked.

In addition, the stack structure 11 'of the semiconductor chip may adopt only an edge pad type semiconductor chip in which the input / output pad 1c' is formed around the second surface 1b 'as the first semiconductor chip 1'. In addition, a center pad type semiconductor chip having an input / output pad formed at the center of the second surface 1b 'cannot be adopted. Of course, the second semiconductor chip 2 'may adopt a center pad type semiconductor chip.

In the figure, the notation 6 'is a second conductive wire which interconnects the input / output pad 2c' of the second semiconductor chip 2 'and the circuit pattern (not shown) of the substrate 7'.

Meanwhile, a stacking structure 12 ′ shown in FIG. 1B has been developed to stack multiple semiconductor chips of the same size.

Referring to FIG. 1B, a first conductive wire 5 ′ bonded to an input / output pad 1 c ′ of the first semiconductor chip 1 ′ may have a first surface 2 a ′ of the second semiconductor chip 2 ′. ) A spacer having a predetermined thickness between the second surface 1b 'of the first semiconductor chip 1' and the first surface 2a 'of the second semiconductor chip 2'. 3 ') (Spacer) has a disadvantage that must be interposed more.

A semiconductor package having such a spacer is described in detail in US Patent No. 5,323,060, Japanese Patent Laid-Open No. Hei 1-99248, and Japanese Patent Laid-Open No. 5-109975.

However, this stack structure 12 'has a predetermined thickness between the second surface 1b' of the first semiconductor chip 1 'and the first surface 2a' of the second semiconductor chip 2 '. By interposing the spacer 3 ', the overall stack thickness of the semiconductor chip is very thick.

That is, the thickness of the spacer 3 'should generally be about twice as thick as the roof height LH of the first conductive wire 5'. In other words, as shown in FIG. 1B, the height H from the uppermost curved point of the first conductive wire 5 ′ to the first surface 2a ′ of the second semiconductor chip 2 ′ is the first conductive wire 5. It should be formed to the same height as the roof height LH of '). This is a standard designed in consideration of the error of the loop height formed in the first conductive wire 5 ', the thickness error of the spacer 3' and the elasticity of the spacer 3 '.

For reference, the first conductive wire 5 ′ is normally bonded to one end of the normal wire (Ball Bonding) to the input / output pad of the semiconductor chip, and the other end of the conductive wire is substrate 2 to the substrate. In the case of the form of stitch bonding, the LH should be approximately 100 µm or more, and the total thickness of the spacer 3 'should be at least 200 µm.

In addition, when the loop height error of the first conductive wire 5 'and the thickness error of the spacer 3' are large, the first conductive wire 5 'is the first of the second semiconductor chip 2'. There is a problem of interference and short with the surface 2a '.

In addition, although the stacking structure as described above can stack semiconductor chips of various sizes up and down, since the center pad type cannot be adopted as the first semiconductor chip 1 ', various kinds of semiconductor chips are stacked. There is a disadvantage that can not.

Accordingly, the present invention has been made to solve the above-described problems, to provide a stacking structure of a semiconductor chip that can stack a variety of types and sizes of semiconductor chips while minimizing the overall stack thickness of the stacked semiconductor chips have.

In order to achieve the above object, a stacking structure of a semiconductor chip according to the present invention includes: a substrate having a plurality of circuit patterns formed thereon; A first semiconductor chip bonded to a surface of the substrate and having a first planar surface and a second surface that are substantially planar, and having a plurality of input / output pads formed on the second surface; A first conductive wire electrically connecting the input / output pad of the first semiconductor chip and the circuit pattern of the substrate; A first adhesive applied to a second surface of the first semiconductor chip at a predetermined thickness; A second adhesive applied to a predetermined thickness on the first adhesive; A second semiconductor chip having a first planar surface and a second surface that is substantially planar, and a plurality of input / output pads are formed on the second surface, and the first surface adhered to the second adhesive; And a second conductive wire connecting the input / output pad of the second semiconductor chip and the circuit pattern of the substrate.

The first adhesive agent and the second adhesive agent may have a total thickness greater than that of the roof height of the first conductive wire.

One end of the first conductive wire may be ball bonded to the input / output pad of the first semiconductor chip, and the other end may be stitch bonded to the circuit pattern of the substrate.

One end of the first conductive wire may be stitch bonded to the input / output pad of the first semiconductor chip, and the other end may be ball bonded to the circuit pattern of the substrate. Here, a conductive ball may be formed in advance on the input / output pad of the first semiconductor chip stitch-bonded with the first conductive wire.

In addition, the first adhesive is electrically nonconductive.

The input / output pad of the first semiconductor chip and the conductive wire on the input / output pad may be located inside the first adhesive.

The first semiconductor chip may be a center pad type in which a plurality of input / output pads are formed in the center of the second surface.

The first semiconductor chip and the second semiconductor chip may be formed in the same size.

In addition, in order to achieve the above object, the stacking method of a semiconductor chip according to the present invention provides a substrate having a plurality of circuit patterns formed thereon, having a first plane and a second plane which are substantially planar, Providing a first semiconductor chip having a plurality of input / output pads formed thereon, and bonding a first surface of the first semiconductor chip to a surface of the substrate; Connecting the input / output pad of the first semiconductor chip and the circuit pattern of the substrate with a first conductive wire; Applying and curing the first adhesive on the second surface of the first semiconductor chip at a predetermined thickness; Applying a second adhesive agent to the first adhesive upper surface at a predetermined thickness; Providing a second semiconductor chip having a first surface and a second surface that are substantially planar, and having a plurality of input / output pads formed thereon, and bonding the second surface of the second semiconductor chip to the second adhesive. Wow; And connecting the input / output pad of the second semiconductor chip and the circuit pattern of the substrate with a second conductive wire.

Here, the first adhesive and the second adhesive is formed so that the total thickness is larger than the loop height of the first conductive wire.

According to the stacking structure of the semiconductor chip according to the present invention as described above, a first adhesive of a predetermined thickness is applied to the second surface of the first semiconductor chip and cured, and a second adhesive is applied to the upper surface of the first adhesive. Then, by stacking the second semiconductor chip, it is possible to exclude the use of the conventional thick spacers and to minimize the overall stacking thickness of the first semiconductor chip and the second semiconductor chip.

In addition, as described above, since the first conductive wire may be positioned inside the first adhesive, various types of semiconductor chip stacks are possible, and there is an advantage of preventing interference or short between the first conductive wires. .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

2A to 2C are cross-sectional views showing the stacking structures 11, 12 and 13 of the semiconductor chip according to the present invention.

First, a substantially plate-shaped substrate 6 in which a plurality of circuit patterns (not shown) are formed, for example, a printed circuit board, a circuit tape, a circuit film or a lead frame, is provided.

The first semiconductor chip 1 is bonded to the center upper surface of the substratum 6 by an adhesive 3. The first semiconductor chip 1 has an approximately planar first surface 1a and a second surface 1b, and a plurality of input / output pads 1c are formed on the second surface 1b.

As illustrated in FIGS. 2A and 2B, the first semiconductor chip 1 may be an edge pad type having a plurality of input / output pads 1c formed on an inner circumference of the second surface 1b, as shown in FIG. 2C. Likewise, the center pad type may include a plurality of input / output pads 1c formed at the center of the second surface 1b.

Subsequently, the circuit patterns of the input / output pad 1c and the substrate 6 of the first semiconductor chip 1 are electrically and mechanically connected to each other by the first conductive wire 4.

Here, one end of the first conductive wire 4 may be ball bonded first to the input / output pad 1c of the first semiconductor chip 1, and the other end may be stitch bonded to the circuit pattern of the substrate 6. (Refer to FIG. 2A) Here, according to the bonding form as described above, the loop height of the first conductive wire 4 is approximately 100 µm.

In addition, one end of the first conductive wire 4 is first ball-bonded to the circuit pattern of the substrate 6 so that the loop height on the first semiconductor chip 1 is further reduced, and the other end is first Secondary stitch bonding may be performed on the input / output pad 1c of the semiconductor chip 1 (see FIGS. 2B and 2C). In this case, conductive balls must be formed in the input / output pad 1c in advance. By the above bonding mode, the loop height of the first conductive wire 4 is approximately 50 to 70 µm.

As described above, in order to achieve good stitch bonding to the input / output pad 1c, a conductive ball should be formed in advance in the input / output pad 1c. (See FIGS. 2B and 2C.) The conductive ball is ball-bonded at one end of the conductive wire. It is formed by cutting after the cut, this bonding method will be defined as SSB (Stand Off Stitch Bonding) bonding.

Subsequently, the second surface 1b of the first semiconductor chip 1 is cured with a non-conductive first adhesive 3a applied to a predetermined thickness. The first adhesive 3a may be formed only in the inner region of the input / output pad 1c (see FIGS. 2A and 2B) or may be formed while completely covering the input / output pad 1c and the first conductive wire 4. In other words, when the first semiconductor chip 1 is a center pad type, the conductive wires on the input / output pad 1c and the second surface 1b may be completely covered with the first adhesive 3a. At this time, the first adhesive 3a is electrically non-conductive in order to prevent the plurality of first conductive wires 4 from being shorted with each other.

Application and curing thickness of the first adhesive (3a) is preferably formed to be larger than the loop height of the ball-bonded or stitch-bonded first conductive wire (4). For example, when the first conductive wires 4 are ball bonded, they have a thickness of 100 μm or more, and when stitch bonded, they have a thickness of about 50 μm to 80 μm or more.

In order to obtain sufficient curing thickness of the first adhesive 3a as described above, the application and curing of the first adhesive 3a may be repeated a number of times.

Subsequently, the second semiconductor chip 2 is bonded to the upper surface of the first adhesive 3a with the non-conductive second adhesive 3b applied thereto. That is, since the first adhesive 3a is already cured and inferior in adhesiveness, the liquid second adhesive 3b is applied to the upper surface of the first adhesive 3a, and then on the second adhesive 3b. The second semiconductor chip 2 is bonded.

As the second adhesive 3b, a conventional adhesive film or adhesive tape may be used, and the same kind as the first adhesive 3a may be used.

On the other hand, the second adhesive (3b) is to have a thickness of about 100 ~ 130㎛ along with the first adhesive (3a). That is, the thickness of the first conductive wire 4 is larger than that of the lufuite.

The second semiconductor chip 2 has an approximately planar first surface 2a and a second surface 2b, and a plurality of input / output pads 2c are formed on the second surface 2b. Here, the first surface 2a of the second semiconductor chip 2 is adhered to the upper surface of the second adhesive 3b. Of course, an edge pad type or a center pad type may be used for the second semiconductor chip 2.

In addition, the input / output pad 2c of the second semiconductor chip 2 is also electrically and mechanically connected to the circuit pattern of the substrate 6 by the second conductive wire 5. The above-mentioned stitch bonding or ball bonding may be used for the connection of the second conductive wire 5 and the second semiconductor chip 2, and the stitch bonding is preferably used to minimize the overall stacking thickness. Of course, at this time, after the conductive ball is fused in advance to the input / output pad 2c of the second semiconductor chip 2, the second conductive wire 5 is stitch bonded.

Here, the first conductive wire and the second conductive wire are common gold wires (Au Wire) or aluminum wires (Al Wire).

FIG. 3 is a cross-sectional view showing an example of the semiconductor package 21 using the stacking structure 11 of the semiconductor chip shown in FIG. 2A.

As shown, a substrate 6 having a plurality of circuit patterns 7 is provided, and the first semiconductor chip 1 is bonded to the upper surface of the substrate 6 with an adhesive 3. In addition, a first adhesive 3a and a second adhesive 3b are coated on the upper surface of the first semiconductor chip 1 at a predetermined thickness, and a second semiconductor chip 2 is disposed on the upper surface of the second adhesive 3b. Is bonded.

In addition, the input / output pad 1c of the first semiconductor chip 1 is electrically and mechanically connected to any one of the circuit patterns 7 of the substrate 6 by the first conductive wire 4. The input / output pad 2c of the second semiconductor chip 2 is electrically and mechanically connected to the other circuit pattern 7 of the substrate 6 by the second conductive wire 5.

In addition, the first semiconductor chip 1, the first and second adhesives 3a and 3b, the second semiconductor chip 2, and the first and second conductive wires 4 and 5 on the substrate 6 may be epoxy. It is encapsulated with encapsulant such as molding compound compound (Epoxy Molding Compound) to protect from external electrical, mechanical and chemical environment. Here, the region encapsulated with the encapsulant is referred to as encapsulation 8.

Meanwhile, as shown in the drawing, when the substrate 6 is a printed circuit board, a circuit tape, or a circuit film, a plurality of conductive balls 9 are fused to the lower surface of the substrate 6, so that the motherboard It can be easily mounted on the Mother Board. Of course, the conductive balls 9 are fused to the circuit pattern 7 formed on the substrate 6.

4A to 4F are explanatory views sequentially showing a stacking method of a semiconductor chip according to the present invention. Here, a method for implementing the stacking structure of FIG. 2A will be described as an example.

First, a substantially plate-shaped substrate 6 in which a plurality of circuit patterns (not shown) are formed, for example, a printed circuit board, a circuit tape, a circuit film or a lead frame, is provided. A first semiconductor chip 1 having a first surface and a second surface 1b and having a plurality of input / output pads 1c formed thereon is provided on the second surface 1b. Here, the first semiconductor chip 1 is an edge pad type.

Subsequently, the first surface 1a of the first semiconductor chip 1 is adhered to the center upper surface of the substrate 6 by an adhesive 3 (see FIG. 4A).

Subsequently, the circuit patterns of the input / output pad 1c and the substrate 6 of the first semiconductor chip 1 are electrically and mechanically connected to each other by the first conductive wire 4 (see FIG. 4B).

That is, one end of the first conductive wire 4 is first ball bonded to the input / output pad 1c of the first semiconductor chip 1, and the other end is secondly bonded to the circuit pattern of the substrate 6. .

Subsequently, the first adhesive 3a is applied to the second surface 1b of the first semiconductor chip 1 with a predetermined thickness and then left for a predetermined time. That is, the first adhesive 3a is to be hardened. In order to speed up the curing time, the coated first adhesive 3a may be provided with a high temperature. In addition, the first adhesive 3a may be applied to a predetermined region of the input / output pad 1c and the first conductive wire 4. That is, the first conductive wire 4 may be applied so as to be completely covered by the first adhesive 3a. At this time, the first non-conductive first adhesive 3a is used to prevent electrical short between the first conductive wires 4.

Application and curing of the first adhesive 3a as described above may be performed several times.

Subsequently, a second adhesive 3b is applied to the upper surface of the first adhesive 3a. (See FIG. 4D.) That is, since the first adhesive 3a is already cured and inferior in adhesiveness, the first adhesive 3a is applied. The liquid second adhesive 3b is applied to the upper surface of the adhesive 3a.

As the second adhesive 3b, a non-liquid conventional adhesive film or adhesive tape may be used, and the same kind as the first adhesive 3a may be used.

However, the total thickness of the first adhesive 3a and the second adhesive 3b must be greater than the loop height of the first conductive wire 3a.

Subsequently, a second semiconductor chip 2 having a substantially planar first surface 2a and a second surface 2b and having a plurality of input / output pads 2c formed thereon is provided. The first surface 2a of the second semiconductor chip 2 is bonded to the second adhesive 3b (see Fig. 4E).

Finally, the circuit patterns of the input / output pads 2c and the substrate 4 of the second semiconductor chip 2 are electrically and mechanically connected to each other using the second conductive wires 5.

The above-mentioned stitch bonding or ball bonding may be used for the connection of the second conductive wire 5 and the second semiconductor chip 2, and a stitch bonding method is preferably used to minimize the overall stacking thickness. Of course, the conductive ball must be formed in advance on the input and output pad for the stitch bonding.

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

Accordingly, according to the stacking structure of the semiconductor chip according to the present invention, a first adhesive having a predetermined thickness is applied to the second surface of the first semiconductor chip to be cured, and a second adhesive is applied to the upper surface of the first adhesive. By stacking the two semiconductor chips, it is possible to eliminate the use of the conventional thick spacers and to minimize the stacking thicknesses of the first semiconductor chip and the second semiconductor chip. Conductive balls are formed in the input / output pads in advance, and one end of the conductive wires are stitch-bonded to the conductive balls, thereby minimizing the wire loop height and thus minimizing the overall stacking thickness of the first semiconductor chip and the second semiconductor chip. It has an effect.

In addition, as described above, since the first conductive wire for electrically connecting the first semiconductor chip to the substrate may be located inside the first adhesive, semiconductor chip stacks of various types and sizes may be possible.

1A and 1B are cross-sectional views showing a stacking structure of a semiconductor chip according to the prior art.

2A to 2C are cross-sectional views showing a stacking structure of a semiconductor chip according to the present invention.

3 is a cross-sectional view showing an example of a semiconductor package using a stacking structure of a semiconductor chip according to the present invention.

4A to 4F are explanatory views sequentially showing a stacking method of a semiconductor chip according to the present invention.

-Description of the main symbols in the drawings-

11,12; Stacking Structure of Semiconductor Chip According to the Present Invention

One; A first semiconductor chip 1c; I / O pad

2; Second semiconductor chip 2c; I / O pad

3; Adhesives 3a, 3b; 1st adhesive, 2nd adhesive

4; First conductive wire 5; 2nd conductive wire

6; Suprate 7; Circuit pattern

8; Encapsulation 9; Conductive ball

10; Circuit pattern 11; Semiconductor Package

Claims (6)

A substrate having a plurality of circuit patterns formed thereon; It is adhered to the surface of the substrate, and has a first plane and a second surface that is substantially planar, a plurality of input and output pads are formed on the second surface, the conductive ball is fused to the plurality of input and output pads 1 semiconductor chip; A plurality of first conductive wires, one end of which is ball-bonded to the circuit pattern of the substrate and the other end of which is stitch-bonded to a conductive ball fused to an input / output pad of the first semiconductor chip; A non-conductive first adhesive coated on a second surface of the first semiconductor chip at a predetermined thickness; A second non-conductive adhesive applied to a predetermined thickness on the first adhesive; It has a first surface and a second surface that is substantially planar, a plurality of input and output pads are formed on the second surface, the conductive ball is fused to the input and output pads, the first surface is bonded to the second adhesive A second semiconductor chip; And, One end is bonded to the circuit pattern of the substrate, the other end is a semiconductor chip stacking structure comprising a plurality of second conductive wire stitch-bonded to the conductive ball fused to the input and output pads of the second semiconductor chip. The stacking structure of a semiconductor chip according to claim 1, wherein the first adhesive agent and the second adhesive agent have a total thickness greater than a loop height of the first conductive wire. (delete) The stacking structure of a semiconductor chip according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are formed in the same size. (delete) (delete)