JPH11340410A - Mounting structure for integrated circuit - Google Patents
Mounting structure for integrated circuitInfo
- Publication number
- JPH11340410A JPH11340410A JP10141480A JP14148098A JPH11340410A JP H11340410 A JPH11340410 A JP H11340410A JP 10141480 A JP10141480 A JP 10141480A JP 14148098 A JP14148098 A JP 14148098A JP H11340410 A JPH11340410 A JP H11340410A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- substrate
- mounting structure
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、主回路基板に複数
の集積回路を装着する集積回路の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit mounting structure in which a plurality of integrated circuits are mounted on a main circuit board.
【０００２】[0002]
【従来の技術】従来の複数の集積回路（ＩＣ）を駆動す
るシステムでは、それぞれの集積回路のチップが別個に
それぞれパッケージされ、これらのパッケージが回路基
板に接続実装されていた。このように、複数の集積回路
が個別にパッケージされると、集積回路の実装密度を高
めることが難しく、製品の小型化が制約を受けると共
に、各集積回路間の配線長が長くなり、ノイズの誘導な
どで集積回路の動作特性が低下することがある。2. Description of the Related Art In a conventional system for driving a plurality of integrated circuits (ICs), chips of each integrated circuit are individually packaged, and these packages are connected and mounted on a circuit board. As described above, when a plurality of integrated circuits are individually packaged, it is difficult to increase the packaging density of the integrated circuits, which limits the miniaturization of the product, increases the wiring length between the integrated circuits, and reduces noise. The operating characteristics of the integrated circuit may be degraded by induction or the like.
【０００３】[0003]
【発明が解決しようとする課題】この問題を解決するた
めに、複数の集積回路を、単一のパッケージ内に実装す
るマルチチップパッケージが利用されるようになってお
り、この場合の実装法としては、ワイヤボンディング
法、フリップチップ法などが採用されている。この際、
複数の集積回路に対して、ランドグリッドアレイ・チッ
プサイズパケッジ（ＬＧＡ−ＣＳＰ）、ボードグリッド
アレイ（ＢＧＡ）を使用したスタック方式をとると、多
ピンの集積回路では全体が大型化され、リードフレーム
を間に挟む方式をとると、チップ端子出力の反転のため
に、別途チップを使用することが必要になり構造が複雑
になる。また、フリップチップ接続と、ワイヤボンド接
続とを使用すると、一方に特製のチップを使用しないと
全体が大型化してしまい、さらに、集積回路の組合せサ
イズにも制限が生じる。In order to solve this problem, a multi-chip package in which a plurality of integrated circuits are mounted in a single package has been used. As a mounting method in this case, Employs a wire bonding method, a flip chip method, or the like. On this occasion,
When a stack system using a land grid array / chip size package (LGA-CSP) and a board grid array (BGA) is adopted for a plurality of integrated circuits, the whole of a multi-pin integrated circuit becomes large and leads If the frame is interposed, a separate chip must be used for inverting the output of the chip terminal, which complicates the structure. In addition, when flip-chip connection and wire bond connection are used, if one does not use a specially-made chip, the whole becomes large, and the combination size of the integrated circuit is limited.
【０００４】本発明は、前述したような集積回路の実装
の現状に鑑みてなされたものであり、その目的は、複数
の集積回路を、全体を小型化した単一のパッケージとし
て、高密度化された状態で、基板に対して簡単に実装可
能な集積回路の実装構造を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned current situation of mounting an integrated circuit, and an object of the present invention is to reduce the number of integrated circuits into a single package having a small size as a whole. An object of the present invention is to provide a mounting structure of an integrated circuit that can be easily mounted on a substrate in a state of being performed.
【０００５】[0005]
【課題を解決するための手段】前記目的を達成するため
に、本発明は、第１の集積回路が実装された主回路基板
に対して、第２の集積回路が実装されたフレキシブルフ
ィルム基板が、前記第１の集積回路を覆って装着され、
前記フレキシブルフィルム基板の配設の端部が、前記主
回路基板に接続され、さらに、前記主回路基板を介し
て、前記第１の集積回路に接続されていることを特徴と
するものである。In order to achieve the above object, the present invention provides a flexible printed circuit board on which a second integrated circuit is mounted on a main circuit board on which a first integrated circuit is mounted. Mounted over the first integrated circuit,
An end of the arrangement of the flexible film substrate is connected to the main circuit board, and further connected to the first integrated circuit via the main circuit board.
【０００６】[0006]
【発明の実施の形態】本発明の一実施の形態を、図１な
いし図３を参照して説明する。図１は本実施の形態の構
成を示す断面説明図、図２は本実施の形態の構成を示す
斜視図、図３は図１の半導体接続部の構成を示す説明図
である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional explanatory view showing the configuration of the present embodiment, FIG. 2 is a perspective view showing the configuration of the present embodiment, and FIG. 3 is an explanatory view showing the configuration of the semiconductor connection portion of FIG.
【０００７】本実施の形態は、２個の半導体集積回路
が、一つのパッケージに組み込まれてマザーボードに実
装される場合であり、図１及び図２に示すように、ガラ
スエポキシ製のプリント配線基板からなるマザーボード
１に対して、半導体集積回路５が、マザーボード１の互
いに対向する縁辺部に、それぞれ複数個所設けられた半
導体接続部８の部分で接続実装されている。この場合、
半導体接続部８では、図３（ａ）に示すように、半田や
金材質が突起状に形成された半導体集積回路５のバンプ
１０と、マザーボード１の電極１１とが、半田１２で互
いに電気的に接続されている。この半導体接続部８の接
続は、同図（ｂ）に示すようにすることもでき、この場
合には、半導体集積回路５のバンプ１０と、マザーボー
ド１の電極１１とは、異方導電性接着フィルム（ＡＣ
Ｆ）１３の熱圧着によって、互いに電気的に接続されて
いる。In this embodiment, two semiconductor integrated circuits are incorporated in one package and mounted on a motherboard. As shown in FIGS. 1 and 2, a printed wiring board made of glass epoxy is used. The semiconductor integrated circuit 5 is connected and mounted on the opposing edge portions of the motherboard 1 at a plurality of semiconductor connection portions 8 provided at a plurality of locations. in this case,
As shown in FIG. 3A, the bumps 10 of the semiconductor integrated circuit 5 in which the solder or the gold material is formed in a protruding shape and the electrodes 11 of the motherboard 1 are electrically connected to each other by the solder 12 at the semiconductor connection portion 8. It is connected to the. The connection of the semiconductor connection portion 8 can be made as shown in FIG. 2B. In this case, the bumps 10 of the semiconductor integrated circuit 5 and the electrodes 11 of the motherboard 1 are connected by anisotropic conductive bonding. Film (AC
F) 13 are electrically connected to each other by thermocompression bonding.
【０００８】この半導体集積回路５の表面には、ポリイ
ミドフィルム（ＰｏｌｙｍｉｄｅＦｉｌｍ）基板２が配
設されており、このポリイミドフィルム基板２には、半
導体集積回路３が、圧着接続されて実装されている。こ
のように半導体集積回路３が実装されたポリイミドフィ
ルム基板２は、半導体集積回路５の表面に沿って延長配
設されており、延長方向の両端部は、半導体集積回路５
の端縁部からマザーボード１方向に屈折延長され、ポリ
イミドフィルム基板２の両端部に設けられたフィルム接
続部６は、半田或いは異方導電性接着フィルム（ＡＣ
Ｆ）の熱圧着によって、マザーボード１と接続されてい
る。A polyimide film (Polyimide Film) substrate 2 is disposed on the surface of the semiconductor integrated circuit 5, and a semiconductor integrated circuit 3 is mounted on the polyimide film substrate 2 by crimping connection. The polyimide film substrate 2 on which the semiconductor integrated circuit 3 is mounted is extended along the surface of the semiconductor integrated circuit 5, and both ends in the extending direction are connected to the semiconductor integrated circuit 5.
The film connecting portions 6 extending from the edge portion of the polyimide film substrate 1 toward the motherboard 1 and provided at both ends of the polyimide film substrate 2 are soldered or anisotropically conductive adhesive film (AC).
F) is connected to the motherboard 1 by thermocompression bonding.
【０００９】この接続により、本実施の形態では、フィ
ルム接続部６でのマザーボード１との接続によって、ポ
リイミドフィルム基板２は、マザーボード１を介して半
導体集積回路５と接続され、また、マザーボード１の電
極部７と接続されている。With this connection, in the present embodiment, the polyimide film substrate 2 is connected to the semiconductor integrated circuit 5 via the motherboard 1 by the connection with the motherboard 1 at the film connection section 6, and It is connected to the electrode unit 7.
【００１０】このようにして、本実施の形態によると、
半導体集積回路３と半導体集積回路５とは、マザーボー
ド１に積層配置され、一つのパッケージに組み込まれた
マルチチップ半導体集積回路となり、ポリイミドフィル
ム基板２では、小パターン化が可能で、フィルム接続部
６も小さくなり、マザーボード１に対する占有面積が削
減され、高密度化され且つ小型化された実装が可能にな
る。さらに、ポリイミドフィルム基板２の取出方向は自
由に設定できて、設計の自由度が増大し、半導体集積回
路３と半導体集積回路５との接続は同一方向で行なわれ
るので、別途チップ端子の反転のための集積回路を設け
ることが不要となり、構成も簡単となり製造コストの低
減も可能になる。As described above, according to the present embodiment,
The semiconductor integrated circuit 3 and the semiconductor integrated circuit 5 are stacked on the motherboard 1 to form a multi-chip semiconductor integrated circuit incorporated in one package. The polyimide film substrate 2 can be formed into a small pattern. And the area occupied by the motherboard 1 is reduced, and high-density and miniaturized mounting becomes possible. Further, the direction in which the polyimide film substrate 2 is taken out can be freely set, so that the degree of freedom in design is increased. Since the connection between the semiconductor integrated circuit 3 and the semiconductor integrated circuit 5 is performed in the same direction, the chip terminals are separately inverted. Therefore, it is not necessary to provide an integrated circuit, the configuration is simplified, and the manufacturing cost can be reduced.
【００１１】[0011]
【発明の効果】本発明によると、第１の半導体集積回路
が実装された主回路基板に対して、第１の半導体集積回
路を覆って、第２の半導体集積回路が実装されたフレキ
シブルフィルム基板が装着され、フレキシブルフィルム
基板の配設の長手方向の両端部が、主回路基板に接続さ
れ、さらに、主回路基板を介して、第１の半導体集積回
路に接続されているので、チップ端子反転用の集積回路
を別途使用することなく、第１の半導体集積回路及び第
２の半導体集積回路を、小さい占有面積で積層配置され
小型化されたマルチチップ構成の単一パッケージとし
て、主回路基板に対して簡単に実装することが可能にな
る。According to the present invention, a flexible film substrate on which a second semiconductor integrated circuit is mounted, covering a first semiconductor integrated circuit, with respect to a main circuit substrate on which a first semiconductor integrated circuit is mounted. Are mounted, and both ends of the flexible film substrate in the longitudinal direction are connected to the main circuit board, and further connected to the first semiconductor integrated circuit via the main circuit board. The first semiconductor integrated circuit and the second semiconductor integrated circuit are stacked and arranged in a small occupied area as a single package of a miniaturized multi-chip configuration without separately using an integrated circuit for the main circuit board. It can be easily implemented.
【図１】本発明の一実施の形態の構成を示す断面説明図
である。FIG. 1 is an explanatory sectional view showing a configuration of an embodiment of the present invention.
【図２】同実施の形態の構成を示す斜視図である。FIG. 2 is a perspective view showing a configuration of the embodiment.
【図３】図１の半導体接続部の構成を示す説明図であ
る。FIG. 3 is an explanatory diagram illustrating a configuration of a semiconductor connection unit in FIG. 1;
１…マザーボード、２…ポリイミドフィルム基板、３、
５…半導体集積回路、６…フィルム接続部、７…電極
部、８…半導体接続部、１０…バンプ、１１…電極、１
２…半田、１３…異方導電性接着フィルム。1 ... motherboard, 2 ... polyimide film substrate, 3,
5 ... Semiconductor integrated circuit, 6 ... Film connection part, 7 ... Electrode part, 8 ... Semiconductor connection part, 10 ... Bump, 11 ... Electrode, 1
2 ... solder, 13 ... anisotropic conductive adhesive film.
Claims (1)
に対して、第２の集積回路が実装されたフレキシブルフ
ィルム基板が、前記第１の集積回路を覆って装着され、
前記フレキシブルフィルム基板の配設の端部が、前記主
回路基板に接続され、さらに、前記主回路基板を介し
て、前記第１の集積回路に接続されていることを特徴と
する半導体集積回路の実装構造。1. A flexible film substrate on which a second integrated circuit is mounted is mounted on the main circuit substrate on which the first integrated circuit is mounted, covering the first integrated circuit.
An end of the arrangement of the flexible film substrate is connected to the main circuit board, and further connected to the first integrated circuit via the main circuit board. Mounting structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10141480A JPH11340410A (en) | 1998-05-22 | 1998-05-22 | Mounting structure for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10141480A JPH11340410A (en) | 1998-05-22 | 1998-05-22 | Mounting structure for integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11340410A true JPH11340410A (en) | 1999-12-10 |
Family
ID=15292885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10141480A Pending JPH11340410A (en) | 1998-05-22 | 1998-05-22 | Mounting structure for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11340410A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100381838B1 (en) * | 2000-09-07 | 2003-05-01 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| KR100668848B1 (en) | 2005-06-27 | 2007-01-16 | 주식회사 하이닉스반도체 | Chip stack package |
-
1998
- 1998-05-22 JP JP10141480A patent/JPH11340410A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100381838B1 (en) * | 2000-09-07 | 2003-05-01 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| KR100668848B1 (en) | 2005-06-27 | 2007-01-16 | 주식회사 하이닉스반도체 | Chip stack package |
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