JP2001223326A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2001223326A
JP2001223326A JP2000031545A JP2000031545A JP2001223326A JP 2001223326 A JP2001223326 A JP 2001223326A JP 2000031545 A JP2000031545 A JP 2000031545A JP 2000031545 A JP2000031545 A JP 2000031545A JP 2001223326 A JP2001223326 A JP 2001223326A
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JP
Japan
Prior art keywords
chip
flip
wire
semiconductor
semiconductor device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000031545A
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Japanese (ja)
Inventor
Toru Maeda
前田  徹
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
日立北海セミコンダクタ株式会社
株式会社日立製作所
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Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd, 日立北海セミコンダクタ株式会社, 株式会社日立製作所 filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP2000031545A priority Critical patent/JP2001223326A/en
Publication of JP2001223326A publication Critical patent/JP2001223326A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73207Bump and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To realize high density mounting by preventing a wire short circuit and reducing in size and thickness in a small-sized semiconductor device of a chip laminated type. SOLUTION: The semiconductor device comprises a tape board 3 for supporting a first chip 1 of a lowermost stage by flip-chip connecting, a wiring film 4 for supporting a second chip 2 laminated and disposed on the first chip by flip-chip connecting, a wire 9 for connecting a connecting electrode 4b of the film 4 to a connecting electrode 3b of the board 3, a plurality of solder bumps 11 disposed on a rear surface 3d of the board 3, and a sealing part 10 for resin-sealing two semiconductor chips, the wire 9 and the like. In this case, the laminated and disposed first and second chips 1, 2 are face down mounted. The flip-chip connecting and the wire bonding are combined to reduce a wire density in the part 10 to prevent a wire short circuit.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体装置に関し、特にチップ積層形の半導体装置の高密度実装化に適用して有効な技術に関する。 The present invention relates to relates to a semiconductor device, a technique which is effectively applied particularly to a high-density mounting of the semiconductor device chip laminate type.

【0002】 [0002]

【従来の技術】以下に説明する技術は、本発明を研究、 BACKGROUND OF THE INVENTION techniques described below, research the present invention,
完成するに際し、本発明者によって検討されたものであり、その概要は次のとおりである。 Upon the completion, it has been examined by the inventors, the summary is as follows.

【0003】近年、小形化された半導体パッケージの一例として、CSP(Chip Size Package またはChip Sca Recently, as an example of the miniaturized semiconductor packages, CSP (Chip Size Package or Chip Sca
le Package) と呼ばれる半導体チップとほぼ同等もしくは半導体チップより若干大きい程度の小形半導体パッケージが知られている。 le Package) and slightly larger extent of small semiconductor package than approximately equal to or a semiconductor chip and a semiconductor chip called is known.

【0004】また、複数の半導体チップが積層配置されたチップ積層形の半導体装置(スタックドパッケージともいう)においても小形化が要求されており、CSP構造でのスタックドパッケージの開発が進められている。 Further, a plurality of semiconductor chips are miniaturized is also required in the semiconductor device of the stacked chips multilayered (also referred to as a stacked package), being developed stacked package in CSP structure there.

【0005】なお、半導体チップを2段に積層させたスタックドパッケージについては、例えば、特開平11− [0005] Note that the stacked package in which a laminate of the semiconductor chip to the two stages, for example, JP-A-11-
204720号公報にその構造と製造方法が記載されている。 Its structure and manufacturing method 204720 JP is described.

【0006】 [0006]

【発明が解決しようとする課題】ところが、前記した特開平11−204720号公報に記載されたスタックドパッケージでは、これをCSPに適用した場合、パッケージの外観サイズも小さいため、半導体チップの外側周囲のワイヤリング領域が非常に狭い。 However [0006] In the stacked package described in JP-A 11-204720 discloses that described above, when this is applied to CSP, for smaller appearance size of the package, the outer periphery of the semiconductor chip wiring area is very narrow.

【0007】したがって、このCSPでワイヤボンディングを2段に亘って行うと、ワイヤの密度が非常に高くなり、その結果、モールド時のワイヤ流れによって隣接するワイヤ同士のワイヤショートが発生することが問題となる。 Accordingly, if performed over two stages wire bonding in this CSP, the density of the wire is very high, as a result, the wire shorting between wires adjacent the wire sweep during molding occurs a problem to become.

【0008】さらに、最上段(2段目)の半導体チップがフェイスアップ実装であり、最上段の半導体チップに対してもワイヤボンディングを行うため、最上段の半導体チップの上方にワイヤのモールド領域を確保しなければならない。 Furthermore, the semiconductor chip of the uppermost (second stage) is face-up mounting, in order to perform wire bonding with respect to the uppermost semiconductor chip, the mold area of ​​the wire above the top of the semiconductor chip It must be secured.

【0009】したがって、この構造のCSPでは、パッケージの薄形化を図れないことが問題となる。 Accordingly, the CSP of the structure, that can not be achieved and slim package becomes a problem.

【0010】本発明の目的は、ワイヤショートを防止するとともに、小形化・薄形化を図って高密度実装を実現するチップ積層形の半導体装置を提供することにある。 An object of the present invention is to prevent wire short, it is to provide a semiconductor device chip multilayered to realize high-density mounting aim miniaturization and thinning.

【0011】本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

【0012】 [0012]

【課題を解決するための手段】本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 Among the inventions disclosed in the present application Means for Solving the Problems] To briefly explain the summary of typical,
以下のとおりである。 It is as follows.

【0013】すなわち、本発明の半導体装置は、複数の半導体チップが積層されて組み込まれたものであり、最下段に配置される半導体チップを突起電極を介してフリップチップ接続によって支持する共通配線基板と、前記最下段の半導体チップのフリップチップ接続が行われる主面と反対側の面に配置され、前記最下段の半導体チップと積層配置される上段の半導体チップを上段の突起電極を介してフリップチップ接続によって支持する上段配線基板と、前記上段の突起電極に配線を介して接続される前記上段配線基板の接続電極と前記共通配線基板の接続電極とを接続するボンディング用のワイヤと、前記共通配線基板のチップ支持面と反対側の面に配置される複数の外部端子とを有し、積層配置された複数の前記半導体チップがそれぞ [0013] That is, the semiconductor device of the present invention has a plurality of semiconductor chips are incorporated are stacked, the common wiring board for supporting the flip-chip connection via the semiconductor chip protruding electrodes are arranged in the bottom When the disposed surface opposite to the main surface of the flip chip connection of the lowermost semiconductor chip is carried out, flip the upper semiconductor chip are stacked with the bottom of the semiconductor chip through the upper protrusion electrodes and upper wiring substrate for supporting the chip connection, and wire bonding for connecting the connection electrodes of the common wiring board and the connection electrode of the upper wiring board which is connected via a wire to the top of the bump electrode, the common and a plurality of external terminals arranged on a surface opposite to the chip supporting surface of the wiring substrate, a plurality of the semiconductor chips stacked arrangement it フェイスダウン実装されるとともに、前記上段の半導体チップの表面電極と前記共通配線基板の前記接続電極とがフリップチップ接続およびワイヤボンディングによって接続され、前記最下段の半導体チップが前記共通配線基板にフリップチップ接続されているものである。 Together are face-down mounted, the upper and the semiconductor chip surface electrode of said connecting electrodes of said common wiring board are connected by flip-chip connection and wire bonding, the lowermost semiconductor chip flip-chip to the common wiring board are those connected.

【0014】本発明によれば、最下段の半導体チップがフリップチップ接続のみによって接続されるため、複数の半導体チップと最下段の共通配線基板との接続をフリップチップ接続とワイヤボンディングとに分けることができる。 According to the present invention, since the lowermost semiconductor chip are connected only by the flip-chip bonding, to divide the connection between the plurality of semiconductor chips and the bottom of the common wiring board and the flip chip bonding and wire bonding can.

【0015】その結果、封止部内のワイヤの密度を低減することができ、これにより、ワイヤショートを防止することができる。 [0015] As a result, it is possible to reduce the density of the wire in the sealing portion, which makes it possible to prevent the wire short.

【0016】 [0016]

【発明の実施の形態】以下、本発明の実施の形態を図面に基づいて詳細に説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be described in detail with reference to embodiments of the present invention with reference to the drawings. なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。 In all the drawings for describing the embodiments, members having the same function are denoted by the same reference numerals, and description thereof is not repeated.

【0017】図1は本発明の実施の形態の半導体装置の構造の一例を示す断面図、図2は図1に示す半導体装置の共通配線基板と上段配線基板における配線および接続電極の配置状態の一例を示す拡大部分平面図、図3は図1に示す半導体装置の製造方法における共通配線基板へのアンダーフィル材形成状態の一例を示す断面図、図4 [0017] Figure 1 is a sectional view showing an example of a structure of a semiconductor device of the embodiment of the present invention, FIG 2 is a layout of the wiring and the connection electrode of the common wiring board and the upper wiring board of the semiconductor device shown in FIG. 1 Figure enlarged partial plan of an example, FIG. 3 is a sectional view showing an example of the underfill material forming state of the common wiring board in the manufacturing method of the semiconductor device shown in FIG. 1, FIG. 4
は図1に示す半導体装置の製造方法における共通配線基板への1stチップ取り付けと上段配線基板の取り付け状態の一例を示す断面図、図5は図1に示す半導体装置の製造方法における上段配線基板への2ndチップ取り付け状態の一例を示す断面図、図6は図1に示す半導体装置の製造方法におけるワイヤボンディングの接続状態の一例を示す断面図、図7は図1に示す半導体装置の製造方法におけるモールドの状態の一例を示す断面図、図8は図1に示す半導体装置の製造方法における半田バンプ取り付け状態の一例を示す断面図である。 Sectional view showing an example of 1st mounting state of chip mounting and upper wiring board to the common wiring board in the manufacturing method of the semiconductor device shown in FIG. 1, FIG. 5 to the upper wiring board in the manufacturing method of the semiconductor device shown in FIG. 1 the 2nd chip sectional view showing an example of the mounting state, FIG. 6 is a sectional view showing an example of a connection state of the wire bonding in the method of manufacturing a semiconductor device shown in FIG. 1, in the manufacturing method of FIG. 7 is a semiconductor device shown in FIG. 1 sectional view showing an example of a mold in the state, and FIG. 8 is a sectional view showing an example of the solder bump mounting state in the method of manufacturing the semiconductor device shown in FIG.

【0018】図1に示す本実施の形態の半導体装置は、 The semiconductor device of the present embodiment shown in FIG. 1,
複数の半導体チップを積層配置させたチップ積層形のものであり、それぞれの前記半導体チップがフェイスダウン実装でフリップチップ接続されるとともに、複数の前記半導体チップとインタポーザとなる共通配線基板との電気的接続に、フリップチップ接続とワイヤボンディングとを組み合わせて用いたものである。 It is of a plurality of chips stacked multi where the semiconductor chips are stacked arrangement, with each of the semiconductor chip is flip-chip connected in a face-down mounting, electrical of the common wiring board comprising a plurality of said semiconductor chip and the interposer the connection is obtained by using a combination of the flip chip bonding and wire bonding.

【0019】さらに、前記半導体装置は、その複数の外部端子が、前記共通配線基板のチップ支持面3cと反対側の面(以降、裏面3dという)に配置されたエリアアレイ形のものである。 Furthermore, the semiconductor device, the plurality of external terminals, the common line opposite surface and the chip supporting surface 3c of the substrate (hereinafter, referred to as the back surface 3d) is of the arranged area array shape on.

【0020】なお、本実施の形態では、前記半導体チップを2段に積層させ、かつ前記半導体装置が小形の半導体パッケージであるCSP12の場合について説明する。 [0020] In the present embodiment, the semiconductor chip is stacked in two stages, and the semiconductor device will be described for the case of CSP12 is a small-sized semiconductor package.

【0021】したがって、CSP12は、スタック形C [0021] Thus, CSP12 is, stack-shaped C
SPとも呼ばれ、例えば、携帯用電子機器などの小形民生機器に組み込まれるものであるが、2つの半導体チップを有した小形の半導体パッケージであるため、MCM Since also called SP, for example, but is incorporated into Tamio Ogata devices such as portable electronic devices, a small-sized semiconductor package having two semiconductor chips, MCM
(Multi-Chip-Module)やシステムLSI(Large Scale (Multi-Chip-Module) and system LSI (Large Scale
Integration)として利用することも可能である。 It is also possible to use as Integration).

【0022】本実施の形態の図1に示すCSP12の構成について説明すると、最下段に配置される半導体チップである1stチップ1をAuバンプ6(突起電極)を介してフリップチップ接続によって支持するテープ基板3(共通配線基板)と、1stチップ1のフリップチップ接続が行われる主面1aと反対側の面である裏面1c [0022] description will be given of a configuration of CSP12 shown in Figure 1 of this embodiment, the tape be supported by flip-chip connection via the the 1st chip 1 is a semiconductor chip disposed on the bottom Au bumps 6 (projecting electrode) the substrate 3 (the common wiring board), the back surface 1c is a surface opposite to the main surface 1a of the flip chip connection 1st chip 1 is carried out
に配置され、かつ1stチップ1の上に積層配置される2ndチップ2(上段の半導体チップ)を上段Auバンプ7(上段の突起電極)を介してフリップチップ接続によって支持する配線フィルム4(上段配線基板)と、上段Auバンプ7に配線4aを介して接続される配線フィルム4のボンディングパッドである接続電極4bとテープ基板3のボンディングパッドである接続電極3bとを接続するボンディング用のワイヤ9と、テープ基板3の裏面3dに配置される複数の外部端子である半田バンプ11と、テープ基板3と1stチップ1との間隙および配線フィルム4と2ndチップ2との間隙を埋めるアンダーフィル材5と、2つの半導体チップとワイヤ9などを樹脂封止して形成された封止部10とからなり、積層配置された1st Disposed, and 2nd chip 2 is stacked on the 1st chip 1 (upper semiconductor chip) via the upper Au bump 7 (the upper protruding electrode) is supported by flip chip interconnections film 4 (the upper wiring a substrate), a wire 9 for bonding for connecting the connection electrodes 3b is a bonding pad of the upper Au connected to bumps 7 is a bonding pad of the wiring film 4 which is connected via a wire 4a electrode 4b and the tape substrate 3 , a solder bump 11 is a plurality of external terminals arranged on the back surface 3d of the tape substrate 3, the underfill material 5 to fill the gap between the gap and the wiring film 4 and 2nd chip 2 of the tape substrate 3 and the 1st chip 1 made and two semiconductor chips and the wire 9 from the sealing portion 10 for formed resin encapsulation, laminated placed 1st ップ1と2ndチップ2とがそれぞれフェイスダウン実装でフリップチップ接続されるとともに、2ndチップ2のパッド2b(表面電極)とテープ基板3の接続電極3bとがフリップチップ接続およびワイヤボンディングによって接続されるものである。 Together with-up 1 and 2nd chip 2 is flip-chip connected by face-down mounting each, 2nd chip 2 pad 2b (surface electrode) and the connection electrode 3b of the tape substrate 3 are connected by flip-chip connection and wire bonding is shall.

【0023】これにより、本実施の形態のCSP12 [0023] As a result, CSP12 of the present embodiment
は、チップ積層形であるとともに、フリップチップ接続とワイヤボンディングとを組み合わせたことにより、封止部10におけるワイヤ密度を少なくしてモールド時のワイヤ流れなどによるワイヤショートを防止するものである。 , Along with a chip stacked-type, by the combination of the flip chip bonding and wire bonding, in which by reducing the wire density in the sealing portion 10 to prevent the wire shorting due wire sweep during molding.

【0024】さらに、フリップチップ接続とワイヤボンディングとを組み合わせたことにより、テープ基板3における接続電極3bの数を減らしてチップ積層形のCS Furthermore, by the combination of the flip chip bonding and wire bonding, CS of chip multilayered reduce the number of connection electrodes 3b in the tape substrate 3
P12の水平方向の面積を小さくし、これにより、パッケージの小形化を図るとともに、最上段の半導体チップである2ndチップ2をフェイスダウン実装したことにより、パッケージの薄形化を図るものである。 The horizontal area of ​​the P12 is reduced, thereby, while achieving miniaturization of the package, by the 2nd chip 2 is a top of the semiconductor chip mounted face down, but to achieve thinning of a package.

【0025】ここで、CSP12では、1stチップ1 [0025] Here, in the CSP12, 1st chip 1
は、テープ基板3に対してその配線3aにフリップチップ接続のみによって接続され、また、2ndチップ2 It is connected to the wiring 3a to the tape substrate 3 by only flip-chip connection, also, 2nd chip 2
は、1stチップ1の上段側である裏面1cに取り付けられた配線フィルム4の配線4aにフリップチップ接続によって接続され、この配線4aに接続された配線フィルム4の接続電極4bと共通配線基板(インタポーザ) Are connected by flip-chip connected to the wiring 4a of the 1st chip 1 of the wiring film 4 is attached to the rear surface 1c is a top side, the connecting electrode 4b and the common wiring board (interposer wiring connected film 4 in the wiring 4a )
であるテープ基板3の接続電極3bとがワイヤボンディングによるワイヤ9によって接続されている。 The connection electrode 3b of the tape substrate 3 is is connected by a wire 9 by wire bonding.

【0026】すなわち、1stチップ1はテープ基板3 [0026] In other words, 1st chip 1 tape substrate 3
に対してフリップチップ接続のみによって接続され、2 They are connected only by the flip-chip connected to the two
ndチップ2はテープ基板3に対してフリップチップ接続とワイヤボンディングによって接続されている。 nd chip 2 are connected by flip chip bonding and wire bonding the tape substrate 3.

【0027】したがって、1stチップ1は、そのパッド1bがAuバンプ6によってテープ基板3の配線3a [0027] Thus, 1st chip 1, the wiring 3a of the tape substrate 3 that pad 1b is the Au bumps 6
に対してフリップチップ接続され、一方、2ndチップ2は、そのパッド2bが上段Auバンプ7によって配線フィルム4の配線4aに対してフリップチップ接続されている。 Respect is flip-chip connected, whereas, 2nd chip 2 is flip-chip connected to the wiring 4a of the wiring film 4 that pad 2b is the upper Au bump 7.

【0028】なお、テープ基板3は、例えば、ポリイミドテープなどによって形成され、そこには、図2に示すように、銅、金または銀などの金属からなる配線3a、 It should be noted, the tape substrate 3 is, for example, be formed by a polyimide tape, there is, as shown in FIG. 2, wire 3a made of metal such as copper, gold or silver,
ボンディングパッドである接続電極3bおよび半田バンプ搭載用のバンプランド3eなどが形成され、このバンプランド3eは、テープ基板3のくり抜きによりその裏面3d側に露出しており、そこに図1に示す外部端子である複数の半田バンプ11が取り付けられている。 And connection electrodes 3b and the solder bump for mounting the bump lands 3e is a bonding pad is formed, the bump lands 3e is exposed on the back surface 3d side by hollowing of the tape substrate 3, outside shown there in Fig 1 a plurality of solder bumps 11 are terminals are attached.

【0029】また、配線フィルム4は、その裏面4d [0029] The wiring film 4, the rear surface 4d
が、1stチップ1の裏面1c側すなわち上段側に熱可塑性の接着材8または耐熱性の高い両面テープなどによって貼り付けられており、テープ基板3と同様に、例えば、ポリイミドテープなどによって形成され、その表面には、銅、金または銀などの金属からなる配線4aやボンディングパッドである接続電極4bが形成されている。 There is affixed to the back surface 1c side i.e. the upper side of the 1st chip 1, such as by a thermoplastic adhesive 8 or a highly heat-resistant double-sided tape, as the tape substrate 3, for example, be formed by a polyimide tape, its surface, copper, connecting electrodes 4b are wiring 4a and the bonding pads made of a metal such as gold or silver is formed.

【0030】また、アンダーフィル材5の代わりとして、絶縁性のペースト材を用いてもよいが、アンダーフィル材5としてACF(Anisotropic Conductive Film, Further, as an alternative to the underfill material 5, it may be used an insulating paste material, as an underfill material 5 ACF (Anisotropic Conductive Film,
異方性導電性フィルム)を用いることが好ましい。 It is preferable to use an anisotropic conductive film).

【0031】すなわち、ACFを用いて1stチップ1 [0031] In other words, 1st chip 1 by using the ACF
および2ndチップ2をACF実装してもよく、この場合には、Auバンプ6および上段Auバンプ7の接続部は導通が図れるとともに、その周囲には、絶縁部材を埋め込むことができる。 And 2nd chip 2 may be ACF mounting, in this case, connecting portions of the Au bumps 6 and the upper Au bumps 7 with continuity can be achieved, in its surroundings, it is possible to embed an insulating member.

【0032】また、テープ基板3のチップ支持面側には、モールド樹脂、例えば、熱硬化性のエポキシ樹脂などを用いたモールドによる封止部10が形成され、これにより、1stチップ1、2ndチップ2、配線フィルム4およびワイヤ9が封止されている。 Further, the chip supporting surface side of the tape substrate 3, the mold resin, for example, the sealing portion 10 by molding using a like thermosetting epoxy resin is formed, thereby, 1st chip 1,2nd chip 2, the wiring film 4 and wire 9 are sealed.

【0033】なお、ボンディング用のワイヤ9は、例えば、金線などである。 It should be noted, the wire 9 for bonding, for example, gold wires or the like.

【0034】また、CSP12に搭載される半導体チップの機能としては、例えば、1stチップ1がASIC Further, as a function of the semiconductor chip mounted on CSP 12, for example, 1st chip 1 ASIC
(Application Specific Integrated Circuit)、2nd (Application Specific Integrated Circuit), 2nd
チップ2がDRAM(Dynamic Random Access Memory) Chip 2 is DRAM (Dynamic Random Access Memory)
などのメモリであり、異なった機能の半導体チップを有したマルチチップパッケージとしてもよい。 A memory, such as may be a multi-chip package having a semiconductor chip of different functions.

【0035】これは、1stチップ1は、2ndチップ2よりも大きいことにより、多ピン対応とすることができるためであり、上段の半導体チップをメモリ用として組み込むことが好適である。 [0035] This, 1st chip 1, by greater than 2nd chip 2 is because the may be a multi-pin compatible, it is preferable to incorporate upper semiconductor chip as a memory.

【0036】ただし、複数の半導体チップを全てメモリとしてもよく、または、マイコンとフラッシュメモリなどとの組み合わせとしてもよい。 [0036] However, all of the plurality of semiconductor chips may be a memory, or may be a combination of a microcomputer and a flash memory.

【0037】次に、本実施の形態の半導体装置であるC Next, a semiconductor device of the present embodiment C
SP12の製造方法を説明する。 SP12 for explaining a method for manufacturing a.

【0038】まず、図3に示すように、テープ基板3を準備し、これのチップ支持面3cの1stチップ実装領域にアンダーフィル材5を塗布または貼り付ける。 [0038] First, as shown in FIG. 3, to prepare a tape substrate 3, coating or paste underfill material 5 to the 1st chip mounting area of ​​this chip supporting surface 3c.

【0039】本実施の形態では、アンダーフィル材5としてACFを用いる場合を説明するが、アンダーフィル材5の代わりとして絶縁性のペースト材などを塗布してもよい。 [0039] In this embodiment, will be described a case of using the ACF as an underfill material 5 may be coated with an insulating property of the paste material as a replacement of the underfill material 5.

【0040】続いて、図4に示すように、1stチップ1をテープ基板3のチップ支持面3cにフェイスダウン実装する。 [0040] Subsequently, as shown in FIG. 4, face-down mounting the 1st chip 1 on the chip supporting surface 3c of the tape substrate 3.

【0041】すなわち、テープ基板3のチップ支持面3 [0041] That is, the chip supporting surface 3 of the tape substrate 3
cと1stチップ1の主面1aとを対向させてアンダーフィル材5であるACF上に1stチップ1を載置し、 Are opposed to the principal surface 1a of the c and 1st chip 1 1st chip 1 is placed on an under-fill material 5 ACF and,
熱圧着によって1stチップ1をテープ基板3上に固定する(マウントする)。 The 1st chip 1 is fixed on the tape substrate 3 by thermocompression bonding (mounting).

【0042】これにより、テープ基板3のチップ支持面3cにAuバンプ6を介して1stチップ1がフリップチップ接続される。 [0042] Thus, 1st chip 1 is flip-chip connected through the Au bumps 6 on the chip supporting surface 3c of the tape substrate 3.

【0043】すなわち、1stチップ1の各パッド1b [0043] In other words, 1st each pad 1b of the chip 1
と、これに対応するテープ基板3の配線3aとがAuバンプ6を介して接続される。 When a wiring 3a of the tape substrate 3 corresponding thereto are connected via Au bumps 6.

【0044】なお、1stチップ1の裏面1cの配線フィルム4は、予め、ウェハ段階で熱可塑性の接着材8などを用いて貼り付けられたものであり、したがって、ダイシングして1stチップ1を取得した際には、既にその裏面1cに、接着材8を介して配線フィルム4が貼り付けられている。 [0044] The wiring film 4 on the back surface 1c of the 1st chip 1 in advance, which was attached by using an adhesive 8 of the thermoplastic at the wafer stage, therefore, obtains the 1st chip 1 by dicing when the is already on the back surface 1c, it is attached wiring film 4 via the adhesive 8.

【0045】その後、図5に示すように、1stチップ1の裏面1c側である1stチップ1の上段側の配線フィルム4のチップ支持面4cの2ndチップ実装領域にアンダーフィル材5であるACFを配置する。 [0045] Thereafter, as shown in FIG. 5, the 2nd is underfill material 5 to the chip mounting area ACF chip supporting surface 4c of the upper side of the wiring film 4 of 1st chip 1 is a rear 1c side of the 1st chip 1 Deploy.

【0046】続いて、1stチップ1の上段側において、2ndチップ2を配線フィルム4のチップ支持面4 [0046] Subsequently, the upper side of the 1st chip 1, the 2nd chip 2 wire film 4 chip supporting surface 4
cにフェイスダウン実装する。 Face-down implementation to c.

【0047】すなわち、配線フィルム4のチップ支持面4cと、2ndチップ2の主面2aとを対向させてアンダーフィル材5であるACF上に2ndチップ2を載置し、熱圧着によって2ndチップ2を配線フィルム4上に固定する(マウントする)。 [0047] That is, the chip supporting surface 4c of the wiring film 4, is opposed to the principal surface 2a of the 2nd chip 2 2nd chip 2 is placed on an under-fill material 5 ACF and, 2nd chip 2 by thermal compression the fixed onto the wiring film 4 (mount).

【0048】これにより、配線フィルム4のチップ支持面4cに上段Auバンプ7を介して2ndチップ2がフリップチップ接続され、その結果、1stチップ1上に2ndチップ2が積層配置される。 [0048] Accordingly, 2nd 2 on the chip supporting surface 4c of the wiring film 4 through the upper Au bumps 7 are flip-chip connected, as a result, 2nd chip 2 is stacked on the 1st chip 1.

【0049】つまり、2ndチップ2の各パッド2b [0049] In other words, each pad 2b of the 2nd chip 2
と、これに対応する配線フィルム4の配線4aとが上段Auバンプ7を介して接続される。 If, and the wiring 4a of the wiring film 4 corresponding thereto are connected via the upper Au bump 7.

【0050】なお、2ndチップ2の固定の際に用いるアンダーフィル材5として、ACFではなく、例えば、 [0050] Incidentally, as an underfill material 5 to be used in the fixed 2nd chip 2, rather than ACF, for example,
導電性接着剤などを用いてもよい。 Conductive adhesive or the like may be used.

【0051】すなわち、ACF同様、前記導電性接着剤を用いた場合でも、2ndチップ2の固定の際にスクラブなどを行わなくて済むため、1stチップ1への衝撃を和らげることができる。 [0051] That is, even when the ACF Similarly, using the conductive adhesive, since it is not necessary to perform such scrubbing during the stationary 2nd chip 2, can cushion the 1st chip 1.

【0052】その後、図6に示すように、配線フィルム4のボンディングパッドである接続電極4bとテープ基板3のボンディングパッドである接続電極3bとを金線のワイヤ9を用いてワイヤボンディングする。 [0052] Thereafter, as shown in FIG. 6, a connection electrode 4b is a bonding pad of the wiring film 4 and the connection electrode 3b is a bonding pad of the tape substrate 3 wire bonding using a gold wire 9.

【0053】これにより、2ndチップ2とインタポーザであるテープ基板3とがフリップチップ接続とワイヤボンディングによって電気的に接続される。 [0053] Thus, the tape substrate 3 is a 2nd chip 2 and the interposer is electrically connected by flip chip bonding and wire bonding.

【0054】その後、図7に示すように、トランスファーモールドによってテープ基板3のチップ支持面3c側を樹脂封止し、チップ支持面3c側に封止部10を形成する。 [0054] Thereafter, as shown in FIG. 7, the chip supporting surface 3c side of the tape substrate 3 sealed with resin by transfer molding, to form a sealing portion 10 on the chip supporting surface 3c side.

【0055】続いて、図8に示すように、CSP12の表裏を反転させ、テープ基板3の裏面3d側を上方に向け、この裏面3d側に露出した複数のバンプランド3e [0055] Subsequently, as shown in FIG. 8, reverses the front and back of the CSP 12, toward the rear surface 3d side of the tape substrate 3 above, a plurality of bump lands 3e exposed in the back surface 3d side
に半田バンプ11を取り付ける。 Attaching a solder bump 11.

【0056】なお、半田バンプ11の取り付け(搭載) [0056] In addition, the mounting of the solder bump 11 (mounted)
は、例えば、転写法などによって行う。 It is carried out, for example, by a transfer method.

【0057】これにより、図1に示す本実施の形態のC [0057] Thus, C of the embodiment shown in FIG. 1
SP12の完成となる。 The completion of the SP12.

【0058】なお、CSP12では、チップセレクト用として、2ndチップ2のみを接続する場合があり、その際には、例えば、1stチップ1の対応するパッド1 [0058] In the CSP 12, as a chip select, it may be connected only 2nd chip 2, At this time, for example, corresponding pad 1 of 1st chip 1
bにはAuバンプ6を接続しないものとする。 The b shall not connect the Au bumps 6.

【0059】すなわち、Auバンプ6は必ずしも全てのパッド1bに接続させて配置するものとは限らない。 [0059] That is, Au bumps 6 are not necessarily intended to arrange to connect necessarily all pads 1b.

【0060】本実施の形態の半導体装置(CSP12) [0060] The semiconductor device of this embodiment (CSP 12)
によれば、以下のような作用効果が得られる。 According to obtained the following working effects.

【0061】すなわち、積層配置された複数の半導体チップがそれぞれフェイスダウン実装され、これにより、 [0061] That is, a plurality of semiconductor chips are stacked is mounted face-down, respectively, thereby,
1stチップ1(最下段の半導体チップ)がフリップチップ接続のみによって接続されるため、前記複数の半導体チップとインタポーザである最下段のテープ基板3 1st chip 1 for (lowermost semiconductor chip) are connected only by the flip-chip connection, the bottom of the tape substrate 3 that is a plurality of semiconductor chips and the interposer
(共通配線基板)との接続をフリップチップ接続とワイヤボンディングとに分けることができる。 It can be divided connection (common wiring board) in flip-chip bonding and wire bonding.

【0062】その結果、封止部10内のワイヤ9の密度を低減することができ、これにより、モールド時のワイヤ流れによるワイヤショートを防止することができる。 [0062] As a result, it is possible to reduce the density of the wire 9 of the sealing portion 10, which makes it possible to prevent the wire short by wire sweep during molding.

【0063】つまり、フリップチップ接続とワイヤボンディングとを組み合わせたことにより、ワイヤボンディングだけを用いた従来のチップ積層形の半導体装置と比較すると、封止部10内のワイヤ9の密度を大幅に低減することができ、その結果、本実施の形態のチップ積層形のCSP12においてワイヤショートの発生を防ぐことができる。 [0063] That is, by the combination of the flip chip bonding and wire bonding is different from the semiconductor device of the conventional chip multilayered using only wire bonding, significantly reduces the density of the wire 9 of the sealing portion 10 it can be, as a result, it is possible to prevent the occurrence of wire short in CSP12 chip laminate type according to the present embodiment.

【0064】さらに、フリップチップ接続だけを用いた従来のチップ積層形の半導体装置と比較すると、本実施の形態のチップ積層形のCSP12は、外部端子である半田バンプ11の配置がエリアアレイ形であり、したがって、高密度実装に適しているのに対し、前記フリップチップ接続だけを用いた従来のチップ積層形の半導体装置は、外部端子となるアウタリードが封止部10から突出する構造となるため、半導体装置の実装面積が増えて、その結果、高密度実装には適していない。 [0064] Further, different from the semiconductor device of the conventional chip multilayered using only flip-chip bonding, CSP 12 of the chip laminate type in the present embodiment, the arrangement is an area array shape of the solder bump 11 which is an external terminal There, therefore, contrast is suitable for high-density mounting, the flip-chip bonding only the semiconductor device of the conventional chip multilayered using, because the outer lead serving as an external terminal is a structure that protrudes from the sealing portion 10 , increasing the mounting area of ​​the semiconductor device, as a result, not suitable for high-density mounting.

【0065】これにより、フリップチップ接続とワイヤボンディングとを組み合わせた本実施の形態のチップ積層形のCSP12の方が高密度実装に適している。 [0065] Thus, towards the CSP12 chip laminate type in the present embodiment that combines the flip chip bonding and wire bonding are suitable for high-density mounting.

【0066】また、複数の半導体チップとインタポーザであるテープ基板3との接続をフリップチップ接続とワイヤボンディングとに分けることにより、テープ基板3 [0066] Further, by separating the connection between the tape substrate 3 is a plurality of semiconductor chips and the interposer to the flip chip bonding and wire bonding, tape substrate 3
におけるワイヤボンディング用のボンディングパッドである接続電極3bの設置領域も少なくすることができ、 Installation region of the connection electrode 3b is a bonding pad for wire bonding in can also be reduced,
これにより、本実施の形態のチップ積層形の半導体装置をCSP12として実現できる。 Thus, it is possible to realize a semiconductor device of a chip Laminated of this embodiment as CSP 12.

【0067】したがって、チップ積層形の半導体装置の小形化を実現できる。 [0067] Accordingly, it is possible to realize a miniaturization of the semiconductor device chip laminate type.

【0068】さらに、積層配置された複数の半導体チップがフェイスダウン実装され、したがって、2ndチップ2(最上段の半導体チップ)もフリップチップ接続となるため、この2ndチップ2上にはワイヤ9のための封止部10の領域を確保する必要性が無くなる。 [0068] Further, a plurality of semiconductor chips are stacked is mounted face down, therefore, 2nd chip 2 (the uppermost semiconductor chip) is also for the flip-chip connection, for wire 9 on the 2nd chip 2 the need to ensure an area of ​​the sealing portion 10 of is eliminated.

【0069】その結果、2ndチップ2の裏面2cの上方の封止部10を非常に薄く形成することができ、これにより、チップ積層形のCSP12の薄形化をさらに図ることができる。 [0069] As a result, it is possible to very thin upper sealing portion 10 of the back surface 2c of the 2nd chip 2, which makes it possible to further reduce the thinned in CSP12 chip laminate type.

【0070】すなわち、最上段の半導体チップにワイヤボンディングを行うタイプの従来のチップ積層形の半導体装置と比較しても本実施の形態のCSP12は薄形化を図ることができる。 [0070] That is, CSP 12 in the form of even the present embodiment as compared with the semiconductor device of the conventional chip multilayered type of wire bonding at the top of the semiconductor chip can be made thinned.

【0071】したがって、本実施の形態のチップ積層形のCSP12は、その小形化および薄形化を図ることができるため、このCSP12の高密度実装を実現できる。 [0071] Therefore, CSP 12 chips Laminated of this embodiment, it is possible to achieve the miniaturization and thinning can realize high-density mounting of the CSP 12.

【0072】また、積層配置した2ndチップ2をフリップチップ接続とワイヤボンディングによる接続でインタポーザであるテープ基板3(共通配線基板)に接続するため、新たな設備投資を必要とせず、既存設備の活用でチップ積層形の小形の半導体装置(CSP12)を製造でき、したがって、この半導体装置のコストアップを抑えることができる。 [0072] In order to connect the 2nd chip 2 is stacked on the tape substrate 3 is interposer in connection by flip chip bonding and wire bonding (common wiring board), without requiring a new equipment investment, use of existing facilities in can manufacture a semiconductor device of a small chip Laminated (CSP 12), thus, it is possible to suppress the cost of the semiconductor device.

【0073】以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 [0073] While there has been concretely described based on the embodiments made the invention invented by the present inventors, the present invention is not intended to be limited to the embodiments of the invention, without departing from the spirit scope in it is needless to say that various changes and modifications can be made.

【0074】例えば、前記実施の形態では、半導体装置の製造方法において、予め裏面1cに配線フィルム4が貼り付けられた1stチップ1を準備し、その後、1s [0074] For example, in the above embodiment, in the method for manufacturing a semiconductor device, prepares the 1st chip 1 on which the wiring film 4 is stuck in advance backside 1c, then, 1s
tチップ1に2ndチップ2を積層する場合を説明したが、配線フィルム4への2ndチップ2のフリップチップ接続を前記半導体装置の製造方法とは異なる別工程で行い、1stチップ1の裏面1c(上段)への2ndチップ2の積層を配線フィルム4ごと行ってもよい。 t has been described a case of stacking the 2nd 2 on the chip 1, carried out in different separate step from the manufacturing method of the semiconductor device of the flip chip connection 2nd chip 2 on the wiring film 4, the 1st chip 1 rear surface 1c ( a stack of 2nd chip 2 to top) may be carried out every line film 4.

【0075】また、前記実施の形態では、チップ積層数が2段の場合を説明したが、前記チップ積層数は、2段以上であれば何段であってもよい。 [0075] Further, in the embodiment, the number of chips stacked is described the case of two-stage, the number of chips stacked, may be a number of stages as long as two or more stages.

【0076】また、前記実施の形態では、共通配線基板および配線フィルム4がポリイミドテープなどの基板からなる場合を説明したが、両基板は、ポリイミドテープの基板に限定されずに、例えば、ガラス入りのエポキシ樹脂などからなる樹脂基板やセラミック基板などであってもよい。 [0076] Further, in the embodiment, the common wiring board and the wiring film 4 has been described to be comprised of a substrate such as a polyimide tape, the substrates include, but are not limited to a substrate of polyimide tape, for example, glass-filled it may be a resin substrate or a ceramic substrate made of epoxy resin.

【0077】さらに、前記実施の形態では、封止部10 [0077] Further, in the above embodiment, the sealing portion 10
がトランスファーモールドによって形成される場合を説明したが、封止部10は、ポッティングによって形成してもよい。 Although There has been described the case where it is formed by transfer molding, the sealing portion 10 may be formed by potting.

【0078】また、前記実施の形態では、半導体装置がCSP12の場合について説明したが、前記半導体装置は、チップ積層形で、かつ外部端子がエリアアレイ配置であり、さらに、それぞれの半導体チップがフェイスダウン実装でフリップチップ接続されるとともに、フリップチップ接続とワイヤボンディングとを組み合わせた接続のものであれば、CSP12以外の例えば、LGA [0078] In the above embodiment, the semiconductor device has been described in CSP 12, the semiconductor device is a chip stacked-type, and an external terminal area array arrangement, further, each of the semiconductor chips face while being flip-chip connected by down-mounted, as long as the connection of a combination of a flip-chip connection and wire bonding, for example, other than the CSP 12, LGA
(Land Grid Array)などであってもよい。 (Land Grid Array) or the like may be used.

【0079】 [0079]

【発明の効果】本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、 Among the inventions disclosed in the present application, according to the present invention will be briefly described effects obtained by typical,
以下のとおりである。 It is as follows.

【0080】(1). [0080] (1). 積層配置された複数の半導体チップがそれぞれフェイスダウン実装され、これにより、最下段の半導体チップがフリップチップ接続のみによって接続されるため、複数の半導体チップと最下段の共通配線基板との接続をフリップチップ接続とワイヤボンディングとに分けることができる。 A plurality of semiconductor chips are stacked is mounted face-down, respectively, Accordingly, since the lowermost semiconductor chip are connected only by the flip-chip bonding, flip the connection between the plurality of semiconductor chips and the bottom of the common wiring board it can be divided into the chip connected to the wire bonding. その結果、封止部内のワイヤの密度を低減することができ、これにより、モールド時のワイヤ流れによるワイヤショートを防止することができる。 As a result, it is possible to reduce the density of the wire in the sealing portion, which makes it possible to prevent the wire short by wire sweep during molding.

【0081】(2). [0081] (2). 複数の半導体チップと最下段の共通配線基板との接続をフリップチップ接続とワイヤボンディングとに分けることにより、共通配線基板におけるワイヤボンディング用の接続電極の設置領域も少なくすることができ、これにより、チップ積層形の半導体装置をCSP対応とすることができる。 By separating the connection between the plurality of semiconductor chips and the bottom of the common wiring board and the flip chip bonding and wire bonding, the installation area of ​​the connection electrode for wire bonding at the common wiring board can also be reduced, thereby, the semiconductor device of chip multilayered can be CSP corresponding. したがって、チップ積層形の半導体装置の小形化を実現できる。 Therefore, it is possible to realize the miniaturization of the semiconductor device chip laminate type.

【0082】(3). [0082] (3). 積層配置された複数の半導体チップがフェイスダウン実装され、したがって、最上段の半導体チップもフリップチップ接続となるため、この半導体チップ上にはワイヤのための封止部の領域を確保する必要性が無くなる。 A plurality of semiconductor chips are stacked is mounted face down, therefore, since the uppermost semiconductor chip is also a flip-chip connection, the need to ensure an area of ​​the sealing portion for wire on the semiconductor chip no. その結果、チップ積層形の半導体装置の薄形化を図ることができる。 As a result, it is possible to thinning of the semiconductor device chip laminate type.

【0083】(4). [0083] (4). 前記(2),(3)により、チップ積層形の半導体装置の小形化および薄形化を図ることができるため、この半導体装置の高密度実装を実現できる。 Wherein (2) and (3), it is possible to achieve downsizing and thinning of semiconductor device chips stacked-type, can realize high-density mounting of the semiconductor device.

【0084】(5). [0084] (5). 積層配置した半導体チップをフリップチップ接続とワイヤボンディングによる接続で共通配線基板に接続するため、新たな設備投資を必要とせず、既存設備の活用でチップ積層形の小形の半導体装置を製造でき、したがって、この半導体装置のコストアップを抑えることができる。 To connect to a common wiring substrate stacked with the semiconductor chip connection by flip chip bonding and wire bonding, without the need for new capital investment, it can produce a semiconductor device of a small chip Laminated with use of existing facilities, thus , it is possible to suppress the cost of the semiconductor device.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施の形態の半導体装置の構造の一例を示す断面図である。 Is a sectional view showing an example of a structure of a semiconductor device of the embodiment of the present invention; FIG.

【図2】図1に示す半導体装置の共通配線基板と上段配線基板における配線および接続電極の配置状態の一例を示す拡大部分平面図である。 2 is an enlarged partial plan view showing an example of arrangement of the wiring and the connection electrode of the common wiring board and the upper wiring board of the semiconductor device shown in FIG.

【図3】図1に示す半導体装置の製造方法における共通配線基板へのアンダーフィル材形成状態の一例を示す断面図である。 It is a cross-sectional view showing an example of the under-fill material forming state of the common wiring board in the manufacturing method of the semiconductor device shown in FIG. 3 FIG.

【図4】図1に示す半導体装置の製造方法における共通配線基板への1stチップ取り付けと上段配線基板の取り付け状態の一例を示す断面図である。 It is a sectional view showing an example of 1st mounting state of chip mounting and upper wiring board to the common wiring board in the manufacturing method of the semiconductor device shown in FIG. 1; FIG.

【図5】図1に示す半導体装置の製造方法における上段配線基板への2ndチップ取り付け状態の一例を示す断面図である。 5 is a cross-sectional view showing an example of a 2nd chip mounted state of the upper wiring board in the manufacturing method of the semiconductor device shown in FIG.

【図6】図1に示す半導体装置の製造方法におけるワイヤボンディングの接続状態の一例を示す断面図である。 It is a cross-sectional view showing an example of a connection state of the wire bonding in the method of manufacturing a semiconductor device shown in FIG. 6 FIG.

【図7】図1に示す半導体装置の製造方法におけるモールドの状態の一例を示す断面図である。 7 is a sectional view showing an example of a state of the mold in the manufacturing method of the semiconductor device shown in FIG.

【図8】図1に示す半導体装置の製造方法における半田バンプ(外部端子)取り付け状態の一例を示す断面図である。 8 is a sectional view showing an example of the solder bumps (external terminals) mounted state in the manufacturing method of the semiconductor device shown in FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 1stチップ(最下段の半導体チップ) 1a 主面 1b パッド(表面電極) 1c 裏面(反対側の面) 2 2ndチップ(上段の半導体チップ) 2a 主面 2b パッド(表面電極) 2c 裏面 3 テープ基板(共通配線基板) 3a 配線 3b 接続電極 3c チップ支持面 3d 裏面(反対側の面) 3e バンプランド 4 配線フィルム(上段配線基板) 4a 配線 4b 接続電極 4c チップ支持面 4d 裏面 5 アンダーフィル材 6 Auバンプ(突起電極) 7 上段Auバンプ(上段の突起電極) 8 接着材 9 ワイヤ 10 封止部 11 半田バンプ(外部端子) 12 CSP(半導体装置) 1 1st chip (lowermost semiconductor chip) 1a principal surface 1b pad (surface electrode) 1c back surface (the opposite surface) 2 2nd chip (upper semiconductor chip) 2a major surface 2b pad (surface electrode) 2c backside 3 tape substrate (common wiring board) 3a wiring 3b connection electrode 3c chip supporting surface 3d backside (opposite) 3e bump lands 4 wiring film (upper wiring board) 4a wiring 4b connected electrodes 4c chip supporting surface 4d backside 5 underfill material 6 Au bump (protruding electrode) 7 upper Au bumps (upper protruding electrodes) 8 adhesive material 9 wire 10 sealing portion 11 of solder bumps (external terminals) 12 CSP (semiconductor device)

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 複数の半導体チップが積層されて組み込まれた半導体装置であって、 最下段に配置される半導体チップを突起電極を介してフリップチップ接続によって支持する共通配線基板と、 前記最下段の半導体チップのフリップチップ接続が行われる主面と反対側の面に配置され、前記最下段の半導体チップと積層配置される上段の半導体チップを上段の突起電極を介してフリップチップ接続によって支持する上段配線基板と、 前記上段の突起電極に配線を介して接続される前記上段配線基板の接続電極と、前記共通配線基板の接続電極とを接続するボンディング用のワイヤと、 前記共通配線基板のチップ支持面と反対側の面に配置される複数の外部端子とを有し、 積層配置された複数の前記半導体チップがそれぞれフェイスダウン実 1. A semiconductor device in which a plurality of semiconductor chips are incorporated are stacked, and the common wiring board for supporting the flip-chip connecting a semiconductor chip disposed on the bottom through the protruding electrodes, the lowermost is disposed major surface of the semiconductor chip flip-chip connections are made and on the opposite side to the support by flip-chip connecting the upper semiconductor chip are stacked with the bottom of the semiconductor chip through the upper protrusion electrodes and the upper wiring board, and the connection electrode of the upper wiring board which is connected via a wire to the top of the bump electrode, and wire bonding for connecting the connection electrodes of the common wiring board, the common wiring board chip and a plurality of external terminals arranged on the surface of the supporting surface opposite, stacked and a plurality of said semiconductor chip is face-down each real されるとともに、前記上段の半導体チップの表面電極と前記共通配線基板の前記接続電極とがフリップチップ接続およびワイヤボンディングによって接続され、前記最下段の半導体チップが前記共通配線基板にフリップチップ接続されていることを特徴とする半導体装置。 While being a surface electrode of the upper semiconductor chip and the connection electrodes of the common wiring board are connected by flip-chip connection and wire bonding, the are flip-chip connected to the bottom of the semiconductor chip is the common wiring board wherein a it is.
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