EP1547141A4 - Semiconductor multi-package module having wire bond interconnection between stacked packages - Google Patents

Semiconductor multi-package module having wire bond interconnection between stacked packages

Info

Publication number
EP1547141A4
EP1547141A4 EP03754585A EP03754585A EP1547141A4 EP 1547141 A4 EP1547141 A4 EP 1547141A4 EP 03754585 A EP03754585 A EP 03754585A EP 03754585 A EP03754585 A EP 03754585A EP 1547141 A4 EP1547141 A4 EP 1547141A4
Authority
EP
European Patent Office
Prior art keywords
wire bond
package module
semiconductor multi
stacked packages
bond interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP03754585A
Other languages
German (de)
French (fr)
Other versions
EP1547141A2 (en
Inventor
Marcos Karnezos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipPAC Inc
Original Assignee
ChipPAC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US632553 priority Critical
Priority to US632551 priority
Priority to US632568 priority
Priority to US632549 priority
Priority to US411590P priority
Priority to US41159002P priority
Priority to US10/632,551 priority patent/US6838761B2/en
Priority to US632550 priority
Priority to US10/632,549 priority patent/US7064426B2/en
Priority to US10/632,552 priority patent/US20040061213A1/en
Priority to US10/632,550 priority patent/US6972481B2/en
Priority to US10/632,568 priority patent/US7205647B2/en
Priority to US632552 priority
Priority to US10/632,553 priority patent/US7053476B2/en
Application filed by ChipPAC Inc filed Critical ChipPAC Inc
Priority to PCT/US2003/028919 priority patent/WO2004027823A2/en
Publication of EP1547141A2 publication Critical patent/EP1547141A2/en
Publication of EP1547141A4 publication Critical patent/EP1547141A4/en
Application status is Ceased legal-status Critical

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    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
EP03754585A 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages Ceased EP1547141A4 (en)

Priority Applications (15)

Application Number Priority Date Filing Date Title
US632553 1984-07-19
US632551 1990-12-21
US632568 1996-04-15
US632549 2000-08-04
US41159002P true 2002-09-17 2002-09-17
US411590P 2002-09-17
US632550 2003-08-02
US10/632,549 US7064426B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages
US10/632,552 US20040061213A1 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,550 US6972481B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US10/632,568 US7205647B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US632552 2003-08-02
US10/632,553 US7053476B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US10/632,551 US6838761B2 (en) 2002-09-17 2003-08-02 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
PCT/US2003/028919 WO2004027823A2 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

Publications (2)

Publication Number Publication Date
EP1547141A2 EP1547141A2 (en) 2005-06-29
EP1547141A4 true EP1547141A4 (en) 2010-02-24

Family

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EP03754585A Ceased EP1547141A4 (en) 2002-09-17 2003-09-15 Semiconductor multi-package module having wire bond interconnection between stacked packages

Country Status (6)

Country Link
EP (1) EP1547141A4 (en)
JP (3) JP4800625B2 (en)
KR (1) KR101166575B1 (en)
AU (1) AU2003272405A1 (en)
TW (3) TWI329918B (en)
WO (1) WO2004027823A2 (en)

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KR101563910B1 (en) * 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 EMI shielding device for semiconductor package and method for manufacturing the same
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JP2011181971A (en) 2011-09-15
JP2005539403A (en) 2005-12-22
TWI378548B (en) 2012-12-01
WO2004027823A3 (en) 2004-05-21
TW200419765A (en) 2004-10-01
TWI329918B (en) 2010-09-01
JP4800625B2 (en) 2011-10-26
JP2013211589A (en) 2013-10-10
AU2003272405A1 (en) 2004-04-08
TWI469301B (en) 2015-01-11
JP5602685B2 (en) 2014-10-08
TW201017853A (en) 2010-05-01
AU2003272405A8 (en) 2004-04-08
KR20050044925A (en) 2005-05-13
WO2004027823A2 (en) 2004-04-01
KR101166575B1 (en) 2012-07-18
EP1547141A2 (en) 2005-06-29
TW201131731A (en) 2011-09-16
JP5856103B2 (en) 2016-02-09

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